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[PATCH] MIPS/opcodes: microMIPS SWXC1 opcode encoding


Hi,

 The change below fixes a problem with the encoding of the microMIPS SWXC1 
opcode.  This instruction shares the major POOL32F opcode with LWXC1, 
however the two instructions have a different minor opcode (bits [8:0]) 
each:

* LWXC1 -> 001001000,

* SWXC1 -> 010001000.

In our opcode table however we use LWXC1's encoding for both.  This is 
trivially corrected; corresponding test suite updates are included.

 Since this change's scope is the MIPS target only I have limited testing 
to the mips-sde-elf and the mips-linux-gnu targets.  OK to apply?

 As this is a serious problem (silent code corruption) I'll backport it 
and apply to 2.23 once approved.

2012-09-06  Chao-ying Fu  <fu@mips.com>

	opcodes/
	* micromips-opc.c (micromips_opcodes): Correct the encoding of
	the "swxc1" instruction.

	gas/testsuite/
	* gas/mips/micromips.d: Correct the disassembly of SWXC1.
	* gas/mips/micromips-trap.d: Likewise.
	* gas/mips/micromips@24k-triple-stores-1.d: Likewise.
	* gas/mips/micromips@mips4-fp.d: Likewise.

  Maciej

binutils-umips-swxc1.diff
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips-trap.d
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/micromips-trap.d	2012-09-06 13:23:14.791098310 +0100
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips-trap.d	2012-09-06 13:25:38.661056835 +0100
@@ -6504,14 +6504,14 @@
 [ 0-9a-f]+:	41a1 1234 	lui	at,0x1234
 [ 0-9a-f]+:	0081 0950 	addu	at,at,a0
 [ 0-9a-f]+:	9861 5678 	swc1	\$f3,22136\(at\)
-[ 0-9a-f]+:	5400 0048 	lwxc1	\$f0,zero\(zero\)
-[ 0-9a-f]+:	5402 0048 	lwxc1	\$f0,zero\(v0\)
-[ 0-9a-f]+:	541f 0048 	lwxc1	\$f0,zero\(ra\)
-[ 0-9a-f]+:	545f 0048 	lwxc1	\$f0,v0\(ra\)
-[ 0-9a-f]+:	57ff 0048 	lwxc1	\$f0,ra\(ra\)
-[ 0-9a-f]+:	57ff 0848 	lwxc1	\$f1,ra\(ra\)
-[ 0-9a-f]+:	57ff 1048 	lwxc1	\$f2,ra\(ra\)
-[ 0-9a-f]+:	57ff f848 	lwxc1	\$f31,ra\(ra\)
+[ 0-9a-f]+:	5400 0088 	swxc1	\$f0,zero\(zero\)
+[ 0-9a-f]+:	5402 0088 	swxc1	\$f0,zero\(v0\)
+[ 0-9a-f]+:	541f 0088 	swxc1	\$f0,zero\(ra\)
+[ 0-9a-f]+:	545f 0088 	swxc1	\$f0,v0\(ra\)
+[ 0-9a-f]+:	57ff 0088 	swxc1	\$f0,ra\(ra\)
+[ 0-9a-f]+:	57ff 0888 	swxc1	\$f1,ra\(ra\)
+[ 0-9a-f]+:	57ff 1088 	swxc1	\$f2,ra\(ra\)
+[ 0-9a-f]+:	57ff f888 	swxc1	\$f31,ra\(ra\)
 [ 0-9a-f]+:	5401 233b 	trunc\.l\.s	\$f0,\$f1
 [ 0-9a-f]+:	57df 233b 	trunc\.l\.s	\$f30,\$f31
 [ 0-9a-f]+:	5442 233b 	trunc\.l\.s	\$f2,\$f2
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips.d
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/micromips.d	2012-09-06 13:23:14.791098310 +0100
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips.d	2012-09-06 13:25:38.671068774 +0100
@@ -6576,14 +6576,14 @@
 [ 0-9a-f]+:	41a1 1234 	lui	at,0x1234
 [ 0-9a-f]+:	0081 0950 	addu	at,at,a0
 [ 0-9a-f]+:	9861 5678 	swc1	\$f3,22136\(at\)
-[ 0-9a-f]+:	5400 0048 	lwxc1	\$f0,zero\(zero\)
-[ 0-9a-f]+:	5402 0048 	lwxc1	\$f0,zero\(v0\)
-[ 0-9a-f]+:	541f 0048 	lwxc1	\$f0,zero\(ra\)
-[ 0-9a-f]+:	545f 0048 	lwxc1	\$f0,v0\(ra\)
-[ 0-9a-f]+:	57ff 0048 	lwxc1	\$f0,ra\(ra\)
-[ 0-9a-f]+:	57ff 0848 	lwxc1	\$f1,ra\(ra\)
-[ 0-9a-f]+:	57ff 1048 	lwxc1	\$f2,ra\(ra\)
-[ 0-9a-f]+:	57ff f848 	lwxc1	\$f31,ra\(ra\)
+[ 0-9a-f]+:	5400 0088 	swxc1	\$f0,zero\(zero\)
+[ 0-9a-f]+:	5402 0088 	swxc1	\$f0,zero\(v0\)
+[ 0-9a-f]+:	541f 0088 	swxc1	\$f0,zero\(ra\)
+[ 0-9a-f]+:	545f 0088 	swxc1	\$f0,v0\(ra\)
+[ 0-9a-f]+:	57ff 0088 	swxc1	\$f0,ra\(ra\)
+[ 0-9a-f]+:	57ff 0888 	swxc1	\$f1,ra\(ra\)
+[ 0-9a-f]+:	57ff 1088 	swxc1	\$f2,ra\(ra\)
+[ 0-9a-f]+:	57ff f888 	swxc1	\$f31,ra\(ra\)
 [ 0-9a-f]+:	5401 233b 	trunc\.l\.s	\$f0,\$f1
 [ 0-9a-f]+:	57df 233b 	trunc\.l\.s	\$f30,\$f31
 [ 0-9a-f]+:	5442 233b 	trunc\.l\.s	\$f2,\$f2
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips@24k-triple-stores-1.d
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/micromips@24k-triple-stores-1.d	2011-12-12 23:49:55.845626534 +0000
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips@24k-triple-stores-1.d	2012-09-06 13:25:38.691020517 +0100
@@ -58,11 +58,11 @@
  *[0-9a-f]+:	209d a010 	sdc2	\$4,16\(sp\)
  *[0-9a-f]+:	20bd a018 	sdc2	\$5,24\(sp\)
  *[0-9a-f]+:	20dd a020 	sdc2	\$6,32\(sp\)
- *[0-9a-f]+:	5528 0048 	lwxc1	\$f0,t1\(t0\)
- *[0-9a-f]+:	5548 0848 	lwxc1	\$f1,t2\(t0\)
- *[0-9a-f]+:	5568 1048 	lwxc1	\$f2,t3\(t0\)
- *[0-9a-f]+:	5588 1848 	lwxc1	\$f3,t4\(t0\)
- *[0-9a-f]+:	55a8 2048 	lwxc1	\$f4,t5\(t0\)
+ *[0-9a-f]+:	5528 0088 	swxc1	\$f0,t1\(t0\)
+ *[0-9a-f]+:	5548 0888 	swxc1	\$f1,t2\(t0\)
+ *[0-9a-f]+:	5568 1088 	swxc1	\$f2,t3\(t0\)
+ *[0-9a-f]+:	5588 1888 	swxc1	\$f3,t4\(t0\)
+ *[0-9a-f]+:	55a8 2088 	swxc1	\$f4,t5\(t0\)
  *[0-9a-f]+:	5528 0108 	sdxc1	\$f0,t1\(t0\)
  *[0-9a-f]+:	5548 1108 	sdxc1	\$f2,t2\(t0\)
  *[0-9a-f]+:	5568 2108 	sdxc1	\$f4,t3\(t0\)
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips@mips4-fp.d
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/micromips@mips4-fp.d	2011-10-05 17:51:41.005866744 +0100
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips@mips4-fp.d	2012-09-06 13:25:38.710998504 +0100
@@ -45,6 +45,6 @@
 [0-9a-f]+ <[^>]*> 5486 423b 	rsqrt\.d	\$f4,\$f6
 [0-9a-f]+ <[^>]*> 5486 023b 	rsqrt\.s	\$f4,\$f6
 [0-9a-f]+ <[^>]*> 5485 2108 	sdxc1	\$f4,a0\(a1\)
-[0-9a-f]+ <[^>]*> 5485 2048 	lwxc1	\$f4,a0\(a1\)
+[0-9a-f]+ <[^>]*> 5485 2088 	swxc1	\$f4,a0\(a1\)
 [0-9a-f]+ <[^>]*> 0c00      	nop
 	\.\.\.
Index: binutils-fsf-trunk-quilt/opcodes/micromips-opc.c
===================================================================
--- binutils-fsf-trunk-quilt.orig/opcodes/micromips-opc.c	2012-09-06 13:23:14.781052807 +0100
+++ binutils-fsf-trunk-quilt/opcodes/micromips-opc.c	2012-09-06 13:25:38.740967121 +0100
@@ -911,7 +911,7 @@ const struct mips_opcode micromips_opcod
 {"invalidate", "t,~(b)",0x60009000, 0xfc00f000,	SM|RD_b|RD_t,		0,		I1	}, /* same */
 {"invalidate", "t,o(b)",0,    (int) M_SWR_OB,	INSN_MACRO,		0,		I1	},
 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I1	},
-{"swxc1",   "D,t(b)",	0x54000048, 0xfc0007ff,	SM|RD_t|RD_b|FP_S,	RD_D,		I1	},
+{"swxc1",   "D,t(b)",	0x54000088, 0xfc0007ff,	SM|RD_t|RD_b|FP_S,	RD_D,		I1	},
 {"sync_acquire", "",	0x00116b7c, 0xffffffff,	NODS,			0,		I1	},
 {"sync_mb", "",		0x00106b7c, 0xffffffff,	NODS,			0,		I1	},
 {"sync_release", "",	0x00126b7c, 0xffffffff,	NODS,			0,		I1	},


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