Re: [PATCH ARM/THUMB1] unified syntax MOV with both low register emitting unpredictable code

[Richard Earnshaw <rearnsha at arm dot com>]

On 15/11/11 23:11, Thomas Klein wrote:
> On 11/15/11 15:13, Matthew Gretton-Dann wrote:
>> On 14/11/11 20:21, Thomas Klein wrote:
>>> +        if (low_regs&&  !ARM_CPU_HAS_FEATURE (selected_cpu, 
>>> arm_ext_v6t2))
>>
>> This test is incorrect - you want to check for arm_ext_v6, as all v6 
>> variants whether Thumb-1 or Thumb-2 allow low registers in this 
>> instruction.
>>
>>> +          {
>>
>> Some regression tests would be good here.
> 
> Correction and tests attached.
> Is this OK.
> 

This is incorrect.  There is no pre-v6 Thumb1 'MOV lo, lo' instruction
in unified syntax and the assembler should fault it; it shouldn't try to
use a flag setting insn.

R.

> Regards
>    Thomas
> 
> 
> 
> diff.out
> 
> 
> Index: gas/config/tc-arm.c
> ===================================================================
> RCS file: /cvs/src/src/gas/config/tc-arm.c,v
> retrieving revision 1.504
> diff -u -p -r1.504 tc-arm.c
> --- gas/config/tc-arm.c	7 Nov 2011 16:20:47 -0000	1.504
> +++ gas/config/tc-arm.c	15 Nov 2011 22:11:53 -0000
> @@ -10913,10 +10913,24 @@ do_t_mov_cmp (void)
>  	switch (inst.instruction)
>  	  {
>  	  case T_MNEM_mov:
> -	    inst.instruction = T_OPCODE_MOV_HR;
> -	    inst.instruction |= (Rn & 0x8) << 4;
> -	    inst.instruction |= (Rn & 0x7);
> -	    inst.instruction |= Rm << 3;
> +	    if (low_regs && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
> +	      {
> +		 as_warn (_("MOV r%u,r%u is not permitted on this architecture "
> +			    "using ADDS r%u,r%u,#0 instead"),Rn,Rm,Rn,Rm);
> +		 /* In v4t or v5t a move of two lowregs produces
> +		    unpredictable results. Encode this the same way as in
> +		    non unified syntax.*/
> +		 inst.instruction = T_OPCODE_ADD_I3;
> +		 inst.instruction |= Rn;
> +		 inst.instruction |= Rm << 3;
> +	      }
> +	    else
> +	      {
> +		 inst.instruction = T_OPCODE_MOV_HR;
> +		 inst.instruction |= (Rn & 0x8) << 4;
> +		 inst.instruction |= (Rn & 0x7);
> +		 inst.instruction |= Rm << 3;
> +	      }
>  	    break;
>  
>  	  case T_MNEM_movs:
> Index: gas/testsuite/gas/arm/thumb1_unified.d
> ===================================================================
> RCS file: /cvs/src/src/gas/testsuite/gas/arm/thumb1_unified.d,v
> retrieving revision 1.3
> diff -u -p -r1.3 thumb1_unified.d
> --- gas/testsuite/gas/arm/thumb1_unified.d	30 Jun 2009 11:57:05 -0000	1.3
> +++ gas/testsuite/gas/arm/thumb1_unified.d	15 Nov 2011 22:11:54 -0000
> @@ -5,6 +5,7 @@
>  
>  Disassembly of section .text:
>  0[0-9a-f]+ <[^>]+> 200c      	movs	r0, #12
> +0[0-9a-f]+ <[^>]+> 1c1a      	adds	r2, r3, #0
>  0[0-9a-f]+ <[^>]+> 1cd1      	adds	r1, r2, #3
>  0[0-9a-f]+ <[^>]+> 1ed1      	subs	r1, r2, #3
>  0[0-9a-f]+ <[^>]+> 3364      	adds	r3, #100.*
> @@ -18,3 +19,6 @@ Disassembly of section .text:
>  0[0-9a-f]+ <[^>]+> b081      	sub	sp, #4
>  0[0-9a-f]+ <[^>]+> af01      	add	r7, sp, #4
>  0[0-9a-f]+ <[^>]+> 4251      	negs	r1, r2
> +0[0-9a-f]+ <[^>]+> 46c0      	nop.*
> +0[0-9a-f]+ <[^>]+> 461a      	mov	r2, r3
> +0[0-9a-f]+ <[^>]+> 46c0      	nop.*
> Index: gas/testsuite/gas/arm/thumb1_unified.s
> ===================================================================
> RCS file: /cvs/src/src/gas/testsuite/gas/arm/thumb1_unified.s,v
> retrieving revision 1.1
> diff -u -p -r1.1 thumb1_unified.s
> --- gas/testsuite/gas/arm/thumb1_unified.s	19 Apr 2007 17:08:21 -0000	1.1
> +++ gas/testsuite/gas/arm/thumb1_unified.s	15 Nov 2011 22:11:54 -0000
> @@ -4,6 +4,7 @@
>  .thumb
>  foo:
>  movs r0, #12
> +mov r2, r3
>  adds r1, r2, #3
>  subs r1, r2, #3
>  adds r3, r3, #0x64
> @@ -21,5 +22,10 @@ add r7, sp, #4
>  rsbs r1, r2, #0
>  
>  .align 2
> +
> +.arch armv6
> +.thumb
>  bar:
> +mov r2, r3
> +.align 2
>  
> 
> 
> ChangeLog
> 
> 
> 2011-11-15  Thomas Klein  <th.r.klein@web.de>
> 
> 	* config/tc-arm.c (do_t_mov_cmp): Encode low register mov for arch v4t
> 	and v5t the same way as in non unified syntax form.