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Thanks, Catherine
Attachment:
include.cl
Description: Text document
Index: elf/ppc.h
===================================================================
RCS file: /cvs/src/src/include/elf/ppc.h,v
retrieving revision 1.30
diff -u -r1.30 ppc.h
--- elf/ppc.h 11 Jul 2011 15:03:08 -0000 1.30
+++ elf/ppc.h 10 Aug 2011 20:17:34 -0000
@@ -131,6 +131,25 @@
RELOC_NUMBER (R_PPC_EMB_BIT_FLD, 115)
RELOC_NUMBER (R_PPC_EMB_RELSDA, 116)
+/* PowerPC VLE relocations. */
+ RELOC_NUMBER (R_PPC_VLE_REL8, 216)
+ RELOC_NUMBER (R_PPC_VLE_REL15, 217)
+ RELOC_NUMBER (R_PPC_VLE_REL24, 218)
+ RELOC_NUMBER (R_PPC_VLE_LO16A, 219)
+ RELOC_NUMBER (R_PPC_VLE_LO16D, 220)
+ RELOC_NUMBER (R_PPC_VLE_HI16A, 221)
+ RELOC_NUMBER (R_PPC_VLE_HI16D, 222)
+ RELOC_NUMBER (R_PPC_VLE_HA16A, 223)
+ RELOC_NUMBER (R_PPC_VLE_HA16D, 224)
+ RELOC_NUMBER (R_PPC_VLE_SDA21, 225)
+ RELOC_NUMBER (R_PPC_VLE_SDA21_LO, 226)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_LO16A, 227)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_LO16D, 228)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16A, 229)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16D, 230)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16A, 231)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16D, 232)
+
/* Support STT_GNU_IFUNC plt calls. */
RELOC_NUMBER (R_PPC_IRELATIVE, 248)
@@ -166,9 +185,11 @@
#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag. */
#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib flag. */
-/* This bit is reserved by BFD for processor specific stuff. Name
- it properly so that we can easily stay consistent elsewhere. */
-#define SEC_PPC_VLE SEC_TIC54X_BLOCK
+/* Processor specific program headers, p_flags field. */
+#define PF_PPC_VLE 0x10000000 /* PowerPC VLE. */
+
+/* Processor specific section headers, sh_flags field. */
+#define SHF_PPC_VLE 0x10000000 /* PowerPC VLE text section. */
/* Processor specific section headers, sh_type field. */
Index: opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.42
diff -u -r1.42 ppc.h
--- opcode/ppc.h 3 Jul 2010 06:51:53 -0000 1.42
+++ opcode/ppc.h 10 Aug 2011 20:17:34 -0000
@@ -174,8 +174,17 @@
/* Opcode which is supported by the e500 family */
#define PPC_OPCODE_E500 0x100000000ull
+/* Opcode which is supported by the VLE extension. */
+#define PPC_OPCODE_VLE 0x200000000ull
+
+/* A macro to determine the shift amount to be used in PPC_OP. */
+#define PPC_OP_SA(m) (((m) <= 0xffff) ? 10 : 26)
+
+/* A macro to determine if the instruction is a 2-byte VLE insn. */
+#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
+
/* A macro to extract the major opcode from an instruction. */
-#define PPC_OP(i) (((i) >> 26) & 0x3f)
+#define PPC_OP(i, s) (((i) >> s) & 0x3f)
/* The operands table is an array of struct powerpc_operand. */
@@ -184,16 +193,22 @@
/* A bitmask of bits in the operand. */
unsigned int bitm;
- /* How far the operand is left shifted in the instruction.
- -1 to indicate that BITM and SHIFT cannot be used to determine
- where the operand goes in the insn. */
+ /* The shift operation to be applied to the operand. No shift
+ is made if this is zero. For positive values, the operand
+ is shifted left by SHIFT. For negative values, the operand
+ is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
+ that BITM and SHIFT cannot be used to determine where the
+ operand goes in the insn. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
- i |= (op & o->bitm) << o->shift;
+ if (o->shift >= 0)
+ i |= (op & o->bitm) << o->shift;
+ else
+ i |= (op & o->bitm) >> -o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the operand value).
@@ -211,7 +226,10 @@
extract this operand type from an instruction, check this field.
If it is NULL, compute
- op = (i >> o->shift) & o->bitm;
+ if (o->shift >= 0)
+ op = (i >> o->shift) & o->bitm;
+ else
+ op = (i << -o->shift) & o->bitm;
if ((o->flags & PPC_OPERAND_SIGNED) != 0)
sign_extend (op);
(i is the instruction, o is a pointer to this structure, and op
@@ -235,6 +253,11 @@
extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;
+/* Use with the shift field of a struct powerpc_operand to indicate
+ that BITM and SHIFT cannot be used to determine where the operand
+ goes in the insn. */
+#define PPC_OPSHIFT_INV (-1 << 31)
+
/* Values defined for the flags field of a struct powerpc_operand. */
/* This operand takes signed values. */
@@ -268,7 +291,7 @@
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
-#define PPC_OPERAND_CR (0x10)
+#define PPC_OPERAND_CR_BIT (0x10)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
@@ -333,6 +356,10 @@
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
+
+/* This is a CR FIELD that does not use symbolic names. */
+#define PPC_OPERAND_CR_REG (0x200000)
+
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
Attachment:
gas.cl
Description: Text document
Index: NEWS
===================================================================
RCS file: /cvs/src/src/gas/NEWS,v
retrieving revision 1.118
diff -u -r1.118 NEWS
--- NEWS 15 Jun 2011 09:12:09 -0000 1.118
+++ NEWS 12 Aug 2011 17:39:49 -0000
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for the VLE extension to the PowerPC architecture.
+
* Add support for the Tilera TILEPRO and TILE-Gx architectures.
Changes in 2.21:
Index: config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.180
diff -u -r1.180 tc-ppc.c
--- config/tc-ppc.c 14 Jun 2011 09:03:51 -0000 1.180
+++ config/tc-ppc.c 12 Aug 2011 17:39:50 -0000
@@ -61,17 +61,44 @@
/* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST,
HIGHESTA. */
-/* #lo(value) denotes the least significant 16 bits of the indicated. */
+/* #lo(value) denotes the least significant 16 bits
+ of the indicated value. */
#define PPC_LO(v) ((v) & 0xffff)
+/* Split the indicated value with the msbs in bits 11-15
+ and the lsbs in bits 21-31. */
+#define PPC_VLE_SPLIT16A(v) ((v & 0xf800) << 11) | (v & 0x7ff)
+
+/* Split the indicated value with the msbs in bits 6-10
+ and the lsbs in bits 21-31. */
+#define PPC_VLE_SPLIT16D(v) ((v & 0xf800) << 5) | (v & 0x7ff)
+
+/* #lo(value) denotes the lsb 16 bits in split16a format. */
+#define PPC_VLE_LO16A(v) PPC_VLE_SPLIT16A(PPC_LO(v))
+
+/* #lo(value) denotes the lsb 16 bits in split16d format. */
+#define PPC_VLE_LO16D(v) PPC_VLE_SPLIT16D(PPC_LO(v))
+
/* #hi(value) denotes bits 16 through 31 of the indicated value. */
#define PPC_HI(v) (((v) >> 16) & 0xffff)
+/* #lo(value) denotes the msb 16 bits in split16a format. */
+#define PPC_VLE_HI16A(v) PPC_VLE_SPLIT16A(PPC_HI(v))
+
+/* #lo(value) denotes the msb 16 bits in split16d format. */
+#define PPC_VLE_HI16D(v) PPC_VLE_SPLIT16D(PPC_HI(v))
+
/* #ha(value) denotes the high adjusted value: bits 16 through 31 of
the indicated value, compensating for #lo() being treated as a
signed number. */
#define PPC_HA(v) PPC_HI ((v) + 0x8000)
+/* #ha(value) denotes the high adjusted value in split16a format. */
+#define PPC_VLE_HA16A(v) PPC_VLE_SPLIT16A(PPC_HA(v))
+
+/* #ha(value) denotes the high adjusted value in split16d format. */
+#define PPC_VLE_HA16D(v) PPC_VLE_SPLIT16D(PPC_HA(v))
+
/* #higher(value) denotes bits 32 through 47 of the indicated value. */
#define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff)
@@ -1038,6 +1065,7 @@
#define PPC_APUINFO_SPE 0x100
#define PPC_APUINFO_EFS 0x101
#define PPC_APUINFO_BRLOCK 0x102
+#define PPC_APUINFO_VLE 0x104
/*
* We keep a list of APUinfo
@@ -1059,6 +1087,35 @@
};
const size_t md_longopts_size = sizeof (md_longopts);
+/* Convert the target integer stored in N bytes in BUF to a host
+ integer, returning that value. */
+
+static valueT
+md_chars_to_number (char *buf, int n)
+{
+ valueT result = 0;
+ unsigned char *p = (unsigned char *) buf;
+
+ if (target_big_endian)
+ {
+ while (n--)
+ {
+ result <<= 8;
+ result |= (*p++ & 0xff);
+ }
+ }
+ else
+ {
+ while (n--)
+ {
+ result <<= 8;
+ result |= (p[n] & 0xff);
+ }
+ }
+
+ return result;
+}
+
int
md_parse_option (int c, char *arg)
{
@@ -1079,6 +1136,8 @@
{
target_big_endian = 0;
set_target_endian = 1;
+ if (ppc_cpu & PPC_OPCODE_VLE)
+ as_bad (_("The use of -mvle requires big endian."));
}
else
return 0;
@@ -1127,7 +1186,11 @@
case 'm':
if ((new_cpu = ppc_parse_cpu (ppc_cpu, arg)) != 0)
- ppc_cpu = new_cpu;
+ {
+ ppc_cpu = new_cpu;
+ if (set_target_endian && target_big_endian == 0)
+ as_bad (_("The use of -mvle requires big endian."));
+ }
else if (strcmp (arg, "regnames") == 0)
reg_names_p = TRUE;
@@ -1160,6 +1223,8 @@
{
target_big_endian = 0;
set_target_endian = 1;
+ if (ppc_cpu & PPC_OPCODE_VLE)
+ as_bad (_("The use of -mvle requires big endian."));
}
else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0)
@@ -1266,6 +1331,7 @@
-me500mc, generate code for Freescale e500mc core complex\n\
-me500mc64, generate code for Freescale e500mc64 core complex\n\
-mspe generate code for Motorola SPE instructions\n\
+-mvle generate code for Freescale VLE instructions\n\
-mtitan generate code for AppliedMicro Titan core complex\n\
-mregnames Allow symbolic names for registers\n\
-mno-regnames Do not allow symbolic names for registers\n"));
@@ -1324,7 +1390,9 @@
const char *default_cpu = TARGET_CPU;
ppc_set_cpu ();
- if ((ppc_cpu & PPC_OPCODE_PPC) != 0)
+ if ((ppc_cpu & PPC_OPCODE_PPC) !=0)
+ return bfd_arch_powerpc;
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
return bfd_arch_powerpc;
else if ((ppc_cpu & PPC_OPCODE_POWER) != 0)
return bfd_arch_rs6000;
@@ -1349,6 +1417,8 @@
return bfd_mach_rs6k;
else if (ppc_cpu & PPC_OPCODE_TITAN)
return bfd_mach_ppc_titan;
+ else if (ppc_cpu & PPC_OPCODE_VLE)
+ return bfd_mach_ppc_vle;
else
return bfd_mach_ppc;
}
@@ -1441,10 +1511,21 @@
if (op != powerpc_opcodes)
{
+ int old_opcode = PPC_OP (op[-1].opcode,
+ PPC_OP_SA (op[-1].mask));
+ int new_opcode = PPC_OP (op[0].opcode,
+ PPC_OP_SA (op[0].mask));
+
+#ifdef PRINT_OPCODE_TABLE
+ printf (
+ "%-14s\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n",
+ op->name, (unsigned int) new_opcode, (unsigned int) op->opcode,
+ (unsigned int) op->mask, (long long unsigned int) op->flags);
+#endif
/* The major opcodes had better be sorted. Code in the
disassembler assumes the insns are sorted according to
major opcode. */
- if (PPC_OP (op[0].opcode) < PPC_OP (op[-1].opcode))
+ if (new_opcode < old_opcode)
{
as_bad (_("major opcode is not sorted for %s"),
op->name);
@@ -1507,9 +1588,14 @@
else
{
const struct powerpc_operand *operand = &powerpc_operands[*o];
- if (operand->shift >= 0)
+ if (operand->shift != PPC_OPSHIFT_INV)
{
- unsigned long mask = operand->bitm << operand->shift;
+ unsigned long mask;
+
+ if (operand->shift >= 0)
+ mask = operand->bitm << operand->shift;
+ else
+ mask = operand->bitm >> -operand->shift;
if (omask & mask)
{
as_bad (_("operand %d overlap in %s"),
@@ -1739,8 +1825,10 @@
if (errmsg != (const char *) NULL)
as_bad_where (file, line, "%s", errmsg);
}
- else
+ else if (operand->shift >= 0)
insn |= ((long) val & operand->bitm) << operand->shift;
+ else
+ insn |= ((long) val & operand->bitm) >> -operand->shift;
return insn;
}
@@ -1822,6 +1910,9 @@
MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC),
MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL),
MAP32 ("sdarel", BFD_RELOC_GPREL16),
+ MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A),
+ MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A),
+ MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A),
MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32),
MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16),
MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO),
@@ -1831,6 +1922,7 @@
MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL),
MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16),
MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21),
+ MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO),
MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF),
MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16),
MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO),
@@ -2367,6 +2459,22 @@
#define MAX_INSN_FIXUPS (5)
+/* Form I16L. */
+#define E_OR2I_INSN 0x7000C000
+#define E_AND2I_DOT_INSN 0x7000C800
+#define E_OR2IS_INSN 0x7000D000
+#define E_LIS_INSN 0x7000E000
+#define E_AND2IS_DOT_INSN 0x7000E800
+
+/* Form I16A. */
+#define E_ADD2I_DOT_INSN 0x70008800
+#define E_ADD2IS_INSN 0x70009000
+#define E_CMP16I_INSN 0x70009800
+#define E_MULL2I_INSN 0x7000A000
+#define E_CMPL16I_INSN 0x7000A800
+#define E_CMPH16I_INSN 0x7000B000
+#define E_CMPHL16I_INSN 0x7000B800
+
/* This routine is called for each instruction to be assembled. */
void
@@ -2384,6 +2492,7 @@
char *f;
int addr_mod;
int i;
+ unsigned int insn_length;
#ifdef OBJ_ELF
bfd_reloc_code_real_type reloc;
#endif
@@ -2633,12 +2742,15 @@
else
#endif /* TE_PE */
{
- if ((reg_names_p && (operand->flags & PPC_OPERAND_CR) != 0)
+ if ((reg_names_p
+ && (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
+ || ((operand->flags & PPC_OPERAND_CR_REG) != 0)))
|| !register_name (&ex))
{
char save_lex = lex_type['%'];
- if ((operand->flags & PPC_OPERAND_CR) != 0)
+ if (((operand->flags & PPC_OPERAND_CR_REG) != 0)
+ || (operand->flags & PPC_OPERAND_CR_BIT) != 0)
{
cr_operand = TRUE;
lex_type['%'] |= LEX_BEGIN_NAME;
@@ -2806,6 +2918,73 @@
break;
}
+ /* If VLE-mode convert LO/HI/HA relocations. */
+ if (opcode->flags & PPC_OPCODE_VLE)
+ {
+ int tmp_insn = insn & opcode->mask;
+
+ int use_d_reloc = (tmp_insn == E_OR2I_INSN
+ || tmp_insn == E_AND2I_DOT_INSN
+ || tmp_insn == E_OR2IS_INSN
+ || tmp_insn == E_LIS_INSN
+ || tmp_insn == E_AND2IS_DOT_INSN);
+
+
+ int use_a_reloc = (tmp_insn == E_ADD2I_DOT_INSN
+ || tmp_insn == E_ADD2IS_INSN
+ || tmp_insn == E_CMP16I_INSN
+ || tmp_insn == E_MULL2I_INSN
+ || tmp_insn == E_CMPL16I_INSN
+ || tmp_insn == E_CMPH16I_INSN
+ || tmp_insn == E_CMPHL16I_INSN);
+
+ switch (reloc)
+ {
+ default:
+ break;
+
+ case BFD_RELOC_PPC_EMB_SDA21:
+ reloc = BFD_RELOC_PPC_VLE_SDA21;
+ break;
+
+ case BFD_RELOC_LO16:
+ if (use_d_reloc)
+ reloc = BFD_RELOC_PPC_VLE_LO16D;
+ else if (use_a_reloc)
+ reloc = BFD_RELOC_PPC_VLE_LO16A;
+ break;
+
+ case BFD_RELOC_HI16:
+ if (use_d_reloc)
+ reloc = BFD_RELOC_PPC_VLE_HI16D;
+ else if (use_a_reloc)
+ reloc = BFD_RELOC_PPC_VLE_HI16A;
+ break;
+
+ case BFD_RELOC_HI16_S:
+ if (use_d_reloc)
+ reloc = BFD_RELOC_PPC_VLE_HA16D;
+ else if (use_a_reloc)
+ reloc = BFD_RELOC_PPC_VLE_HA16A;
+ break;
+
+ case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
+ if (use_d_reloc)
+ reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D;
+ break;
+
+ case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
+ if (use_d_reloc)
+ reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D;
+ break;
+
+ case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
+ if (use_d_reloc)
+ reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D;
+ break;
+ }
+ }
+
/* For the absolute forms of branches, convert the PC
relative form back into the absolute. */
if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
@@ -2971,7 +3150,7 @@
#ifdef OBJ_ELF
/* Do we need/want a APUinfo section? */
- if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC)) != 0)
+ if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0)
{
/* These are all version "1". */
if (opcode->flags & PPC_OPCODE_SPE)
@@ -2988,20 +3167,41 @@
ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1);
if (opcode->flags & PPC_OPCODE_RFMCI)
ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1);
+ if (opcode->flags & PPC_OPCODE_VLE)
+ ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
}
#endif
/* Write out the instruction. */
- f = frag_more (4);
- addr_mod = frag_now_fix () & 3;
+ /* Differentiate between two and four byte insns. */
+ if (ppc_mach () == bfd_mach_ppc_vle)
+ {
+ if (PPC_OP_SE_VLE (insn))
+ insn_length = 2;
+ else
+ insn_length = 4;
+ addr_mod = frag_now_fix () & 1;
+ }
+ else
+ {
+ insn_length = 4;
+ addr_mod = frag_now_fix () & 3;
+ }
+ /* VLE instructions may be 2-byte aligned. */
+ f = frag_more (insn_length);
if (frag_now->has_code && frag_now->insn_addr != addr_mod)
- as_bad (_("instruction address is not a multiple of 4"));
+ {
+ if (ppc_mach() == bfd_mach_ppc_vle)
+ as_bad (_("instruction address is not a multiple of 2"));
+ else
+ as_bad (_("instruction address is not a multiple of 4"));
+ }
frag_now->insn_addr = addr_mod;
frag_now->has_code = 1;
- md_number_to_chars (f, insn, 4);
+ md_number_to_chars (f, insn, insn_length);
#ifdef OBJ_ELF
- dwarf2_emit_insn (4);
+ dwarf2_emit_insn (insn_length);
#endif
/* Create any fixups. At this point we do not use a
@@ -3045,6 +3245,12 @@
case BFD_RELOC_LO16:
case BFD_RELOC_HI16:
case BFD_RELOC_HI16_S:
+ case BFD_RELOC_PPC_VLE_LO16A:
+ case BFD_RELOC_PPC_VLE_LO16D:
+ case BFD_RELOC_PPC_VLE_HI16A:
+ case BFD_RELOC_PPC_VLE_HI16D:
+ case BFD_RELOC_PPC_VLE_HA16A:
+ case BFD_RELOC_PPC_VLE_HA16D:
#ifdef OBJ_ELF
case BFD_RELOC_PPC64_HIGHER:
case BFD_RELOC_PPC64_HIGHER_S:
@@ -3064,7 +3270,7 @@
operand = &powerpc_operands[fixups[i].opindex];
fix_new_exp (frag_now,
f - frag_now->fr_literal,
- 4,
+ insn_length,
&fixups[i].exp,
(operand->flags & PPC_OPERAND_RELATIVE) != 0,
((bfd_reloc_code_real_type)
@@ -5949,6 +6155,24 @@
}
#endif
+void
+ppc_frag_check (struct frag *fragP)
+{
+ if (!fragP->has_code)
+ return;
+
+ if (ppc_mach() == bfd_mach_ppc_vle)
+ {
+ if (((fragP->fr_address + fragP->insn_addr) & 1) != 0)
+ as_bad (_("instruction address is not a multiple of 2"));
+ }
+ else
+ {
+ if (((fragP->fr_address + fragP->insn_addr) & 3) != 0)
+ as_bad (_("instruction address is not a multiple of 4"));
+ }
+}
+
/* Implement HANDLE_ALIGN. This writes the NOP pattern into an
rs_align_code frag. */
@@ -5958,7 +6182,14 @@
valueT count = (fragP->fr_next->fr_address
- (fragP->fr_address + fragP->fr_fix));
- if (count != 0 && (count & 3) == 0)
+ if (ppc_mach() == bfd_mach_ppc_vle && count != 0 && (count & 1) == 0)
+ {
+ char *dest = fragP->fr_literal + fragP->fr_fix;
+
+ fragP->fr_var = 2;
+ md_number_to_chars (dest, 0x4400, 2);
+ }
+ else if (count != 0 && (count & 3) == 0)
{
char *dest = fragP->fr_literal + fragP->fr_fix;
@@ -6107,16 +6338,36 @@
value, and stuff the instruction back again. */
where = fixP->fx_frag->fr_literal + fixP->fx_where;
if (target_big_endian)
- insn = bfd_getb32 ((unsigned char *) where);
+ {
+ if (fixP->fx_size == 4)
+ insn = bfd_getb32 ((unsigned char *) where);
+ else
+ insn = bfd_getb16 ((unsigned char *) where);
+ }
else
- insn = bfd_getl32 ((unsigned char *) where);
+ {
+ if (fixP->fx_size == 4)
+ insn = bfd_getl32 ((unsigned char *) where);
+ else
+ insn = bfd_getl16 ((unsigned char *) where);
+ }
insn = ppc_insert_operand (insn, operand, (offsetT) value,
fixP->tc_fix_data.ppc_cpu,
fixP->fx_file, fixP->fx_line);
if (target_big_endian)
- bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
+ {
+ if (fixP->fx_size == 4)
+ bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
+ else
+ bfd_putb16 ((bfd_vma) insn, (unsigned char *) where);
+ }
else
- bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
+ {
+ if (fixP->fx_size == 4)
+ bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
+ else
+ bfd_putl16 ((bfd_vma) insn, (unsigned char *) where);
+ }
if (fixP->fx_done)
/* Nothing else to do here. */
@@ -6142,6 +6393,18 @@
fixP->fx_where += 2;
#endif
}
+ else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
+ && operand->bitm == 0x1fe
+ && operand->shift == -1)
+ fixP->fx_r_type = BFD_RELOC_PPC_VLE_REL8;
+ else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
+ && operand->bitm == 0xfffe
+ && operand->shift == 0)
+ fixP->fx_r_type = BFD_RELOC_PPC_VLE_REL15;
+ else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
+ && operand->bitm == 0x1fffffe
+ && operand->shift == 0)
+ fixP->fx_r_type = BFD_RELOC_PPC_VLE_REL24;
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0
&& operand->bitm == 0x3fffffc
&& operand->shift == 0)
@@ -6326,6 +6589,91 @@
PPC_HA (value), 2);
break;
+ case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
+ case BFD_RELOC_PPC_VLE_LO16A:
+ {
+ int tval = PPC_VLE_LO16A (value);
+ valueT oldval = md_chars_to_number (
+ fixP->fx_frag->fr_literal + fixP->fx_where, 4);
+ md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+ (oldval | tval), 4);
+ }
+ break;
+
+ case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
+ case BFD_RELOC_PPC_VLE_LO16D:
+ {
+ int tval = PPC_VLE_LO16D (value);
+ valueT oldval = md_chars_to_number (
+ fixP->fx_frag->fr_literal + fixP->fx_where, 4);
+ md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+ (oldval | tval), 4);
+ }
+ break;
+
+ case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
+ case BFD_RELOC_PPC_VLE_HI16A:
+ {
+ int tval = PPC_VLE_HI16A (value);
+ valueT oldval = md_chars_to_number (
+ fixP->fx_frag->fr_literal + fixP->fx_where, 4);
+ md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+ (oldval | tval), 4);
+ }
+ break;
+
+ case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
+ case BFD_RELOC_PPC_VLE_HI16D:
+ {
+ int tval = PPC_VLE_HI16D (value);
+ valueT oldval = md_chars_to_number (
+ fixP->fx_frag->fr_literal + fixP->fx_where, 4);
+ md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+ (oldval | tval), 4);
+ }
+ break;
+
+ case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
+ case BFD_RELOC_PPC_VLE_HA16A:
+ {
+ int tval = PPC_VLE_HA16A (value);
+ valueT oldval = md_chars_to_number (
+ fixP->fx_frag->fr_literal + fixP->fx_where, 4);
+ md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+ (oldval | tval), 4);
+ }
+ break;
+
+ case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
+ case BFD_RELOC_PPC_VLE_HA16D:
+ {
+ int tval = PPC_VLE_HA16D (value);
+ valueT oldval = md_chars_to_number (
+ fixP->fx_frag->fr_literal + fixP->fx_where, 4);
+ md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+ (oldval | tval), 4);
+ }
+ break;
+
+ case BFD_RELOC_PPC_VLE_SDA21_LO:
+ {
+ int tval = PPC_LO (value);
+ valueT oldval = md_chars_to_number (
+ fixP->fx_frag->fr_literal + fixP->fx_where, 4);
+ md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+ (oldval | tval), 4);
+ }
+ break;
+
+ case BFD_RELOC_PPC_VLE_SDA21:
+ {
+ valueT oldval = md_chars_to_number (
+ fixP->fx_frag->fr_literal + fixP->fx_where, 4);
+ md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+ (oldval | value), 4);
+ }
+ break;
+
#ifdef OBJ_XCOFF
case BFD_RELOC_NONE:
break;
Index: config/tc-ppc.h
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.h,v
retrieving revision 1.44
diff -u -r1.44 tc-ppc.h
--- config/tc-ppc.h 14 Jun 2011 09:03:51 -0000 1.44
+++ config/tc-ppc.h 12 Aug 2011 17:39:50 -0000
@@ -84,14 +84,11 @@
ppc_handle_align (FRAGP);
extern void ppc_handle_align (struct frag *);
+extern void ppc_frag_check (struct frag *);
#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
-#define md_frag_check(FRAGP) \
- if ((FRAGP)->has_code \
- && (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 3) != 0) \
- as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line, \
- _("instruction address is not a multiple of 4"));
+#define md_frag_check(FRAGP) ppc_frag_check (FRAGP)
/* Arrange to store the value of ppc_cpu at the site of a fixup
for later use in md_apply_fix. */
@@ -273,6 +270,6 @@
extern int ppc_cie_data_alignment;
-#define DWARF2_LINE_MIN_INSN_LENGTH 4
+#define DWARF2_LINE_MIN_INSN_LENGTH 2
#define DWARF2_DEFAULT_RETURN_COLUMN 0x41
#define DWARF2_CIE_DATA_ALIGNMENT ppc_cie_data_alignment
Index: doc/c-ppc.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-ppc.texi,v
retrieving revision 1.22
diff -u -r1.22 c-ppc.texi
--- doc/c-ppc.texi 10 Feb 2011 22:50:09 -0000 1.22
+++ doc/c-ppc.texi 12 Aug 2011 17:39:50 -0000
@@ -109,6 +109,9 @@
@item -maltivec
Generate code for processors with AltiVec instructions.
+@item -mvle
+Generate code for Freescale PowerPC VLE instructions.
+
@item -mvsx
Generate code for processors with Vector-Scalar (VSX) instructions.
Index: testsuite/gas/ppc/ppc.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/ppc.exp,v
retrieving revision 1.27
diff -u -r1.27 ppc.exp
--- testsuite/gas/ppc/ppc.exp 8 Feb 2010 01:59:38 -0000 1.27
+++ testsuite/gas/ppc/ppc.exp 12 Aug 2011 17:39:50 -0000
@@ -51,5 +51,13 @@
run_dump_test "vsx"
run_dump_test "476"
run_dump_test "titan"
+ run_dump_test "vle"
+ run_dump_test "vle-reloc"
+ run_dump_test "vle-simple-1"
+ run_dump_test "vle-simple-2"
+ run_dump_test "vle-simple-3"
+ run_dump_test "vle-simple-4"
+ run_dump_test "vle-simple-5"
+ run_dump_test "vle-simple-6"
}
}
Index: testsuite/gas/ppc/vle-reloc.d
===================================================================
RCS file: testsuite/gas/ppc/vle-reloc.d
diff -N testsuite/gas/ppc/vle-reloc.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-reloc.d 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,172 @@
+#as: -mvle
+#objdump: -dr -Mvle
+#name: VLE relocations
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section \.text:
+
+00000000 <.text>:
+ 0: e8 00 se_b 0x0
+ 0: R_PPC_VLE_REL8 sub1
+ 2: e9 00 se_bl 0x2
+ 2: R_PPC_VLE_REL8 sub1
+ 4: e1 00 se_ble 0x4
+ 4: R_PPC_VLE_REL8 sub2
+ 6: e6 00 se_beq 0x6
+ 6: R_PPC_VLE_REL8 sub2
+ 8: 78 00 00 00 e_b 0x8
+ 8: R_PPC_VLE_REL24 sub3
+ c: 78 00 00 01 e_bl 0xc
+ c: R_PPC_VLE_REL24 sub4
+ 10: 7a 05 00 00 e_ble cr1,0x10
+ 10: R_PPC_VLE_REL15 sub5
+ 14: 7a 1a 00 01 e_beql cr2,0x14
+ 14: R_PPC_VLE_REL15 sub5
+
+ 18: 70 20 c0 00 e_or2i r1,0
+ 18: R_PPC_VLE_LO16D low
+ 1c: 70 40 c0 00 e_or2i r2,0
+ 1c: R_PPC_VLE_HI16D high
+ 20: 70 60 c0 00 e_or2i r3,0
+ 20: R_PPC_VLE_HA16D high_adjust
+ 24: 70 80 c0 00 e_or2i r4,0
+ 24: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 28: 70 a0 c0 00 e_or2i r5,0
+ 28: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 2c: 70 40 c0 00 e_or2i r2,0
+ 2c: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 30: 70 20 c8 00 e_and2i. r1,0
+ 30: R_PPC_VLE_LO16D low
+ 34: 70 40 c8 00 e_and2i. r2,0
+ 34: R_PPC_VLE_HI16D high
+ 38: 70 60 c8 00 e_and2i. r3,0
+ 38: R_PPC_VLE_HA16D high_adjust
+ 3c: 70 80 c8 00 e_and2i. r4,0
+ 3c: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 40: 70 a0 c8 00 e_and2i. r5,0
+ 40: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 44: 70 40 c8 00 e_and2i. r2,0
+ 44: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 48: 70 40 c8 00 e_and2i. r2,0
+ 48: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 4c: 70 20 d0 00 e_or2is r1,0
+ 4c: R_PPC_VLE_LO16D low
+ 50: 70 40 d0 00 e_or2is r2,0
+ 50: R_PPC_VLE_HI16D high
+ 54: 70 60 d0 00 e_or2is r3,0
+ 54: R_PPC_VLE_HA16D high_adjust
+ 58: 70 80 d0 00 e_or2is r4,0
+ 58: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 5c: 70 a0 d0 00 e_or2is r5,0
+ 5c: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 60: 70 40 d0 00 e_or2is r2,0
+ 60: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 64: 70 20 e0 00 e_lis r1,0
+ 64: R_PPC_VLE_LO16D low
+ 68: 70 40 e0 00 e_lis r2,0
+ 68: R_PPC_VLE_HI16D high
+ 6c: 70 60 e0 00 e_lis r3,0
+ 6c: R_PPC_VLE_HA16D high_adjust
+ 70: 70 80 e0 00 e_lis r4,0
+ 70: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 74: 70 a0 e0 00 e_lis r5,0
+ 74: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 78: 70 40 e0 00 e_lis r2,0
+ 78: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 7c: 70 20 e8 00 e_and2is. r1,0
+ 7c: R_PPC_VLE_LO16D low
+ 80: 70 40 e8 00 e_and2is. r2,0
+ 80: R_PPC_VLE_HI16D high
+ 84: 70 60 e8 00 e_and2is. r3,0
+ 84: R_PPC_VLE_HA16D high_adjust
+ 88: 70 80 e8 00 e_and2is. r4,0
+ 88: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 8c: 70 a0 e8 00 e_and2is. r5,0
+ 8c: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 90: 70 40 e8 00 e_and2is. r2,0
+ 90: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 94: 70 01 98 00 e_cmp16i r1,0
+ 94: R_PPC_VLE_LO16A low
+ 98: 70 02 98 00 e_cmp16i r2,0
+ 98: R_PPC_VLE_HI16A high
+ 9c: 70 03 98 00 e_cmp16i r3,0
+ 9c: R_PPC_VLE_HA16A high_adjust
+ a0: 70 04 98 00 e_cmp16i r4,0
+ a0: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ a4: 70 05 98 00 e_cmp16i r5,0
+ a4: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ a8: 70 02 98 00 e_cmp16i r2,0
+ a8: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ ac: 70 01 a8 00 e_cmpl16i r1,0
+ ac: R_PPC_VLE_LO16A low
+ b0: 70 02 a8 00 e_cmpl16i r2,0
+ b0: R_PPC_VLE_HI16A high
+ b4: 70 03 a8 00 e_cmpl16i r3,0
+ b4: R_PPC_VLE_HA16A high_adjust
+ b8: 70 04 a8 00 e_cmpl16i r4,0
+ b8: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ bc: 70 05 a8 00 e_cmpl16i r5,0
+ bc: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ c0: 70 02 a8 00 e_cmpl16i r2,0
+ c0: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ c4: 70 01 b0 00 e_cmph16i r1,0
+ c4: R_PPC_VLE_LO16A low
+ c8: 70 02 b0 00 e_cmph16i r2,0
+ c8: R_PPC_VLE_HI16A high
+ cc: 70 03 b0 00 e_cmph16i r3,0
+ cc: R_PPC_VLE_HA16A high_adjust
+ d0: 70 04 b0 00 e_cmph16i r4,0
+ d0: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ d4: 70 05 b0 00 e_cmph16i r5,0
+ d4: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ d8: 70 02 b0 00 e_cmph16i r2,0
+ d8: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ dc: 70 01 b8 00 e_cmphl16i r1,0
+ dc: R_PPC_VLE_LO16A low
+ e0: 70 02 b8 00 e_cmphl16i r2,0
+ e0: R_PPC_VLE_HI16A high
+ e4: 70 03 b8 00 e_cmphl16i r3,0
+ e4: R_PPC_VLE_HA16A high_adjust
+ e8: 70 04 b8 00 e_cmphl16i r4,0
+ e8: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ ec: 70 05 b8 00 e_cmphl16i r5,0
+ ec: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ f0: 70 02 b8 00 e_cmphl16i r2,0
+ f0: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ f4: 70 01 88 00 e_add2i. r1,0
+ f4: R_PPC_VLE_LO16A low
+ f8: 70 02 88 00 e_add2i. r2,0
+ f8: R_PPC_VLE_HI16A high
+ fc: 70 03 88 00 e_add2i. r3,0
+ fc: R_PPC_VLE_HA16A high_adjust
+ 100: 70 04 88 00 e_add2i. r4,0
+ 100: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 104: 70 05 88 00 e_add2i. r5,0
+ 104: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 108: 70 02 88 00 e_add2i. r2,0
+ 108: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 10c: 70 01 90 00 e_add2is r1,0
+ 10c: R_PPC_VLE_LO16A low
+ 110: 70 02 90 00 e_add2is r2,0
+ 110: R_PPC_VLE_HI16A high
+ 114: 70 03 90 00 e_add2is r3,0
+ 114: R_PPC_VLE_HA16A high_adjust
+ 118: 70 04 90 00 e_add2is r4,0
+ 118: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 11c: 70 05 90 00 e_add2is r5,0
+ 11c: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 120: 70 02 90 00 e_add2is r2,0
+ 120: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 124: 70 01 a0 00 e_mull2i r1,0
+ 124: R_PPC_VLE_LO16A low
+ 128: 70 02 a0 00 e_mull2i r2,0
+ 128: R_PPC_VLE_HI16A high
+ 12c: 70 03 a0 00 e_mull2i r3,0
+ 12c: R_PPC_VLE_HA16A high_adjust
+ 130: 70 04 a0 00 e_mull2i r4,0
+ 130: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 134: 70 05 a0 00 e_mull2i r5,0
+ 134: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 138: 70 02 a0 00 e_mull2i r2,0
+ 138: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
Index: testsuite/gas/ppc/vle-reloc.s
===================================================================
RCS file: testsuite/gas/ppc/vle-reloc.s
diff -N testsuite/gas/ppc/vle-reloc.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-reloc.s 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,95 @@
+ .section .text
+ se_b sub1
+ se_bl sub1
+ se_bc 0,1,sub2
+ se_bc 1,2,sub2
+
+ e_b sub3
+ e_bl sub4
+ e_bc 0,5,sub5
+ e_bcl 1,10,sub5
+
+ e_or2i 1, low@l
+ e_or2i 2, high@h
+ e_or2i 3, high_adjust@ha
+ e_or2i 4, low_sdarel@sdarel@l
+ e_or2i 5, high_sdarel@sdarel@h
+ e_or2i 2, high_adjust_sdarel@sdarel@ha
+
+ e_and2i. 1, low@l
+ e_and2i. 2, high@h
+ e_and2i. 3, high_adjust@ha
+ e_and2i. 4, low_sdarel@sdarel@l
+ e_and2i. 5, high_sdarel@sdarel@h
+ e_and2i. 2, high_adjust_sdarel@sdarel@ha
+ e_and2i. 2, high_adjust_sdarel@sdarel@ha
+
+ e_or2is 1, low@l
+ e_or2is 2, high@h
+ e_or2is 3, high_adjust@ha
+ e_or2is 4, low_sdarel@sdarel@l
+ e_or2is 5, high_sdarel@sdarel@h
+ e_or2is 2, high_adjust_sdarel@sdarel@ha
+
+ e_lis 1, low@l
+ e_lis 2, high@h
+ e_lis 3, high_adjust@ha
+ e_lis 4, low_sdarel@sdarel@l
+ e_lis 5, high_sdarel@sdarel@h
+ e_lis 2, high_adjust_sdarel@sdarel@ha
+
+ e_and2is. 1, low@l
+ e_and2is. 2, high@h
+ e_and2is. 3, high_adjust@ha
+ e_and2is. 4, low_sdarel@sdarel@l
+ e_and2is. 5, high_sdarel@sdarel@h
+ e_and2is. 2, high_adjust_sdarel@sdarel@ha
+
+ e_cmp16i 1, low@l
+ e_cmp16i 2, high@h
+ e_cmp16i 3, high_adjust@ha
+ e_cmp16i 4, low_sdarel@sdarel@l
+ e_cmp16i 5, high_sdarel@sdarel@h
+ e_cmp16i 2, high_adjust_sdarel@sdarel@ha
+
+ e_cmpl16i 1, low@l
+ e_cmpl16i 2, high@h
+ e_cmpl16i 3, high_adjust@ha
+ e_cmpl16i 4, low_sdarel@sdarel@l
+ e_cmpl16i 5, high_sdarel@sdarel@h
+ e_cmpl16i 2, high_adjust_sdarel@sdarel@ha
+
+ e_cmph16i 1, low@l
+ e_cmph16i 2, high@h
+ e_cmph16i 3, high_adjust@ha
+ e_cmph16i 4, low_sdarel@sdarel@l
+ e_cmph16i 5, high_sdarel@sdarel@h
+ e_cmph16i 2, high_adjust_sdarel@sdarel@ha
+
+ e_cmphl16i 1, low@l
+ e_cmphl16i 2, high@h
+ e_cmphl16i 3, high_adjust@ha
+ e_cmphl16i 4, low_sdarel@sdarel@l
+ e_cmphl16i 5, high_sdarel@sdarel@h
+ e_cmphl16i 2, high_adjust_sdarel@sdarel@ha
+
+ e_add2i. 1, low@l
+ e_add2i. 2, high@h
+ e_add2i. 3, high_adjust@ha
+ e_add2i. 4, low_sdarel@sdarel@l
+ e_add2i. 5, high_sdarel@sdarel@h
+ e_add2i. 2, high_adjust_sdarel@sdarel@ha
+
+ e_add2is 1, low@l
+ e_add2is 2, high@h
+ e_add2is 3, high_adjust@ha
+ e_add2is 4, low_sdarel@sdarel@l
+ e_add2is 5, high_sdarel@sdarel@h
+ e_add2is 2, high_adjust_sdarel@sdarel@ha
+
+ e_mull2i 1, low@l
+ e_mull2i 2, high@h
+ e_mull2i 3, high_adjust@ha
+ e_mull2i 4, low_sdarel@sdarel@l
+ e_mull2i 5, high_sdarel@sdarel@h
+ e_mull2i 2, high_adjust_sdarel@sdarel@ha
Index: testsuite/gas/ppc/vle-simple-1.d
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-1.d
diff -N testsuite/gas/ppc/vle-simple-1.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-1.d 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,39 @@
+#as: -mvle
+#objdump: -dr -Mvle
+#name: VLE Simplified mnemonics 1
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section \.text:
+
+00000000 <target0>:
+ 0: e6 03 se_beq 6 <target3>
+
+00000002 <target1>:
+ 2: e1 03 se_ble 8 <target4>
+
+00000004 <target2>:
+ 4: e0 00 se_bge 4 <target2>
+
+00000006 <target3>:
+ 6: e5 fe se_bgt 2 <target1>
+
+00000008 <target4>:
+ 8: e1 ff se_ble 6 <target3>
+ a: e4 03 se_blt 10 <target6>
+
+0000000c <target5>:
+ c: e2 fb se_bne 2 <target1>
+ e: e1 01 se_ble 10 <target6>
+
+00000010 <target6>:
+ 10: e0 fc se_bge 8 <target4>
+ 12: e3 fd se_bns c <target5>
+
+00000014 <target8>:
+ 14: e3 f8 se_bns 4 <target2>
+ 16: e7 ff se_bso 14 <target8>
+
+00000018 <target9>:
+ 18: e6 fc se_beq 10 <target6>
+ 1a: e7 ff se_bso 18 <target9>
Index: testsuite/gas/ppc/vle-simple-1.s
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-1.s
diff -N testsuite/gas/ppc/vle-simple-1.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-1.s 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,34 @@
+ .section .text
+
+target0:
+ se_beq target3
+
+target1:
+ se_bf cr1, target4
+
+target2:
+ se_bge target2
+
+target3:
+ se_bgt target1
+
+target4:
+ se_ble target3
+ se_blt target6
+
+target5:
+ se_bne target1
+ se_bng target6
+
+target6:
+ se_bnl target4
+ se_bns target5
+
+target8:
+ se_bnu target2
+ se_bso target8
+
+target9:
+ se_bt cr2, target6
+ se_bun target9
+
Index: testsuite/gas/ppc/vle-simple-2.d
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-2.d
diff -N testsuite/gas/ppc/vle-simple-2.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-2.d 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,83 @@
+#as: -mvle
+#objdump: -dr -Mvle
+#name: VLE Simplified mnemonics 2
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <target0>:
+ 0: 7a 20 00 0c e_bdnz c <target1>
+ 4: 7a 20 00 09 e_bdnzl c <target1>
+ 8: 7a 30 00 10 e_bdz 18 <target2>
+
+0000000c <target1>:
+ c: 7a 30 ff f5 e_bdzl 0 <target0>
+ 10: 7a 12 ff f0 e_beq 0 <target0>
+ 14: 7a 16 00 8c e_beq cr1,a0 <target8>
+
+00000018 <target2>:
+ 18: 7a 12 ff f5 e_beql c <target1>
+ 1c: 7a 12 00 4d e_beql 68 <target6>
+ 20: 7a 01 00 04 e_ble 24 <target3>
+
+00000024 <target3>:
+ 24: 7a 03 ff dd e_bnsl 0 <target0>
+ 28: 7a 04 ff e4 e_bge cr1,c <target1>
+ 2c: 7a 00 00 24 e_bge 50 <target5>
+
+00000030 <target4>:
+ 30: 7a 08 ff f5 e_bgel cr2,24 <target3>
+ 34: 7a 00 ff fd e_bgel 30 <target4>
+ 38: 7a 11 ff c8 e_bgt 0 <target0>
+ 3c: 7a 11 ff c4 e_bgt 0 <target0>
+ 40: 7a 19 ff d9 e_bgtl cr2,18 <target2>
+ 44: 7a 11 ff d5 e_bgtl 18 <target2>
+ 48: 7a 0d 00 08 e_ble cr3,50 <target5>
+ 4c: 7a 01 00 04 e_ble 50 <target5>
+
+00000050 <target5>:
+ 50: 7a 01 ff e1 e_blel 30 <target4>
+ 54: 7a 01 ff dd e_blel 30 <target4>
+ 58: 7a 14 ff cc e_blt cr1,24 <target3>
+ 5c: 7a 10 ff c8 e_blt 24 <target3>
+ 60: 7a 10 ff a1 e_bltl 0 <target0>
+ 64: 7a 14 ff 9d e_bltl cr1,0 <target0>
+
+00000068 <target6>:
+ 68: 7a 02 00 18 e_bne 80 <target7>
+ 6c: 7a 06 ff 94 e_bne cr1,0 <target0>
+ 70: 7a 02 ff e1 e_bnel 50 <target5>
+ 74: 7a 02 ff dd e_bnel 50 <target5>
+ 78: 7a 01 00 48 e_ble c0 <target9>
+ 7c: 7a 05 ff b4 e_ble cr1,30 <target4>
+
+00000080 <target7>:
+ 80: 7a 09 ff e9 e_blel cr2,68 <target6>
+ 84: 7a 01 00 1d e_blel a0 <target8>
+ 88: 7a 04 ff c8 e_bge cr1,50 <target5>
+ 8c: 7a 00 ff c4 e_bge 50 <target5>
+ 90: 7a 0c ff 95 e_bgel cr3,24 <target3>
+ 94: 7a 00 ff 91 e_bgel 24 <target3>
+ 98: 7a 03 ff 80 e_bns 18 <target2>
+ 9c: 7a 03 ff 7c e_bns 18 <target2>
+
+000000a0 <target8>:
+ a0: 7a 0b ff 61 e_bnsl cr2,0 <target0>
+ a4: 7a 03 ff c5 e_bnsl 68 <target6>
+ a8: 7a 07 ff 64 e_bns cr1,c <target1>
+ ac: 7a 03 ff 60 e_bns c <target1>
+ b0: 7a 03 ff d1 e_bnsl 80 <target7>
+ b4: 7a 03 ff 71 e_bnsl 24 <target3>
+ b8: 7a 17 ff 78 e_bso cr1,30 <target4>
+ bc: 7a 13 ff 74 e_bso 30 <target4>
+
+000000c0 <target9>:
+ c0: 7a 13 ff e1 e_bsol a0 <target8>
+ c4: 7a 13 ff dd e_bsol a0 <target8>
+ c8: 7a 11 ff b8 e_bgt 80 <target7>
+ cc: 7a 10 ff 85 e_bltl 50 <target5>
+ d0: 7a 17 ff 60 e_bso cr1,30 <target4>
+ d4: 7a 13 ff 5c e_bso 30 <target4>
+ d8: 7a 1b ff 29 e_bsol cr2,0 <target0>
+ dc: 7a 13 ff e5 e_bsol c0 <target9>
Index: testsuite/gas/ppc/vle-simple-2.s
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-2.s
diff -N testsuite/gas/ppc/vle-simple-2.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-2.s 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,78 @@
+ .section .text
+
+target0:
+ e_bdnz target1
+ e_bdnzl target1
+ e_bdz target2
+
+target1:
+ e_bdzl target0
+ e_beq target0
+ e_beq cr1, target8
+
+target2:
+ e_beql cr0, target1
+ e_beql target6
+ e_bf cr1, target3
+
+target3:
+ e_bfl cr3, target0
+ e_bge cr1, target1
+ e_bge target5
+
+target4:
+ e_bgel cr2, target3
+ e_bgel target4
+ e_bgt cr0, target0
+ e_bgt target0
+ e_bgtl cr2, target2
+ e_bgtl target2
+ e_ble cr3, target5
+ e_ble target5
+
+target5:
+ e_blel cr0, target4
+ e_blel target4
+ e_blt cr1, target3
+ e_blt target3
+ e_bltl target0
+ e_bltl cr1, target0
+
+target6:
+ e_bne target7
+ e_bne cr1, target0
+ e_bnel cr0, target5
+ e_bnel target5
+ e_bng target9
+ e_bng cr1, target4
+
+target7:
+ e_bngl cr2, target6
+ e_bngl target8
+ e_bnl cr1, target5
+ e_bnl target5
+ e_bnll cr3, target3
+ e_bnll target3
+ e_bns target2
+ e_bns cr0, target2
+
+target8:
+ e_bnsl cr2, target0
+ e_bnsl target6
+ e_bnu cr1, target1
+ e_bnu target1
+ e_bnul target7
+ e_bnul cr0, target3
+ e_bso cr1, target4
+ e_bso target4
+
+target9:
+ e_bsol cr0, target8
+ e_bsol target8
+ e_bt cr1, target7
+ e_btl cr0, target5
+ e_bun cr1, target4
+ e_bun target4
+ e_bunl cr2, target0
+ e_bunl target9
+
Index: testsuite/gas/ppc/vle-simple-3.d
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-3.d
diff -N testsuite/gas/ppc/vle-simple-3.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-3.d 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,24 @@
+#as: -mvle
+#objdump: -dr -Mvle
+#name: VLE Simplified mnemonics 3
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <trap>:
+ 0: 7f e0 00 08 trap
+ 4: 7e 01 10 08 twlt r1,r2
+ 8: 7e 83 20 08 twle r3,r4
+ c: 7c 80 08 08 tweq r0,r1
+ 10: 7d 82 18 08 twge r2,r3
+ 14: 7d 02 20 08 twgt r2,r4
+ 18: 7d 82 28 08 twge r2,r5
+ 1c: 7f 02 30 08 twne r2,r6
+ 20: 7e 82 38 08 twle r2,r7
+ 24: 7c 42 40 08 twllt r2,r8
+ 28: 7c c2 48 08 twlle r2,r9
+ 2c: 7c a2 50 08 twlge r2,r10
+ 30: 7c 22 58 08 twlgt r2,r11
+ 34: 7c a2 60 08 twlge r2,r12
+ 38: 7c c2 68 08 twlle r2,r13
Index: testsuite/gas/ppc/vle-simple-3.s
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-3.s
diff -N testsuite/gas/ppc/vle-simple-3.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-3.s 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,18 @@
+ .section .text
+trap:
+ trap
+ twlt 1, 2
+ twle 3, 4
+ tweq 0, 1
+ twge 2, 3
+ twgt 2, 4
+ twnl 2, 5
+ twne 2, 6
+ twng 2, 7
+ twllt 2, 8
+ twlle 2, 9
+ twlge 2, 10
+ twlgt 2, 11
+ twlnl 2, 12
+ twlng 2, 13
+
Index: testsuite/gas/ppc/vle-simple-4.d
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-4.d
diff -N testsuite/gas/ppc/vle-simple-4.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-4.d 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,23 @@
+#as: -mvle
+#objdump: -dr -Mvle
+#name: VLE Simplified mnemonics 4
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <subtract>:
+ 0: 7c 23 10 50 subf r1,r3,r2
+ 4: 7c a3 20 51 subf. r5,r3,r4
+ 8: 7c 21 14 50 subfo r1,r1,r2
+ c: 7c 01 14 51 subfo. r0,r1,r2
+ 10: 7c 65 20 10 subfc r3,r5,r4
+ 14: 7c 65 20 11 subfc. r3,r5,r4
+ 18: 7c 23 14 10 subfco r1,r3,r2
+ 1c: 7c a7 34 11 subfco. r5,r7,r6
+ 20: 18 85 84 d0 e_addi r4,r5,-48
+ 24: 18 66 94 fe e_addic r3,r6,-2
+ 28: 18 e8 9c f0 e_addic. r7,r8,-16
+ 2c: 1c 22 ff f1 e_add16i r1,r2,-15
+ 30: 73 e5 8f ff e_add2i. r5,-1
+ 34: 73 ea 97 00 e_add2is r10,-256
Index: testsuite/gas/ppc/vle-simple-4.s
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-4.s
diff -N testsuite/gas/ppc/vle-simple-4.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-4.s 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,19 @@
+ .section .text
+
+subtract:
+ sub 1, 2, 3
+ sub. 5, 4, 3
+ subo 1, 2, 1
+ subo. 0, 2, 1
+ subc 3, 4, 5
+ subc. 3, 4, 5
+ subco 1, 2, 3
+ subco. 5, 6, 7
+
+ e_subi 4, 5, 0x30
+ e_subic 3, 6, 0x2
+ e_subic. 7, 8, 0x10
+
+ e_sub16i 1, 2, 0xf
+ e_sub2i. 5, 0x1
+ e_sub2is 10, 0x100
Index: testsuite/gas/ppc/vle-simple-5.d
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-5.d
diff -N testsuite/gas/ppc/vle-simple-5.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-5.d 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,20 @@
+#as: -mvle
+#objdump: -dr -Mvle
+#name: VLE Simplified mnemonics 5
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 74 42 00 01 e_rlwinm r2,r2,0,0,0
+ 4: 74 62 7d bf e_rlwinm r2,r3,15,22,31
+ 8: 74 a4 f8 48 e_rlwimi r4,r5,31,1,4
+ c: 74 e6 c9 4c e_rlwimi r6,r7,25,5,6
+ 10: 74 41 50 3f e_rlwinm r1,r2,10,0,31
+ 14: 74 83 c0 3f e_rlwinm r3,r4,24,0,31
+ 18: 7c 62 f8 70 e_slwi r2,r3,31
+ 1c: 7c 25 f4 70 e_srwi r5,r1,30
+ 20: 74 64 07 7f e_rlwinm r4,r3,0,29,31
+ 24: 74 41 00 07 e_rlwinm r1,r2,0,0,3
+ 28: 74 e6 d8 49 e_rlwinm r6,r7,27,1,4
Index: testsuite/gas/ppc/vle-simple-5.s
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-5.s
diff -N testsuite/gas/ppc/vle-simple-5.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-5.s 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,13 @@
+ .section .text
+
+ e_extlwi 2, 2, 1, 0
+ e_extrwi 2, 3, 10, 5
+ e_inslwi 4, 5, 4, 1
+ e_insrwi 6, 7, 2, 5
+ e_rotlwi 1, 2, 10
+ e_rotrwi 3, 4, 8
+ e_slwi 2, 3, 31
+ e_srwi 5, 1, 30
+ e_clrlwi 4, 3, 29
+ e_clrrwi 1, 2, 28
+ e_clrlslwi 6, 7, 28, 27
Index: testsuite/gas/ppc/vle-simple-6.d
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-6.d
diff -N testsuite/gas/ppc/vle-simple-6.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-6.d 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,60 @@
+#as: -mvle
+#objdump: -dr -Mvle
+#name: VLE Simplified mnemonics 6
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 7c b1 9b a6 mtmas1 r5
+ 4: 7c 3a 0b a6 mtcsrr0 r1
+ 8: 7c 5b 0b a6 mtcsrr1 r2
+ c: 7c b0 62 a6 mfivor0 r5
+ 10: 7c b1 62 a6 mfivor1 r5
+ 14: 7c b2 62 a6 mfivor2 r5
+ 18: 7c b3 62 a6 mfivor3 r5
+ 1c: 7c b4 62 a6 mfivor4 r5
+ 20: 7c b5 62 a6 mfivor5 r5
+ 24: 7c b6 62 a6 mfivor6 r5
+ 28: 7c b7 62 a6 mfivor7 r5
+ 2c: 7c b8 62 a6 mfivor8 r5
+ 30: 7c b9 62 a6 mfivor9 r5
+ 34: 7c ba 62 a6 mfivor10 r5
+ 38: 7c bb 62 a6 mfivor11 r5
+ 3c: 7c bc 62 a6 mfivor12 r5
+ 40: 7c bd 62 a6 mfivor13 r5
+ 44: 7c be 62 a6 mfivor14 r5
+ 48: 7c bf 62 a6 mfivor15 r5
+ 4c: 7d 50 43 a6 mtsprg 0,r10
+ 50: 7d 51 43 a6 mtsprg 1,r10
+ 54: 7d 52 43 a6 mtsprg 2,r10
+ 58: 7d 53 43 a6 mtsprg 3,r10
+ 5c: 7d 54 43 a6 mtsprg 4,r10
+ 60: 7d 55 43 a6 mtsprg 5,r10
+ 64: 7d 56 43 a6 mtsprg 6,r10
+ 68: 7d 57 43 a6 mtsprg 7,r10
+ 6c: 7d 50 43 a6 mtsprg 0,r10
+ 70: 7d 51 43 a6 mtsprg 1,r10
+ 74: 7d 52 43 a6 mtsprg 2,r10
+ 78: 7d 53 43 a6 mtsprg 3,r10
+ 7c: 7d 54 43 a6 mtsprg 4,r10
+ 80: 7d 55 43 a6 mtsprg 5,r10
+ 84: 7d 56 43 a6 mtsprg 6,r10
+ 88: 7d 57 43 a6 mtsprg 7,r10
+ 8c: 7d 30 42 a6 mfsprg r9,0
+ 90: 7d 31 42 a6 mfsprg r9,1
+ 94: 7d 32 42 a6 mfsprg r9,2
+ 98: 7d 33 42 a6 mfsprg r9,3
+ 9c: 7d 24 42 a6 mfsprg r9,4
+ a0: 7d 25 42 a6 mfsprg r9,5
+ a4: 7d 26 42 a6 mfsprg r9,6
+ a8: 7d 27 42 a6 mfsprg r9,7
+ ac: 7d 30 42 a6 mfsprg r9,0
+ b0: 7d 31 42 a6 mfsprg r9,1
+ b4: 7d 32 42 a6 mfsprg r9,2
+ b8: 7d 33 42 a6 mfsprg r9,3
+ bc: 7d 24 42 a6 mfsprg r9,4
+ c0: 7d 25 42 a6 mfsprg r9,5
+ c4: 7d 26 42 a6 mfsprg r9,6
+ c8: 7d 27 42 a6 mfsprg r9,7
Index: testsuite/gas/ppc/vle-simple-6.s
===================================================================
RCS file: testsuite/gas/ppc/vle-simple-6.s
diff -N testsuite/gas/ppc/vle-simple-6.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle-simple-6.s 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,59 @@
+ .section .text
+
+ mtmas1 5
+
+ mtcsrr0 1
+ mtcsrr1 2
+
+ mfivor0 5
+ mfivor1 5
+ mfivor2 5
+ mfivor3 5
+ mfivor4 5
+ mfivor5 5
+ mfivor6 5
+ mfivor7 5
+ mfivor8 5
+ mfivor9 5
+ mfivor10 5
+ mfivor11 5
+ mfivor12 5
+ mfivor13 5
+ mfivor14 5
+ mfivor15 5
+
+ mtsprg 0, 10
+ mtsprg 1, 10
+ mtsprg 2, 10
+ mtsprg 3, 10
+ mtsprg 4, 10
+ mtsprg 5, 10
+ mtsprg 6, 10
+ mtsprg 7, 10
+
+ mtsprg0 10
+ mtsprg1 10
+ mtsprg2 10
+ mtsprg3 10
+ mtsprg4 10
+ mtsprg5 10
+ mtsprg6 10
+ mtsprg7 10
+
+ mfsprg 9, 0
+ mfsprg 9, 1
+ mfsprg 9, 2
+ mfsprg 9, 3
+ mfsprg 9, 4
+ mfsprg 9, 5
+ mfsprg 9, 6
+ mfsprg 9, 7
+
+ mfsprg0 9
+ mfsprg1 9
+ mfsprg2 9
+ mfsprg3 9
+ mfsprg4 9
+ mfsprg5 9
+ mfsprg6 9
+ mfsprg7 9
Index: testsuite/gas/ppc/vle.d
===================================================================
RCS file: testsuite/gas/ppc/vle.d
diff -N testsuite/gas/ppc/vle.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle.d 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,150 @@
+#as: -mvle
+#objdump: -dr -Mvle
+#name: Validate VLE instructions
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <.*>:
+ 0: 1c 83 00 1b e_add16i r4,r3,27
+ 4: 70 c0 8c 56 e_add2i\. r0,13398
+ 8: 71 01 93 21 e_add2is r1,17185
+ c: 18 46 88 37 e_addi\. r2,r6,55
+ 10: 18 65 81 37 e_addi r3,r5,14080
+ 14: 18 84 9a 37 e_addic\. r4,r4,3604480
+ 18: 18 e8 93 37 e_addic r7,r8,922746880
+ 1c: 71 3f ce ed e_and2i\. r9,65261
+ 20: 71 40 e8 05 e_and2is\. r10,5
+ 24: 19 ab c8 39 e_andi\. r11,r13,57
+ 28: 19 ec c2 37 e_andi r12,r15,3604480
+ 2c: 78 00 00 ec e_b 118 <middle_label>
+ 30: 78 00 00 01 e_bl 30 <start_label\+0x30>
+ 30: R_PPC_VLE_REL24 extern_subr
+ 34: 7a 03 ff cc e_bns 0 <start_label>
+ 38: 7a 1f 00 01 e_bsol cr3,38 <start_label\+0x38>
+ 38: R_PPC_VLE_REL15 extern_subr
+ 3c: 70 c2 9b 33 e_cmp16i r2,13107
+ 40: 18 46 a9 37 e_cmpi cr2,r6,14080
+ 44: 7c 87 58 1c e_cmph cr1,r7,r11
+ 48: 73 ec b5 ef e_cmph16i r12,-529
+ 4c: 7c 06 40 5c e_cmphl cr0,r6,r8
+ 50: 70 4d ba 34 e_cmphl16i r13,4660
+ 54: 73 e1 ae e0 e_cmpl16i r1,65248
+ 58: 18 a3 ab 37 e_cmpli cr1,r3,922746880
+ 5c: 7f a3 02 02 e_crand 4\*cr7\+gt,so,lt
+ 60: 7c 02 e9 02 e_crandc lt,eq,4\*cr7\+gt
+ 64: 7d f0 8a 42 e_creqv 4\*cr3\+so,4\*cr4\+lt,4\*cr4\+gt
+ 68: 7d e0 19 c2 e_crnand 4\*cr3\+so,lt,so
+ 6c: 7d e0 18 42 e_crnor 4\*cr3\+so,lt,so
+ 70: 7d 8d 73 82 e_cror 4\*cr3\+lt,4\*cr3\+gt,4\*cr3\+eq
+ 74: 7e 72 8b 42 e_crorc 4\*cr4\+so,4\*cr4\+eq,4\*cr4\+gt
+ 78: 7c 00 01 82 e_crclr lt
+ 7c: 30 e3 cc 0d e_lbz r7,-13299\(r3\)
+ 80: 18 e5 00 cc e_lbzu r7,-52\(r5\)
+ 84: 39 0a 01 ff e_lha r8,511\(r10\)
+ 88: 19 01 03 ff e_lhau r8,-1\(r1\)
+ 8c: 58 e0 18 38 e_lhz r7,6200\(0\)
+ 90: 18 e0 01 3e e_lhzu r7,62\(0\)
+ 94: 70 06 1b 33 e_li r0,209715
+ 98: 70 26 e3 33 e_lis r1,13107
+ 9c: 18 a3 08 18 e_lmw r5,24\(r3\)
+ a0: 50 a3 27 28 e_lwz r5,10024\(r3\)
+ a4: 18 c2 02 72 e_lwzu r6,114\(r2\)
+ a8: 7c 98 00 20 e_mcrf cr1,cr6
+ ac: 19 2a a0 37 e_mulli r9,r10,55
+ b0: 70 01 a6 68 e_mull2i r1,1640
+ b4: 70 a4 c3 45 e_or2i r5,9029
+ b8: 70 b4 d3 45 e_or2is r5,41797
+ bc: 19 27 d8 37 e_ori\. r7,r9,55
+ c0: 19 07 d1 37 e_ori r7,r8,14080
+ c4: 7e d2 02 30 e_rlw r18,r22,r0
+ c8: 7c 48 02 31 e_rlw\. r8,r2,r0
+ cc: 7c 74 aa 70 e_rlwi r20,r3,21
+ d0: 7c 62 aa 71 e_rlwi\. r2,r3,21
+ d4: 76 64 6a 1e e_rlwimi r4,r19,13,8,15
+ d8: 74 24 68 63 e_rlwinm r4,r1,13,1,17
+ dc: 7e 6c 30 70 e_slwi r12,r19,6
+ e0: 7d 4c a0 71 e_slwi\. r12,r10,20
+ e4: 7c 20 84 70 e_srwi r0,r1,16
+ e8: 7c 20 5c 71 e_srwi\. r0,r1,11
+ ec: 34 61 55 f0 e_stb r3,22000\(r1\)
+ f0: 1a 76 04 fc e_stbu r19,-4\(r22\)
+ f4: 5c 15 02 9a e_sth r0,666\(r21\)
+ f8: 18 37 05 ff e_sthu r1,-1\(r23\)
+ fc: 18 03 09 04 e_stmw r0,4\(r3\)
+ 100: 54 60 3f 21 e_stw r3,16161\(0\)
+ 104: 1a c4 06 ee e_stwu r22,-18\(r4\)
+ 108: 18 15 b2 37 e_subfic r0,r21,3604480
+ 10c: 1a c0 bb 37 e_subfic\. r22,r0,922746880
+ 110: 18 75 e1 37 e_xori r21,r3,14080
+ 114: 1a 80 e8 37 e_xori\. r0,r20,55
+0+0000118 <middle_label>:
+ 118: 04 7f se_add r31,r7
+ 11a: 21 ec se_addi r28,31
+ 11c: 46 10 se_and r0,r1
+ 11e: 47 01 se_and\. r1,r0
+ 120: 45 32 se_andc r2,r3
+ 122: 2f 14 se_andi r4,17
+ 124: e8 fa se_b 118 <middle_label>
+ 126: e9 00 se_bl 126 <middle_label\+0xe>
+ 126: R_PPC_VLE_REL8 extern_subr
+ 128: e7 14 se_bso 150 <not_end_label>
+ 12a: 61 2b se_bclri r27,18
+ 12c: 00 06 se_bctr
+ 12e: 00 07 se_bctrl
+ 130: 63 17 se_bgeni r7,17
+ 132: 00 04 se_blr
+ 134: 00 05 se_blrl
+ 136: 2c 06 se_bmaski r6,0
+ 138: 64 10 se_bseti r0,1
+ 13a: 66 74 se_btsti r4,7
+ 13c: 0c 10 se_cmp r0,r1
+ 13e: 0e cf se_cmph r31,r28
+ 140: 0f 91 se_cmphl r1,r25
+ 142: 2b 63 se_cmpi r3,22
+ 144: 0d 76 se_cmpl r6,r7
+ 146: 22 bc se_cmpli r28,12
+ 148: 00 d1 se_extsb r1
+ 14a: 00 f2 se_extsh r2
+ 14c: 00 ce se_extzb r30
+ 14e: 00 e8 se_extzh r24
+0+0000150 <not_end_label>:
+ 150: 00 00 se_illegal
+ 152: 00 01 se_isync
+ 154: 88 18 se_lbz r1,8\(r24\)
+ 156: a9 84 se_lhz r24,18\(r4\)
+ 158: 4c f4 se_li r4,79
+ 15a: cf 60 se_lwz r6,60\(r0\)
+ 15c: 03 07 se_mfar r7,r8
+ 15e: 00 a3 se_mfctr r3
+ 160: 00 84 se_mflr r4
+ 162: 01 0f se_mr r31,r0
+ 164: 02 2f se_mtar r23,r2
+ 166: 00 b6 se_mtctr r6
+ 168: 00 9f se_mtlr r31
+ 16a: 05 43 se_mullw r3,r4
+ 16c: 00 38 se_neg r24
+ 16e: 00 29 se_not r25
+ 170: 44 10 se_or r0,r1
+ 172: 00 09 se_rfci
+ 174: 00 0a se_rfdi
+ 176: 00 08 se_rfi
+ 178: 00 02 se_sc
+ 17a: 42 65 se_slw r5,r6
+ 17c: 6c 77 se_slwi r7,7
+ 17e: 41 e6 se_sraw r6,r30
+ 180: 6a 89 se_srawi r25,8
+ 182: 40 0e se_srw r30,r0
+ 184: 69 9d se_srwi r29,25
+ 186: 9a 02 se_stb r0,10\(r2\)
+ 188: b6 1e se_sth r1,12\(r30\)
+ 18a: d0 7d se_stw r7,0\(r29\)
+ 18c: 06 21 se_sub r1,r2
+ 18e: 07 ad se_subf r29,r26
+ 190: 25 77 se_subi r7,24
+0+0000192 <end_label>:
+ 192: 27 29 se_subi\. r25,19
+ 194: e9 c2 se_bl 118 <middle_label>
+ 196: 79 ff ff 82 e_b 118 <middle_label>
+ 19a: 79 ff fe 67 e_bl 0 <start_label>
Index: testsuite/gas/ppc/vle.s
===================================================================
RCS file: testsuite/gas/ppc/vle.s
diff -N testsuite/gas/ppc/vle.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/ppc/vle.s 12 Aug 2011 17:39:50 -0000
@@ -0,0 +1,184 @@
+# Freescale PowerPC VLE instruction tests
+#as: -mvle
+ .section .text
+ .extern extern_subr
+ .equ UI8,0x37
+ .equ SCI0,UI8<<0
+ .equ SCI1,UI8<<8
+ .equ SCI2,UI8<<16
+ .equ SCI3,UI8<<24
+ .equ r0,0
+ .equ r1,1
+ .equ r2,2
+ .equ r3,3
+ .equ r4,4
+ .equ r5,5
+ .equ r6,6
+ .equ r7,7
+ .equ r8,8
+ .equ r9,9
+ .equ r10,10
+ .equ r11,11
+ .equ r12,12
+ .equ r13,13
+ .equ r14,14
+ .equ r15,15
+ .equ r16,16
+ .equ r17,17
+ .equ r18,18
+ .equ r19,19
+ .equ r20,20
+ .equ r21,21
+ .equ r22,22
+ .equ r23,23
+ .equ r24,24
+ .equ r25,25
+ .equ r26,26
+ .equ r27,27
+ .equ r28,28
+ .equ r29,29
+ .equ r30,30
+ .equ r31,31
+ .equ r32,32
+ .equ rsp,r1
+
+
+start_label:
+ e_add16i r4,r3,27
+ e_add2i. r0,0x3456
+ e_add2is r1,0x4321
+ e_addi. r2,r6,SCI0
+ e_addi r3,r5,SCI1
+ e_addic. r4,r4,SCI2
+ e_addic r7,r8,SCI3
+ e_and2i. r9,0xfeed
+ e_and2is. r10,5
+ e_andi. r11,r13,0x39
+ e_andi r12,r15,SCI2
+ e_b middle_label
+ e_bl extern_subr
+ e_bc 0,3,start_label
+ e_bcl 1,15,extern_subr
+ e_cmp16i r2,0x3333
+ e_cmpi 2,r6,SCI1
+ e_cmph 1,r7,r11
+ e_cmph16i r12,0xfdef
+ e_cmphl 0,r6,r8
+ e_cmphl16i r13,0x1234
+ e_cmpl16i r1, 0xfee0
+ e_cmpli 1,r3,SCI3
+ e_crand 0x1d,3,0
+ e_crandc 0,2,0x1d
+ e_creqv 15,16,17
+ e_crnand 0xf,0,3
+ e_crnor 0xf,0,3
+ e_cror 12,13,14
+ e_crorc 19,18,17
+ e_crxor 0,0,0
+ e_lbz r7,0xffffcc0d(r3)
+ e_lbzu r7,-52(r5)
+ e_lha r8,0x1ff(r10)
+ e_lhau r8,-1(r1)
+ e_lhz r7,6200(r0)
+ e_lhzu r7,62(r0)
+ e_li r0,0x33333
+ e_lis r1,0x3333
+ e_lmw r5,24(r3)
+ e_lwz r5,10024(r3)
+ e_lwzu r6,0x72(r2)
+ e_mcrf 1,6
+ e_mulli r9,r10,SCI0
+ e_mull2i r1,0x668
+ e_or2i r5,0x2345
+ e_or2is r5,0xa345
+ e_ori. r7,r9,SCI0
+ e_ori r7,r8,SCI1
+ e_rlw r18, r22,r0
+ e_rlw. r8, r2,r0
+ e_rlwi r20,r3,21
+ e_rlwi. r2,r3,21
+ e_rlwimi r4,r19,13,8,15
+ e_rlwinm r4,r1,13,1,17
+ e_slwi r12,r19,6
+ e_slwi. r12,r10,20
+ e_srwi r0,r1,16
+ e_srwi. r0,r1,11
+ e_stb r3,22000(r1)
+ e_stbu r19,-4(r22)
+ e_sth r0,666(r21)
+ e_sthu r1,-1(r23)
+ e_stmw r0,4(r3)
+ e_stw r3,16161(r0)
+ e_stwu r22,0xffffffee(r4)
+ e_subfic r0,r21,SCI2
+ e_subfic. r22,r0,SCI3
+ e_xori r21,r3,SCI1
+ e_xori. r0,r20,SCI0
+middle_label:
+ se_add r31,r7
+ se_addi r28,0x1f
+ se_and r0,r1
+ se_and. r1,r0
+ se_andc r2, r3
+ se_andi r4,0x11
+ se_b middle_label
+ se_bl extern_subr
+ se_bc 1,3,not_end_label
+ se_bclri r27,0x12
+ se_bctr
+ se_bctrl
+ se_bgeni r7,17
+ se_blr
+ se_blrl
+ se_bmaski r6,0
+ se_bseti r0,1
+ se_btsti r4,7
+ se_cmp r0,r1
+ se_cmph r31,r28
+ se_cmphl r1,r25
+ se_cmpi r3,22
+ se_cmpl r6,r7
+ se_cmpli r28,0xc
+ se_extsb r1
+ se_extsh r2
+ se_extzb r30
+ se_extzh r24
+not_end_label:
+ se_illegal
+ se_isync
+ se_lbz r1,8(r24)
+ se_lhz r24,18(r4)
+ se_li r4,0x4f
+ se_lwz r6,60(r0)
+ se_mfar r7,r8
+ se_mfctr r3
+ se_mflr r4
+ se_mr r31,r0
+ se_mtar r23,r2
+ se_mtctr r6
+ se_mtlr r31
+ se_mullw r3,r4
+ se_neg r24
+ se_not r25
+ se_or r0,r1
+ se_rfci
+ se_rfdi
+ se_rfi
+ se_sc
+ se_slw r5,r6
+ se_slwi r7,7
+ se_sraw r6,r30
+ se_srawi r25,8
+ se_srw r30,r0
+ se_srwi r29,25
+ se_stb r0,10(r2)
+ se_sth r1,12(r30)
+ se_stw r7,0(r29)
+ se_sub r1,r2
+ se_subf r29,r26
+ se_subi r7,24
+end_label:
+ se_subi. r25,19
+ se_bl middle_label
+ e_b middle_label
+ e_bl start_label
Attachment:
opcodes.cl
Description: Text document
? big.opcodes.patch
? diff
Index: ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.50
diff -u -r1.50 ppc-dis.c
--- ppc-dis.c 3 Jul 2010 08:27:23 -0000 1.50
+++ ppc-dis.c 12 Aug 2011 15:50:10 -0000
@@ -23,6 +23,8 @@
#include <stdio.h>
#include "sysdep.h"
#include "dis-asm.h"
+#include "elf-bfd.h"
+#include "elf/ppc.h"
#include "opintl.h"
#include "opcode/ppc.h"
@@ -169,10 +171,28 @@
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
0 },
+ { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
+ PPC_OPCODE_VLE },
{ "vsx", (PPC_OPCODE_PPC),
PPC_OPCODE_VSX },
};
+/* Switch between Booke and VLE dialects for interlinked dumps. */
+static ppc_cpu_t
+get_powerpc_dialect (struct disassemble_info *info)
+{
+ ppc_cpu_t dialect = 0;
+
+ dialect = POWERPC_DIALECT (info);
+
+ /* Disassemble according to the section headers flags for VLE-mode. */
+ if (dialect & PPC_OPCODE_VLE
+ && info->section->flags & SHF_PPC_VLE)
+ return dialect;
+ else
+ return dialect & ~ PPC_OPCODE_VLE;
+}
+
/* Handle -m and -M options that set cpu type, and .machine arg. */
ppc_cpu_t
@@ -244,9 +264,12 @@
dialect |= PPC_OPCODE_64;
else
dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
- /* Choose a reasonable default. */
- dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
- | PPC_OPCODE_ALTIVEC);
+ if (info->mach == bfd_mach_ppc_vle)
+ dialect |= PPC_OPCODE_PPC | PPC_OPCODE_VLE;
+ else
+ /* Choose a reasonable default. */
+ dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
+ | PPC_OPCODE_ALTIVEC);
}
info->private_data = priv;
@@ -262,7 +285,7 @@
{
if (info->private_data == NULL && !powerpc_init_dialect (info))
return -1;
- return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
+ return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
}
/* Print a little endian PowerPC instruction. */
@@ -272,7 +295,7 @@
{
if (info->private_data == NULL && !powerpc_init_dialect (info))
return -1;
- return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
+ return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
}
/* Print a POWER (RS/6000) instruction. */
@@ -296,11 +319,14 @@
value = (*operand->extract) (insn, dialect, &invalid);
else
{
- value = (insn >> operand->shift) & operand->bitm;
+ if (operand->shift >= 0)
+ value = (insn >> operand->shift) & operand->bitm;
+ else
+ value = (insn << -operand->shift) & operand->bitm;
if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
{
/* BITM is always some number of zeros followed by some
- number of ones, followed by some numer of zeros. */
+ number of ones, followed by some number of zeros. */
unsigned long top = operand->bitm;
/* top & -top gives the rightmost 1 bit, so this
fills in any trailing zeros. */
@@ -344,16 +370,33 @@
bfd_byte buffer[4];
int status;
unsigned long insn;
+ unsigned long mask, table_opcode;
const struct powerpc_opcode *opcode;
const struct powerpc_opcode *opcode_end;
unsigned long op;
ppc_cpu_t dialect_orig = dialect;
+ bfd_boolean insn_is_short, table_op_is_short;
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
- (*info->memory_error_func) (status, memaddr, info);
- return -1;
+ /* The final instruction may be a 2-byte VLE insn. */
+ if ((dialect & PPC_OPCODE_VLE) != 0)
+ {
+ /* Clear buffer so unused bytes will not have garbage in them. */
+ buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
+ status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, memaddr, info);
+ return -1;
+ }
+ }
+ else
+ {
+ (*info->memory_error_func) (status, memaddr, info);
+ return -1;
+ }
}
if (bigendian)
@@ -361,8 +404,8 @@
else
insn = bfd_getl32 (buffer);
- /* Get the major opcode of the instruction. */
- op = PPC_OP (insn);
+ /* Get the major opcode of the insn in short and long form. */
+ op = PPC_OP (insn, 26);
/* Find the first match in the opcode table. We could speed this up
a bit by doing a binary search on the major opcode. */
@@ -371,6 +414,8 @@
for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
{
unsigned long table_op;
+ unsigned long masked_op;
+ unsigned long masked_insn;
const unsigned char *opindex;
const struct powerpc_operand *operand;
int invalid;
@@ -378,13 +423,49 @@
int need_paren;
int skip_optional;
- table_op = PPC_OP (opcode->opcode);
- if (op < table_op)
+ mask = opcode->mask;
+ table_opcode = opcode->opcode;
+ table_op_is_short = PPC_OP_SE_VLE (mask);
+ table_op = PPC_OP (table_opcode, PPC_OP_SA (mask));
+
+ masked_op = op;
+ if (table_op_is_short)
+ {
+ /* Some short instructions only have 4 or 5 opcode bits. */
+ if ((mask & 0xfff) == 0)
+ masked_op &= 0x3c;
+ else if ((mask & 0x7ff) == 0)
+ masked_op &= 0x3e;
+ }
+ if (masked_op < table_op)
break;
- if (op > table_op)
+ if (masked_op > table_op)
continue;
- if ((insn & opcode->mask) != opcode->opcode
+ /* Handle 16-bit VLE instructions by comparing the
+ correct number of opcode bits. The opcode field for
+ 16-bit VLE instructions may only have 4 or 5 bits. */
+
+ masked_insn = insn;
+ if (table_op_is_short)
+ {
+ /* Skip se_bc in favor of simplified mnemonics. */
+ if (table_opcode == 0xe000 && !strcmp (opcode->name, "se_bc"))
+ continue;
+ if ((mask & 0xfff) == 0)
+ masked_insn &= 0xf3ffffff;
+ else if ((mask & 0x7ff) == 0)
+ masked_insn &= 0xfbffffff;
+ mask <<= 16;
+ table_opcode <<= 16;
+ }
+ /* Skip e_bc or e_bcl in favor of simplified mnemonics. */
+ else if (table_opcode == 0x7a000000 && !strcmp (opcode->name, "e_bc"))
+ continue;
+ else if (table_opcode == 0x7a000001 && !strcmp (opcode->name, "e_bcl"))
+ continue;
+
+ if ((masked_insn & mask) != table_opcode
|| (opcode->flags & dialect) == 0
|| (opcode->deprecated & dialect_orig) != 0)
continue;
@@ -408,6 +489,11 @@
else
(*info->fprintf_func) (info->stream, "%s", opcode->name);
+ insn_is_short = table_op_is_short;
+ if (insn_is_short)
+ /* The operands will be fetched out of the 16-bit instruction. */
+ insn >>= 16;
+
/* Now extract and print the operands. */
need_comma = 0;
need_paren = 0;
@@ -463,26 +549,26 @@
(*info->fprintf_func) (info->stream, "fcr%ld", value);
else if ((operand->flags & PPC_OPERAND_UDI) != 0)
(*info->fprintf_func) (info->stream, "%ld", value);
- else if ((operand->flags & PPC_OPERAND_CR) != 0
- && (dialect & PPC_OPCODE_PPC) != 0)
+ else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
+ && (((dialect & PPC_OPCODE_PPC) != 0)
+ || ((dialect & PPC_OPCODE_VLE) != 0)))
+ (*info->fprintf_func) (info->stream, "cr%ld", value);
+ else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
+ && (((dialect & PPC_OPCODE_PPC) != 0)
+ || ((dialect & PPC_OPCODE_VLE) != 0)))
{
- if (operand->bitm == 7)
- (*info->fprintf_func) (info->stream, "cr%ld", value);
- else
- {
- static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
- int cr;
- int cc;
-
- cr = value >> 2;
- if (cr != 0)
- (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
- cc = value & 3;
- (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
- }
+ static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
+ int cr;
+ int cc;
+
+ cr = value >> 2;
+ if (cr != 0)
+ (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
+ cc = value & 3;
+ (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
}
else
- (*info->fprintf_func) (info->stream, "%ld", value);
+ (*info->fprintf_func) (info->stream, "%d", value);
if (need_paren)
{
@@ -500,7 +586,14 @@
}
/* We have found and printed an instruction; return. */
- return 4;
+ if (insn_is_short)
+ {
+ memaddr += 2;
+ return 2;
+ }
+ else
+ /* Otherwise, return. */
+ return 4;
}
if ((dialect & PPC_OPCODE_ANY) != 0)
Index: ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.137
diff -u -r1.137 ppc-opc.c
--- ppc-opc.c 25 Apr 2011 23:11:21 -0000 1.137
+++ ppc-opc.c 12 Aug 2011 15:50:11 -0000
@@ -39,6 +39,10 @@
/* Local insertion and extraction functions. */
+static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_arx (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_ary (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
static long extract_bat (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
@@ -53,6 +57,8 @@
static long extract_boe (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
static long extract_fxm (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_li20 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
static long extract_mbe (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
@@ -60,14 +66,28 @@
static long extract_nb (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
static long extract_nsi (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_oimm (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
static long extract_rbs (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_rx (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_ry (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
static long extract_spr (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
@@ -86,6 +106,14 @@
static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
static long extract_dm (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_vleui (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_vleil (unsigned long, ppc_cpu_t, int *);
/* The operands table.
@@ -110,7 +138,7 @@
/* The BI field in a B form or XL form instruction. */
#define BI BA
#define BI_MASK (0x1f << 16)
- { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
+ { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
/* The BA field in an XL form instruction when it must be the same
as the BT field in the same instruction. */
@@ -120,7 +148,7 @@
/* The BB field in an XL form instruction. */
#define BB BAT + 1
#define BB_MASK (0x1f << 11)
- { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
+ { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
/* The BB field in an XL form instruction when it must be the same
as the BA field in the same instruction. */
@@ -165,7 +193,9 @@
#define BF BDPA + 1
/* The CRFD field in an X form instruction. */
#define CRFD BF
- { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
+ /* The CRD field in an XL form instruction. */
+#define CRD BF
+ { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
/* The BF field in an X or XL form instruction. */
#define BFF BF + 1
@@ -174,11 +204,11 @@
/* An optional BF field. This is used for comparison instructions,
in which an omitted BF field is taken as zero. */
#define OBF BFF + 1
- { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+ { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
/* The BFA field in an X or XL form instruction. */
#define BFA OBF + 1
- { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
+ { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
/* The BO field in a B form instruction. Certain values are
illegal. */
@@ -196,14 +226,40 @@
/* The BT field in an X or XL form instruction. */
#define BT BH + 1
- { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
+ { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
+
+ /* The BI16 field in a BD8 form instruction. */
+#define BI16 BT + 1
+ { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
+
+ /* The BI32 field in a BD15 form instruction. */
+#define BI32 BI16 + 1
+ { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
+
+ /* The BO32 field in a BD15 form instruction. */
+#define BO32 BI32 + 1
+ { 0x3, 20, NULL, NULL, 0 },
+
+ /* The B8 field in a BD8 form instruction. */
+#define B8 BO32 + 1
+ { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
+
+ /* The B15 field in a BD15 form instruction. The lowest bit is
+ forced to zero. */
+#define B15 B8 + 1
+ { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
+
+ /* The B24 field in a BD24 form instruction. The lowest bit is
+ forced to zero. */
+#define B24 B15 + 1
+ { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The condition register number portion of the BI field in a B form
or XL form instruction. This is used for the extended
conditional branch mnemonics, which set the lower two bits of the
BI field. This field is optional. */
-#define CR BT + 1
- { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+#define CR B24 + 1
+ { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
/* The CRB field in an X form instruction. */
#define CRB CR + 1
@@ -212,12 +268,19 @@
#define MB_MASK (0x1f << 6)
{ 0x1f, 6, NULL, NULL, 0 },
+ /* The CRD32 field in an XL form instruction. */
+#define CRD32 CRB + 1
+ { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
+
/* The CRFS field in an X form instruction. */
-#define CRFS CRB + 1
- { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
+#define CRFS CRD32 + 1
+ { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
+
+#define CRS CRFS + 1
+ { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
/* The CT field in an X form instruction. */
-#define CT CRFS + 1
+#define CT CRS + 1
/* The MO field in an mbar instruction. */
#define MO CT
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
@@ -228,9 +291,15 @@
#define D CT + 1
{ 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+ /* The D8 field in a D form instruction. This is a displacement off
+ a register, and implies that the next operand is a register in
+ parentheses. */
+#define D8 D + 1
+ { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
/* The DQ field in a DQ form instruction. This is like D, but the
lower four bits are forced to zero. */
-#define DQ D + 1
+#define DQ D8 + 1
{ 0xfff0, 0, NULL, NULL,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
@@ -293,8 +362,12 @@
#define FXM4 FXM + 1
{ 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
+ /* The IMM20 field in an LI instruction. */
+#define IMM20 FXM4 + 1
+ { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
+
/* The L field in a D or X form instruction. */
-#define L FXM4 + 1
+#define L IMM20 + 1
{ 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The LEV field in a POWER SVC form instruction. */
@@ -351,7 +424,7 @@
{ 0xffff, 0, insert_nsi, extract_nsi,
PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
- /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
+ /* The RA field in a D, DS, DQ, X, XO, M, or MDS form instruction. */
#define RA NSI + 1
#define RA_MASK (0x1f << 16)
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
@@ -404,10 +477,11 @@
/* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
instruction or the RT field in a D, DS, X, XFX or XO form
- instruction. */
+ instruction or the RD field in an I16L form instruction. */
#define RS RBOPT + 1
#define RT RS
#define RT_MASK (0x1f << 21)
+#define RD RS
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
/* The RS and RT fields of the DS form stq instruction, which have
@@ -421,8 +495,47 @@
#define RTO RSO
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
+ /* The RX field of the SE_RR form instruction. */
+#define RX RSO + 1
+ { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
+
+ /* The ARX field of the SE_RR form instruction. */
+#define ARX RX + 1
+ { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
+
+ /* The RY field of the SE_RR form instruction. */
+#define RY ARX + 1
+#define RZ RY
+ { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
+
+ /* The ARY field of the SE_RR form instruction. */
+#define ARY RY + 1
+ { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
+
+ /* The SCLSCI8 field in a D form instruction. */
+#define SCLSCI8 ARY + 1
+ { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
+
+ /* The SCLSCI8N field in a D form instruction. This is the same as the
+ SCLSCI8 field, only negated. */
+#define SCLSCI8N SCLSCI8 + 1
+ { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
+ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
+
+ /* The SD field of the SD4 form instruction. */
+#define SE_SD SCLSCI8N + 1
+ { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
+
+ /* The SD field of the SD4 form instruction, for halfword. */
+#define SE_SDH SE_SD + 1
+ { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
+
+ /* The SD field of the SD4 form instruction, for word. */
+#define SE_SDW SE_SDH + 1
+ { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
+
/* The SH field in an X or M form instruction. */
-#define SH RSO + 1
+#define SH SE_SDW + 1
#define SH_MASK (0x1f << 11)
/* The other UIMM field in a EVX form instruction. */
#define EVUIMM SH
@@ -431,7 +544,7 @@
/* The SH field in an MD form instruction. This is split. */
#define SH6 SH + 1
#define SH6_MASK ((0x1f << 11) | (1 << 1))
- { 0x3f, -1, insert_sh6, extract_sh6, 0 },
+ { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
/* The SH field of the tlbwe instruction, which is optional. */
#define SHO SH6 + 1
@@ -446,9 +559,13 @@
#define SISIGNOPT SI + 1
{ 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+ /* The SI8 field in a D form instruction. */
+#define SI8 SISIGNOPT + 1
+ { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
+
/* The SPR field in an XFX form instruction. This is flipped--the
lower 5 bits are stored in the upper 5 and vice- versa. */
-#define SPR SISIGNOPT + 1
+#define SPR SI8 + 1
#define PMR SPR
#define SPR_MASK (0x3ff << 11)
{ 0x3ff, 11, insert_spr, extract_spr, 0 },
@@ -491,8 +608,20 @@
#define UI TO + 1
{ 0xffff, 0, NULL, NULL, 0 },
+ /* The IMM field in an SE_IM5 instruction. */
+#define UI5 UI + 1
+ { 0x1f, 4, NULL, NULL, 0 },
+
+ /* The OIMM field in an SE_OIM5 instruction. */
+#define OIMM5 UI5 + 1
+ { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
+
+ /* The UI7 field in an SE_LI instruction. */
+#define UI7 OIMM5 + 1
+ { 0x7f, 4, NULL, NULL, 0 },
+
/* The VA field in a VA, VX or VXR form instruction. */
-#define VA UI + 1
+#define VA UI7 + 1
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
/* The VB field in a VA, VX or VXR form instruction. */
@@ -540,10 +669,12 @@
/* PowerPC paired singles extensions. */
/* W bit in the pair singles instructions for x type instructions. */
#define PSWM WS + 1
- { 0x1, 10, 0, 0, 0 },
+ /* The BO16 field in a BD8 form instruction. */
+#define BO16 PSWM
+ { 0x1, 10, NULL, NULL, 0 },
/* IDX bits for quantization in the pair singles instructions. */
-#define PSQ PSWM + 1
+#define PSQ BO16 + 1
{ 0x7, 12, 0, 0, 0 },
/* IDX bits for quantization in the pair singles x-type instructions. */
@@ -609,28 +740,46 @@
#define URC URB + 1
{ 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
+ /* The VLESIMM field in a D form instruction. */
+#define VLESIMM URC + 1
+ { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
+ PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+
+ /* The VLENSIMM field in a D form instruction. */
+#define VLENSIMM VLESIMM + 1
+ { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
+ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+
+ /* The VLEUIMM field in a D form instruction. */
+#define VLEUIMM VLENSIMM + 1
+ { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
+
+ /* The VLEUIMML field in a D form instruction. */
+#define VLEUIMML VLEUIMM + 1
+ { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
+
/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
-#define XS6 URC + 1
+#define XS6 VLEUIMML + 1
#define XT6 XS6
- { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
+ { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
/* The XA field in an XX3 form instruction. This is split. */
#define XA6 XT6 + 1
- { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
+ { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
/* The XB field in an XX2 or XX3 form instruction. This is split. */
#define XB6 XA6 + 1
- { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
+ { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
/* The XB field in an XX3 form instruction when it must be the same as
the XA field in the instruction. This is used in extended mnemonics
like xvmovdp. This is split. */
#define XB6S XB6 + 1
- { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
+ { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
/* The XC field in an XX4 form instruction. This is split. */
#define XC6 XB6S + 1
- { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
+ { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
/* The DM or SHW field in an XX3 form instruction. */
#define DM XC6 + 1
@@ -654,6 +803,112 @@
/* The functions used to insert and extract complicated operands. */
+/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
+
+static unsigned long
+insert_arx (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value >= 8 && value < 24)
+ return insn | ((value - 8) & 0xf);
+ else
+ {
+ *errmsg = _("invalid register");
+ return 0;
+ }
+}
+
+static long
+extract_arx (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return (insn & 0xf) + 8;
+}
+
+static unsigned long
+insert_ary (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value >= 8 && value < 24)
+ return insn | (((value - 8) & 0xf) << 4);
+ else
+ {
+ *errmsg = _("invalid register");
+ return 0;
+ }
+}
+
+static long
+extract_ary (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 4) & 0xf) + 8;
+}
+
+static unsigned long
+insert_rx (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value >=0 && value < 8)
+ return insn | value;
+ else if (value >= 24 && value <= 31)
+ return insn | (value - 16);
+ else
+ {
+ *errmsg = _("invalid register");
+ return 0;
+ }
+}
+
+static long
+extract_rx (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ int value = insn & 0xf;
+ if (value >=0 && value < 8)
+ return value;
+ else
+ return value + 16;
+}
+
+static unsigned long
+insert_ry (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value >=0 && value < 8)
+ return insn | (value << 4);
+ else if (value >= 24 && value <= 31)
+ return insn | ((value - 16) << 4);
+ else
+ {
+ *errmsg = _("invalid register");
+ return 0;
+ }
+}
+
+static long
+extract_ry (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 4) & 0xf;
+ if (value >=0 && value < 8)
+ return value;
+ else
+ return value + 16;
+}
+
/* The BA field in an XL form instruction when it must be the same as
the BT field in the same instruction. This operand is marked FAKE.
The insertion function just copies the BT field into the BA field,
@@ -996,6 +1251,32 @@
return mask;
}
+static unsigned long
+insert_li20 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn
+ | ((value & 0xf0000) >> 5)
+ | ((value & 0x0f800) << 5)
+ | (value & 0x7ff);
+}
+
+static long
+extract_li20 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
+
+ return ext
+ | (((insn >> 11) & 0xf) << 16)
+ | (((insn >> 17) & 0xf) << 12)
+ | (((insn >> 16) & 0x1) << 11)
+ | (insn & 0x7ff);
+}
+
/* The MB and ME fields in an M form instruction expressed as a single
operand which is itself a bitmask. The extraction function always
marks it as invalid, since we never want to recognize an
@@ -1229,6 +1510,166 @@
return 0;
}
+/* The SCI8 field is made up of SCL and {U,N}I8 fields. */
+static unsigned long
+insert_sci8 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ int fill = 0;
+ int scale_factor = 0;
+ long ui8 = value;
+
+ if ((value & 0xff000000) == (unsigned int) value)
+ {
+ scale_factor = 3;
+ ui8 = value >> 24;
+ fill = 0;
+ }
+ else if ((value & 0xff0000) == (unsigned int) value)
+ {
+ scale_factor = 2;
+ ui8 = value >> 16;
+ fill = 0;
+ }
+ else if ((value & 0xff00) == (unsigned int) value)
+ {
+ scale_factor = 1;
+ ui8 = value >> 8;
+ fill = 0;
+ }
+ else if ((value & 0xff) == value)
+ {
+ scale_factor = 0;
+ ui8 = value;
+ fill = 0;
+ }
+ else if ((value & 0xffffff00) == 0xffffff00)
+ {
+ scale_factor = 0;
+ ui8 = (value & 0xff);
+ fill = 1;
+ }
+ else if ((value & 0xffff00ff) == 0xffff00ff)
+ {
+ scale_factor = 1;
+ ui8 = (value & 0xff00) >> 8;
+ fill = 1;
+ }
+ else if ((value & 0xff00ffff) == 0xff00ffff)
+ {
+ scale_factor = 2;
+ ui8 = (value & 0xff0000) >> 16;
+ fill = 1;
+ }
+ else if ((value & 0x00ffffff) == 0x00ffffff)
+ {
+ scale_factor = 3;
+ ui8 = (value & 0xff000000) >> 24;
+ fill = 1;
+ }
+ else
+ *errmsg = _("illegal immediate value");
+
+ return insn | (fill << 10) | (scale_factor << 8) | (ui8 & 0xff);
+}
+
+static long
+extract_sci8 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ int scale_factor, fill;
+ scale_factor = (insn & 0x300) >> 8;
+ fill = (insn & 0x00000400) >> 10;
+
+ if (fill == 0)
+ return (insn & 0xff) << (scale_factor << 3);
+
+ /* Fill is one. */
+ if (scale_factor == 0)
+ return (insn & 0xff) | 0xffffff00;
+ else if (scale_factor == 1)
+ return 0xffff00ff | ((insn & 0xff) << (scale_factor << 3));
+ else if (scale_factor == 2)
+ return 0xff00ffff | (insn & 0xff << (scale_factor << 3));
+ else /* scale_factor 3 */
+ return 0x00ffffff | (insn & 0xff << (scale_factor << 3));
+}
+
+static unsigned long
+insert_sci8n (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ insn = insert_sci8 (insn, -(value & 0xff) & 0xff, 0, errmsg);
+ /* Set the F bit. */
+ return insn | 0x400;
+}
+
+static long
+extract_sci8n (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ int scale_factor;
+ scale_factor = (insn & 0x300) >> 8;
+ return -(((insn & 0xff) ^ 0x80) - 0x80) << (scale_factor << 3);
+}
+
+static unsigned long
+insert_sd4h (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x1e) << 7);
+}
+
+static long
+extract_sd4h (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 8) & 0xf) << 1;
+}
+
+static unsigned long
+insert_sd4w (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x3c) << 6);
+}
+
+static long
+extract_sd4w (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 8) & 0xf) << 2;
+}
+
+static unsigned long
+insert_oimm (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | (((value - 1) & 0x1f) << 4);
+}
+
+static long
+extract_oimm (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 4) & 0x1f) + 1;
+}
+
/* The SH field in an MD form instruction. This is split. */
static unsigned long
@@ -1269,6 +1710,7 @@
}
/* Some dialects have 8 SPRG registers instead of the standard 4. */
+#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
static unsigned long
insert_sprg (unsigned long insn,
@@ -1278,7 +1720,7 @@
{
if (value > 7
|| (value > 3
- && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
+ && (dialect & ALLOW8_SPRG) == 0))
*errmsg = _("invalid sprg number");
/* If this is mfsprg4..7 then use spr 260..263 which can be read in
@@ -1298,7 +1740,7 @@
/* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
If not BOOKE or 405, then both use only 272..275. */
- if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
+ if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
|| (val - 0x10 > 7 && (insn & 0x100) != 0)
|| val <= 3
|| (val & 8) != 0)
@@ -1465,6 +1907,89 @@
*invalid = 1;
return (value) ? 1 : 0;
}
+
+/* The VLESIMM field in an I16A form instruction. This is split. */
+
+static unsigned long
+insert_vlesi (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
+}
+
+static long
+extract_vlesi (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
+ if (value & 0x8000)
+ value |= 0xffff0000;
+ return value;
+}
+
+static unsigned long
+insert_vlensi (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ value = -value;
+ return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
+}
+
+static long
+extract_vlensi (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
+ if (value & 0x8000)
+ value |= 0xffff0000;
+ *invalid = 1;
+ return -value;
+}
+
+/* The VLEUIMM field in an I16A form instruction. This is split. */
+
+static unsigned long
+insert_vleui (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
+}
+
+static long
+extract_vleui (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
+}
+
+/* The VLEUIMML field in an I16L form instruction. This is split. */
+
+static unsigned long
+insert_vleil (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
+}
+
+static long
+extract_vleil (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
+}
+
/* Macros used to form opcodes. */
@@ -1484,6 +2009,11 @@
#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
#define OPL_MASK OPL (0x3f,1)
+/* The main opcode combined with an update code in D form instruction.
+ Used for extended mnemonics for VLE memory instructions. */
+#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
+#define OPVUP_MASK OPVUP (0x3f, 0xff)
+
/* An A form instruction. */
#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
#define A_MASK A (0x3f, 0x1f, 1)
@@ -1504,6 +2034,43 @@
#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
#define B_MASK B (0x3f, 1, 1)
+/* A BD8 form instruction. This is a 16-bit instruction. */
+#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
+#define BD8_MASK BD8 (0x3f, 1, 1)
+
+/* Another BD8 form instruction. This is a 16-bit instruction. */
+#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
+#define BD8IO_MASK BD8IO (0x1f)
+
+/* A BD8 form instruction for simplified mnemonics. */
+#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
+/* A mask that excludes BO32 and BI32. */
+#define EBD8IO1_MASK 0xf800
+/* A mask that includes BO32 and excludes BI32. */
+#define EBD8IO2_MASK 0xfc00
+/* A mask that include BO32 AND BI32. */
+#define EBD8IO3_MASK 0xff00
+
+/* A BD15 form instruction. */
+#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
+#define BD15_MASK BD15 (0x3f, 0xf, 1)
+
+/* A BD15 form instruction for extended conditional branch mnemonics. */
+#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
+#define EBD15_MASK 0xfff00001
+
+/* A BD15 form instruction for extended conditional branch mnemonics with BI. */
+#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
+ | (((aa) & 0xf) << 22) \
+ | (((bo) & 0x3) << 20) \
+ | (((bi) & 0x3) << 16) \
+ | ((lk) & 1)
+#define EBD15BI_MASK 0xfff30001
+
+/* A BD24 form instruction. */
+#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
+#define BD24_MASK BD24 (0x3f, 1, 1)
+
/* A B form instruction setting the BO field. */
#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
@@ -1532,11 +2099,17 @@
#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
-/* An Context form instruction. */
+/* A VLE C form instruction. */
+#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
+#define C_LK_MASK C_LK(0x7fff, 1)
+#define C(x) ((((unsigned long)(x)) & 0xffff))
+#define C_MASK C(0xffff)
+
+/* A Context form instruction. */
#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
#define CTX_MASK CTX(0x3f, 0x7)
-/* An User Context form instruction. */
+/* A User Context form instruction. */
#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
#define UCTX_MASK UCTX(0x3f, 0x1f)
@@ -1551,10 +2124,30 @@
#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
#define EVSEL_MASK EVSEL(0x3f, 0xff)
+/* An IA16 form instruction. */
+#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
+#define IA16_MASK IA16(0x3f, 0x1f)
+
+/* An I16A form instruction. */
+#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
+#define I16A_MASK I16A(0x3f, 0x1f)
+
+/* An I16L form instruction. */
+#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
+#define I16L_MASK I16L(0x3f, 0x1f)
+
+/* An IM7 form instruction. */
+#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
+#define IM7_MASK IM7(0x1f)
+
/* An M form instruction. */
#define M(op, rc) (OP (op) | ((rc) & 1))
#define M_MASK M (0x3f, 1)
+/* An LI20 form instruction. */
+#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
+#define LI20_MASK LI20(0x3f, 0x1)
+
/* An M form instruction with the ME field specified. */
#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
@@ -1585,19 +2178,43 @@
#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
-/* An VX form instruction. */
+/* An SCI8 form instruction. */
+#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
+#define SCI8_MASK SCI8(0x3f, 0x1f)
+
+/* An SCI8 form instruction. */
+#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
+#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
+
+/* An SD4 form instruction. This is a 16-bit instruction. */
+#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
+#define SD4_MASK SD4(0xf)
+
+/* An SE_IM5 form instruction. This is a 16-bit instruction. */
+#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
+#define SE_IM5_MASK SE_IM5(0x3f, 1)
+
+/* An SE_R form instruction. This is a 16-bit instruction. */
+#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
+#define SE_R_MASK SE_R(0x3f, 0x3f)
+
+/* An SE_RR form instruction. This is a 16-bit instruction. */
+#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
+#define SE_RR_MASK SE_RR(0x3f, 3)
+
+/* A VX form instruction. */
#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
-/* The mask for an VX form instruction. */
+/* The mask for a VX form instruction. */
#define VX_MASK VX(0x3f, 0x7ff)
-/* An VA form instruction. */
+/* A VA form instruction. */
#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
-/* The mask for an VA form instruction. */
+/* The mask for a VA form instruction. */
#define VXA_MASK VXA(0x3f, 0x3f)
-/* An VXR form instruction. */
+/* A VXR form instruction. */
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
/* The mask for a VXR form instruction. */
@@ -1606,6 +2223,12 @@
/* An X form instruction. */
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
+/* An EX form instruction. */
+#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
+
+/* The mask for an EX form instruction. */
+#define EX_MASK EX (0x3f, 0x7ff)
+
/* An XX2 form instruction. */
#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
@@ -1874,6 +2497,16 @@
#define BOU (0x14)
+/* The BO16 encodings used in extended VLE conditional branch mnemonics. */
+#define BO16F (0x0)
+#define BO16T (0x1)
+
+/* The BO32 encodings used in extended VLE conditional branch mnemonics. */
+#define BO32F (0x0)
+#define BO32T (0x1)
+#define BO32DNZ (0x2)
+#define BO32DZ (0x3)
+
/* The BI condition bit encodings used in extended conditional branch
mnemonics. */
#define CBLT (0)
@@ -1933,11 +2566,11 @@
#define MFDEC1 PPC_OPCODE_POWER
#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
#define BOOKE PPC_OPCODE_BOOKE
-#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_EFS
+#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_EFS | PPC_OPCODE_VLE
#define PPCE300 PPC_OPCODE_E300
-#define PPCSPE PPC_OPCODE_SPE
-#define PPCISEL PPC_OPCODE_ISEL
-#define PPCEFS PPC_OPCODE_EFS
+#define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE
+#define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
+#define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE
#define PPCBRLK PPC_OPCODE_BRLOCK
#define PPCPMR PPC_OPCODE_PMR
#define PPCCHLK PPC_OPCODE_CACHELCK
@@ -1945,20 +2578,23 @@
#define E500MC PPC_OPCODE_E500MC
#define PPCA2 PPC_OPCODE_A2
#define TITAN PPC_OPCODE_TITAN
-#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
+#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
#define E500 PPC_OPCODE_E500
+#define PPCVLE PPC_OPCODE_VLE
/* The opcode table.
The format of the opcode table is:
- NAME OPCODE MASK FLAGS {OPERANDS}
+ NAME OPCODE MASK FLAGS DEPRECATED {OPERANDS}
NAME is the name of the instruction.
OPCODE is the instruction opcode.
MASK is the opcode mask; this is used to tell the disassembler
which bits in the actual opcode must match OPCODE.
FLAGS are flags indicated what processors support the instruction.
+ DEPRECATED are flags that indicate what processors no longer
+ support the instruction.
OPERANDS is the list of operands.
The disassembler reads the table in order and prints the first
@@ -1970,7 +2606,36 @@
constrained otherwise by disassembler operation. */
const struct powerpc_opcode powerpc_opcodes[] = {
+
+{"se_illegal", C(0), C_MASK, PPCVLE, PPCNONE, {}},
+{"se_isync", C(1), C_MASK, PPCVLE, PPCNONE, {}},
+{"se_sc", C(2), C_MASK, PPCVLE, PPCNONE, {}},
+{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, PPCNONE, {}},
+{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, PPCNONE, {}},
+{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, PPCNONE, {}},
+{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, PPCNONE, {}},
+{"se_rfi", C(8), C_MASK, PPCVLE, PPCNONE, {}},
+{"se_rfci", C(9), C_MASK, PPCVLE, PPCNONE, {}},
+{"se_rfdi", C(10), C_MASK, PPCVLE, PPCNONE, {}},
+{"se_rfmci", C(11), C_MASK, PPCVLE, PPCNONE, {}},
+{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
+{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, PPCNONE, {ARX, RY}},
+{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, ARY}},
{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476, {0}},
+{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
@@ -1987,6 +2652,10 @@
{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
{"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}},
+{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
@@ -2611,32 +3280,82 @@
{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}},
+{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}},
+#if 0
+{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}},
+#endif
+{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}},
+#if 0
+{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}},
+#endif
+{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}},
+{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}},
+{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}},
+{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
+{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, PPCNONE, {0}},
+{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
+{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
+{"e_add16i", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, RA, SI}},
+{"e_la", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+{"e_sub16i", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, RA, NSI}},
+
{"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
{"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
+{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
+{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
+
{"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
{"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
+{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
+{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
{"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}},
{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}},
+{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}},
{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}},
{"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}},
-{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}},
+{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM|PPCVLE, PPCNONE, {OBF, RA, SI}},
{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}},
{"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}},
{"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}},
+{"e_lbz", OP(12), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
{"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
{"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
{"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
+{"e_stb", OP(13), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+
{"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
{"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
{"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
+{"e_lha", OP(14), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
{"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}},
{"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}},
{"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}},
@@ -2644,12 +3363,16 @@
{"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
{"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
+
{"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}},
{"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}},
{"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
{"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
+{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
@@ -2922,11 +3645,17 @@
{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
{"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
+{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, PPCNONE, {0}},
+{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
+{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
{"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
{"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
{"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}},
{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
{"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}},
+{"se_li", IM7(9), IM7_MASK, PPCVLE, PPCNONE, {RX, UI7}},
{"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}},
{"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}},
@@ -3358,12 +4087,15 @@
{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
+{"e_lwz", OP(20), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
{"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
+{"e_stw", OP(21), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+
{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
@@ -3373,9 +4105,13 @@
{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
+{"e_lhz", OP(22), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+
{"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
{"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
+{"e_sth", OP(23), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
+
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
@@ -3383,25 +4119,94 @@
{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
+{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
{"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}},
{"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
{"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
{"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
{"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
+{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
{"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
{"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
{"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
{"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+
+{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
+{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
+{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
+{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
+{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
+{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, PPCNONE, {RA, VLEUIMM}},
+{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, PPCNONE, {RA, VLEUIMM}},
+{"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+{"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, PPCNONE, {RA, VLENSIMM}},
+{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, PPCNONE, {RA, VLENSIMM}},
+{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
+{"e_li", LI20(28,0), LI20_MASK, PPCVLE, PPCNONE, {RT, IMM20}},
+
{"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
{"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+{"e_rlwimi", M(29,0), M_MASK, PPCVLE, PPCNONE, {RA, RS, SH, MB, ME}},
+{"e_rlwinm", M(29,1), M_MASK, PPCVLE, PPCNONE, {RA, RT, SH, MBE, ME}},
+
{"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
{"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
+{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, PPCNONE, {B24}},
+{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, PPCNONE, {B24}},
+{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, PPCNONE, {BO32, BI32, B15}},
+{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, PPCNONE, {BO32, BI32, B15}},
+
+{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
+{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
+{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
+{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
+
+{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
+
+{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
+
{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
@@ -3426,64 +4231,88 @@
{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
-{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
+{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM|PPCVLE, PPCNONE, {OBF, RA, RB}},
{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
-{"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
+{"cmp", X(31,0), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}},
{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
-{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"e_cmph", X(31,14), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}},
+{"e_cmphl", X(31,46), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}},
+{"e_crand", XL(31,257), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+{"e_crandc", XL(31,129), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+{"e_crset", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}},
+{"e_creqv", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+{"e_crnand", XL(31,225), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+{"e_crnot", XL(31,33), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}},
+{"e_crnor", XL(31,33), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+{"e_crmove", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}},
+{"e_cror", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+{"e_crorc", XL(31,417), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+{"e_crclr", XL(31,193), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}},
+{"e_crxor", XL(31,193), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
+{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, PPCNONE, {CRD, CR}},
+{"e_rlw", EX(31,560), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}},
+{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}},
+{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+{"e_slwi", EX(31,112), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
+
+{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
+{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
-{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, PPCNONE, {0}},
-{"tw", X(31,4), X_MASK, PPCCOM, PPCNONE, {TO, RA, RB}},
+{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM|PPCVLE, PPCNONE, {0}},
+{"tw", X(31,4), X_MASK, PPCCOM|PPCVLE, PPCNONE, {TO, RA, RB}},
{"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
{"lvsl", X(31,6), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
{"lvebx", X(31,7), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
-{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"subc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
+{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
+{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
-{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
+{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"addc", XO(31,10,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
+{"mulhwu", XO(31,11,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
@@ -3493,43 +4322,43 @@
{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}},
{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
-{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}},
-{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}},
+{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4, {RT}},
+{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM}},
-{"lwarx", X(31,20), XEH_MASK, PPC, PPCNONE, {RT, RA0, RB, EH}},
+{"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
-{"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
+{"ldx", X(31,21), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}},
-{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}},
+{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA, RB}},
-{"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
+{"lwzx", X(31,23), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}},
{"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"slw", XRC(31,24,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
+{"slw", XRC(31,24,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
-{"slw.", XRC(31,24,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
+{"slw.", XRC(31,24,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
-{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
+{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
-{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
+{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
{"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
{"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-{"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
+{"and", XRC(31,28,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+{"and.", XRC(31,28,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
-{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
-{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
+{"ldepx", X(31,29), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"lwepx", X(31,31), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
+{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM|PPCVLE, PPCNONE, {OBF, RA, RB}},
{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
-{"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
+{"cmpl", X(31,32), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}},
{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
{"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
@@ -3546,33 +4375,33 @@
{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE, {RT, RA, RB, CRB}},
-{"subf", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"sub", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
-{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
+{"subf", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"sub", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}},
+{"subf.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"sub.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}},
{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
{"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
-{"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
+{"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
-{"dcbst", X(31,54), XRT_MASK, PPC, PPCNONE, {RA, RB}},
+{"dcbst", X(31,54), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA, RB}},
-{"lwzux", X(31,55), X_MASK, PPCCOM, PPCNONE, {RT, RAL, RB}},
+{"lwzux", X(31,55), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RAL, RB}},
{"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
-{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
+{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
+{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
-{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
+{"andc", XRC(31,60,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+{"andc.", XRC(31,60,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
-{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2, PPCNONE, {WC}},
+{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
-{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
+{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA, RB}},
{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
@@ -3588,36 +4417,36 @@
{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
-{"td", X(31,68), X_MASK, PPC64, PPCNONE, {TO, RA, RB}},
+{"td", X(31,68), X_MASK, PPC64|PPCVLE, PPCNONE, {TO, RA, RB}},
{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
+{"mulhd", XO(31,73,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"mulhw", XO(31,75,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
+{"mulhw", XO(31,75,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"mulhw.", XO(31,75,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}},
{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}},
{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}},
-{"mfmsr", X(31,83), XRARB_MASK, COM, PPCNONE, {RT}},
+{"mfmsr", X(31,83), XRARB_MASK, COM|PPCVLE, PPCNONE, {RT}},
-{"ldarx", X(31,84), XEH_MASK, PPC64, PPCNONE, {RT, RA0, RB, EH}},
+{"ldarx", X(31,84), XEH_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA, RB}},
-{"dcbf", X(31,86), XLRT_MASK, PPC, PPCNONE, {RA, RB, L}},
+{"dcbf", X(31,86), XLRT_MASK, PPC|PPCVLE, PPCNONE, {RA, RB, L}},
-{"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
+{"lbzx", X(31,87), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
-{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
+{"lbepx", X(31,95), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA, RB}},
{"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"neg", XO(31,104,0,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
-{"neg.", XO(31,104,0,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
+{"neg", XO(31,104,0,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
+{"neg.", XO(31,104,0,1), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
{"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
{"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
@@ -3628,50 +4457,50 @@
{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
-{"lbzux", X(31,119), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
+{"lbzux", X(31,119), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
-{"popcntb", X(31,122), XRB_MASK, POWER5, PPCNONE, {RA, RS}},
+{"popcntb", X(31,122), XRB_MASK, POWER5|PPCVLE, PPCNONE, {RA, RS}},
{"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
-{"nor", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
+{"nor", XRC(31,124,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
-{"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
+{"nor.", XRC(31,124,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
-{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
+{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA, RB}},
-{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
+{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
-{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
+{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}},
{"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"adde", XO(31,138,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
-{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
-{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
+{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {FXM, RS}},
+{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {FXM, RS}},
-{"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}},
+{"mtmsr", X(31,146),XRLARB_MASK, COM|PPCVLE, PPCNONE, {RS, A_L}},
{"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
-{"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
+{"stdx", X(31,149), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}},
-{"stwcx.", XRC(31,150,1), X_MASK, PPC, PPCNONE, {RS, RA0, RB}},
+{"stwcx.", XRC(31,150,1), X_MASK, PPC|PPCVLE, PPCNONE, {RS, RA0, RB}},
-{"stwx", X(31,151), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
+{"stwx", X(31,151), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}},
{"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}},
{"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
@@ -3682,13 +4511,13 @@
{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
-{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
+{"stdepx", X(31,157), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA, RB}},
-{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
+{"stwepx", X(31,159), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA, RB}},
-{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}},
+{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}},
-{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
+{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}},
{"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
@@ -3699,11 +4528,11 @@
{"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}},
-{"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}},
+{"stdux", X(31,181), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RAS, RB}},
{"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}},
-{"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}},
+{"stwux", X(31,183), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RAS, RB}},
{"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
{"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
@@ -3714,17 +4543,17 @@
{"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE, {RB}},
+{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
@@ -3732,9 +4561,9 @@
{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
-{"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
+{"stdcx.", XRC(31,214,1), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}},
-{"stbx", X(31,215), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
+{"stbx", X(31,215), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}},
{"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
@@ -3742,41 +4571,41 @@
{"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
+{"stbepx", X(31,223), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA, RB}},
-{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
+{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}},
{"stvx", X(31,231), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"mulld", XO(31,233,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
+{"mulld", XO(31,233,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"mulld.", XO(31,233,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
-{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE, {RB}},
+{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
-{"dcbtst", X(31,246), X_MASK, PPC, POWER4, {CT, RA, RB}},
+{"dcbtst", X(31,246), X_MASK, PPC|PPCVLE, POWER4, {CT, RA, RB}},
-{"stbux", X(31,247), X_MASK, COM, PPCNONE, {RS, RAS, RB}},
+{"stbux", X(31,247), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
@@ -3785,7 +4614,7 @@
{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
-{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
+{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}},
{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}},
{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
@@ -3794,9 +4623,9 @@
{"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
{"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-{"add", XO(31,266,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"add", XO(31,266,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"add.", XO(31,266,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
@@ -3810,32 +4639,32 @@
{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
{"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
-{"dcbt", X(31,278), X_MASK, PPC, POWER4, {CT, RA, RB}},
+{"dcbt", X(31,278), X_MASK, PPC|PPCVLE, POWER4, {CT, RA, RB}},
-{"lhzx", X(31,279), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
+{"lhzx", X(31,279), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
{"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
-{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
+{"eqv", XRC(31,284,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+{"eqv.", XRC(31,284,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
-{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
+{"lhepx", X(31,287), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}},
+{"mfdcrux", X(31,291), X_MASK, PPC464|PPCVLE, PPCNONE, {RS, RA}},
{"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}},
{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
{"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA, RB}},
-{"lhzux", X(31,311), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
+{"lhzux", X(31,311), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
{"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
-{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
+{"xor", XRC(31,316,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+{"xor.", XRC(31,316,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
-{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
+{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA, RB}},
{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}},
@@ -3871,7 +4700,7 @@
{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
-{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT, SPR}},
+{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RT, SPR}},
{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
{"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA, RB}},
@@ -3881,15 +4710,15 @@
{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}},
+{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}},
{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
-{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}},
+{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}},
-{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, PPCNONE, {RT}},
-{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, PPCNONE, {RT}},
+{"mflr", XSPR(31,339, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
+{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
@@ -3899,12 +4728,12 @@
{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}},
{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}},
{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}},
-{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, PPCNONE, {RT}},
+{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}},
{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}},
{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}},
@@ -3922,53 +4751,53 @@
{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}},
{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}},
{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}},
-{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, PPCNONE, {RT, SPRG}},
-{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
-{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
-{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
-{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}},
-{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, PPCNONE, {RT}},
-{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, PPCNONE, {RT}},
-{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, PPCNONE, {RT}},
-{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, PPCNONE, {RT}},
+{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE, {RT, SPRG}},
+{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}},
{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
-{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, PPCNONE, {RT}},
-{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, PPCNONE, {RT}},
-{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, PPCNONE, {RT}},
+{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
+{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
+{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
@@ -4079,13 +4908,13 @@
{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}},
{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}},
-{"mfspr", X(31,339), X_MASK, COM, PPCNONE, {RT, SPR}},
+{"mfspr", X(31,339), X_MASK, COM|PPCVLE, PPCNONE, {RT, SPR}},
-{"lwax", X(31,341), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
+{"lwax", X(31,341), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}},
{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
-{"lhax", X(31,343), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
+{"lhax", X(31,343), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
{"lvxl", X(31,359), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
@@ -4101,18 +4930,18 @@
{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}},
{"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371|POWER7, {RT, TBR}},
-{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
+{"lwaux", X(31,373), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
-{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
+{"lhaux", X(31,375), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
-{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}},
+{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2|PPCVLE, PPCNONE, {RA, RS}},
-{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
+{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}},
{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
@@ -4127,14 +4956,14 @@
{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
-{"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
+{"sthx", X(31,407), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}},
-{"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
+{"orc", XRC(31,412,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+{"orc.", XRC(31,412,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
-{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
+{"sthepx", X(31,415), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA, RB}},
-{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}},
+{"mtdcrux", X(31,419), X_MASK, PPC464|PPCVLE, PPCNONE, {RA, RS}},
{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
@@ -4145,14 +4974,14 @@
{"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA, RB}},
-{"sthux", X(31,439), X_MASK, COM, PPCNONE, {RS, RAS, RB}},
+{"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
{"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}},
-{"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
-{"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
-{"or.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
+{"mr", XRC(31,444,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RBS}},
+{"or", XRC(31,444,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+{"mr.", XRC(31,444,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RBS}},
+{"or.", XRC(31,444,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}},
{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}},
@@ -4188,24 +5017,24 @@
{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
-{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {SPR, RS}},
+{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {SPR, RS}},
{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
-{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}},
+{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
-{"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
+{"divdu", XO(31,457,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divdu.", XO(31,457,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"divwu", XO(31,459,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
+{"divwu", XO(31,459,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divwu.", XO(31,459,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}},
+{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}},
{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
-{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}},
-{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, PPCNONE, {RS}},
-{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, PPCNONE, {RS}},
+{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
+{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}},
{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
@@ -4217,13 +5046,13 @@
{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, PPCNONE, {RS}},
{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, PPCNONE, {RS}},
{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}},
-{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, PPCNONE, {RS}},
+{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}},
{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}},
{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}},
@@ -4241,50 +5070,50 @@
{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}},
{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}},
{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}},
-{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, PPCNONE, {SPRG, RS}},
-{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, PPCNONE, {RS}},
-{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, PPCNONE, {RS}},
-{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, PPCNONE, {RS}},
-{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, PPCNONE, {RS}},
-{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
-{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
-{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
-{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}},
+{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC|PPCVLE, PPCNONE, {SPRG, RS}},
+{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
+{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
+{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
+{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
+{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}},
{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}},
{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}},
-{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, PPCNONE, {RS}},
-{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, PPCNONE, {RS}},
+{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
+{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
@@ -4299,6 +5128,7 @@
{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
+{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, PPCNONE, {RS}},
{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, PPCNONE, {RS}},
{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, PPCNONE, {RS}},
{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, PPCNONE, {RS}},
@@ -4362,29 +5192,29 @@
{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}},
{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}},
{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}},
-{"mtspr", X(31,467), X_MASK, COM, PPCNONE, {SPR, RS}},
+{"mtspr", X(31,467), X_MASK, COM|PPCVLE, PPCNONE, {SPR, RS}},
-{"dcbi", X(31,470), XRT_MASK, PPC, PPCNONE, {RA, RB}},
+{"dcbi", X(31,470), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA, RB}},
-{"nand", XRC(31,476,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"nand.", XRC(31,476,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
+{"nand", XRC(31,476,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
+{"nand.", XRC(31,476,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA, RB}},
-{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
+{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}},
{"stvxl", X(31,487), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
{"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
{"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
-{"divd", XO(31,489,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-{"divd.", XO(31,489,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
+{"divd", XO(31,489,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divd.", XO(31,489,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
+{"divw", XO(31,491,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divw.", XO(31,491,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"icbtlse", X(31,494), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
@@ -4396,7 +5226,7 @@
{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS, RB}},
-{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}},
+{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM|PPCVLE, POWER7, {BF}},
{"lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
@@ -4405,40 +5235,40 @@
{"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
-{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"subco", XO(31,8,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
+{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
+{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
-{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"addco", XO(31,10,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}},
-{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RA0, RB}},
+{"lswx", X(31,533), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RA0, RB}},
{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
+{"lwbrx", X(31,534), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}},
{"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
-{"srw", XRC(31,536,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
+{"srw", XRC(31,536,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
-{"srw.", XRC(31,536,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
+{"srw.", XRC(31,536,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
{"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-{"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
-{"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
+{"srd", XRC(31,539,0), X_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, RB}},
+{"srd.", XRC(31,539,1), X_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, RB}},
{"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
@@ -4450,12 +5280,12 @@
{"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
-{"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
+{"subfo", XO(31,40,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"subo", XO(31,40,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}},
+{"subfo.", XO(31,40,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"subo.", XO(31,40,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}},
-{"tlbsync", X(31,566), 0xffffffff, PPC, PPCNONE, {0}},
+{"tlbsync", X(31,566), 0xffffffff, PPC|PPCVLE, PPCNONE, {0}},
{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
@@ -4467,12 +5297,12 @@
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
-{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RA0, NB}},
+{"lswi", X(31,597), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RA0, NB}},
{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
-{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
+{"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476, {LS}},
{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, PPCNONE, {0}},
{"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}},
@@ -4481,14 +5311,14 @@
{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
-{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, PPCNONE, {FRT, RA, RB}},
+{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA, RB}},
{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
-{"nego.", XO(31,104,1,1), XORB_MASK, COM, PPCNONE, {RT, RA}},
+{"nego", XO(31,104,1,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
+{"nego.", XO(31,104,1,1), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
@@ -4504,24 +5334,24 @@
{"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}},
-{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
+{"stswx", X(31,661), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, RB}},
{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
-{"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
+{"stwbrx", X(31,662), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}},
{"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
@@ -4550,17 +5380,17 @@
{"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
+{"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}},
{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
{"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
@@ -4574,23 +5404,23 @@
{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
-{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, PPCNONE, {FRS, RA, RB}},
+{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRS, RA, RB}},
{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
+{"mulldo", XO(31,233,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
+{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
@@ -4598,7 +5428,7 @@
{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
+{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA, RB}},
{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
@@ -4612,14 +5442,14 @@
{"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
{"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"addo", XO(31,266,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
+{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
+{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA, RB}},
{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
@@ -4628,9 +5458,9 @@
{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRT, RA, RB}},
{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
-{"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
+{"sraw", XRC(31,792,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
-{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
+{"sraw.", XRC(31,792,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
{"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
{"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
@@ -4650,13 +5480,13 @@
{"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
-{"srawi", XRC(31,824,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
+{"srawi", XRC(31,824,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, SH}},
{"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
-{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
-{"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
+{"srawi.", XRC(31,824,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, SH}},
+{"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
-{"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
-{"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
+{"sradi", XS(31,413,0), XS_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, SH6}},
+{"sradi.", XS(31,413,1), XS_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, SH6}},
{"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
{"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
@@ -4670,7 +5500,7 @@
{"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
-{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO}},
+{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {MO}},
{"eieio", XMBAR(31,854,1),0xffffffff, E500, PPCNONE, {0}},
{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, PPCNONE, {0}},
@@ -4697,13 +5527,13 @@
{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
-{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
+{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RTO, RA, RB}},
{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
{"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
-{"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
+{"sthbrx", X(31,918), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}},
{"stfdpx", X(31,919), X_MASK, POWER6, PPCNONE, {FRS, RA, RB}},
{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
@@ -4714,9 +5544,9 @@
{"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
+{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
-{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}},
+{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
{"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
@@ -4734,7 +5564,7 @@
{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
-{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
+{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RSO, RAOPT, SHO}},
{"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
@@ -4746,55 +5576,55 @@
{"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
{"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-{"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}},
-{"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}},
+{"extsb", XRC(31,954,0), XRB_MASK, PPC|PPCVLE, PPCNONE, {RA, RS}},
+{"extsb.", XRC(31,954,1), XRB_MASK, PPC|PPCVLE, PPCNONE, {RA, RS}},
{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
-{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}},
+{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
-{"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
+{"divduo", XO(31,457,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divduo.", XO(31,457,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"divwuo", XO(31,459,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
+{"divwuo", XO(31,459,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divwuo.", XO(31,459,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
-{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
+{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RSO, RAOPT, SHO}},
{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
-{"icbi", X(31,982), XRT_MASK, PPC, PPCNONE, {RA, RB}},
+{"icbi", X(31,982), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA, RB}},
{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
-{"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
-{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
+{"extsw", XRC(31,986,0), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
+{"extsw.", XRC(31,986,1), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
-{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
+{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA, RB}},
-{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}},
+{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA, RB}},
{"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
{"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
-{"divdo", XO(31,489,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
-{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
+{"divdo", XO(31,489,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divdo.", XO(31,489,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
-{"divwo", XO(31,491,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
-{"divwo.", XO(31,491,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
+{"divwo", XO(31,491,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"divwo.", XO(31,491,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
{"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
-{"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
+{"dcbz", X(31,1014), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA, RB}},
{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
-{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
+{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA, RB}},
{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA, RB}},
@@ -4811,6 +5641,7 @@
{"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}},
{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}},
+{"se_lbz", SD4(8), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}},
{"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
{"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
@@ -4820,6 +5651,7 @@
{"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
{"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
+{"se_stb", SD4(9), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}},
{"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
{"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
@@ -4830,6 +5662,7 @@
{"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
{"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
+{"se_lhz", SD4(10), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}},
{"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
@@ -4838,6 +5671,7 @@
{"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
{"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
+{"se_sth", SD4(11), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}},
{"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
@@ -4849,6 +5683,7 @@
{"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
{"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
+{"se_lwz", SD4(12), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}},
{"lfs", OP(48), OP_MASK, COM, PPCEFS, {FRT, D, RA0}},
{"lfsu", OP(49), OP_MASK, COM, PPCEFS, {FRT, D, RAS}},
@@ -4857,6 +5692,7 @@
{"lfdu", OP(51), OP_MASK, COM, PPCEFS, {FRT, D, RAS}},
+{"se_stw", SD4(13), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}},
{"stfs", OP(52), OP_MASK, COM, PPCEFS, {FRS, D, RA0}},
{"stfsu", OP(53), OP_MASK, COM, PPCEFS, {FRS, D, RAS}},
@@ -4865,14 +5701,36 @@
{"stfdu", OP(55), OP_MASK, COM, PPCEFS, {FRS, D, RAS}},
+{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, PPCNONE, {BO16, BI16, B8}},
+
+{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+
+{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, PPCNONE, {BI16, B8}},
+
{"lq", OP(56), OP_MASK, POWER4, PPC476, {RTQ, DQ, RAQ}},
{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
{"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
+{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
+
+{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, PPCNONE, {BI16, B8}},
+
{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}},
{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
+{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, PPCNONE, {B8}},
+{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, PPCNONE, {B8}},
{"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
{"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}},
{"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
@@ -5414,6 +6272,18 @@
{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
+
+{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
+{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
+{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
+{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
+{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
+{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
+{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
+{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
+{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
+{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
+{"e_clrlslwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
};
const int powerpc_num_macros =
Attachment:
ld.cl
Description: Text document
Index: NEWS =================================================================== RCS file: /cvs/src/src/ld/NEWS,v retrieving revision 1.119 diff -u -r1.119 NEWS --- NEWS 11 Jul 2011 15:03:09 -0000 1.119 +++ NEWS 12 Aug 2011 17:34:50 -0000 @@ -1,5 +1,7 @@ -*- text -*- +* Add support for the VLE extension to the PowerPC architecture. + * INPUT_SECTION_FLAGS has been added to the linker script language to allow selection of input sections by section header section flags. Index: testsuite/ld-powerpc/apuinfo.rd =================================================================== RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/apuinfo.rd,v retrieving revision 1.4 diff -u -r1.4 apuinfo.rd --- testsuite/ld-powerpc/apuinfo.rd 8 Feb 2010 07:09:39 -0000 1.4 +++ testsuite/ld-powerpc/apuinfo.rd 12 Aug 2011 17:34:51 -0000 @@ -6,6 +6,7 @@ #target: powerpc-eabi* Hex dump of section '.PPC.EMB.apuinfo': - 0x00000000 00000008 0000001c 00000002 41505569 ............APUi + 0x00000000 00000008 00000020 00000002 41505569 ....... ....APUi 0x00000010 6e666f00 00420001 00430001 00410001 nfo..B...C...A.. - 0x00000020 01020001 01010001 00400001 01000001 .........@...... + 0x00000020 01020001 01010001 00400001 01040001 .........@...... + 0x00000030 01000001 ....$ Index: testsuite/ld-powerpc/vle-reloc-1.d =================================================================== RCS file: testsuite/ld-powerpc/vle-reloc-1.d diff -N testsuite/ld-powerpc/vle-reloc-1.d --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ testsuite/ld-powerpc/vle-reloc-1.d 12 Aug 2011 17:34:51 -0000 @@ -0,0 +1,29 @@ +.*: file format .* + + +Disassembly of section .text_vle: + +01800074 <sub1>: + 1800074: 00 04 se_blr + +01800076 <sub2>: + 1800076: 00 04 se_blr + +01800078 <vle_reloc>: + 1800078: e8 fe se_b 1800074 <sub1> + 180007a: e9 fd se_bl 1800074 <sub1> + 180007c: e1 fd se_ble 1800076 <sub2> + 180007e: e6 fc se_beq 1800076 <sub2> + 1800080: 78 00 00 10 e_b 1800090 <sub3> + 1800084: 78 00 00 0f e_bl 1800092 <sub4> + 1800088: 7a 05 00 0c e_ble cr1,1800094 <sub5> + 180008c: 7a 1a 00 09 e_beql cr2,1800094 <sub5> + +01800090 <sub3>: + 1800090: 00 04 se_blr + +01800092 <sub4>: + 1800092: 00 04 se_blr + +01800094 <sub5>: + 1800094: 00 04 se_blr Index: testsuite/ld-powerpc/vle-reloc-1.s =================================================================== RCS file: testsuite/ld-powerpc/vle-reloc-1.s diff -N testsuite/ld-powerpc/vle-reloc-1.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ testsuite/ld-powerpc/vle-reloc-1.s 12 Aug 2011 17:34:51 -0000 @@ -0,0 +1,18 @@ + .section .text_vle +sub1: + se_blr + +sub2: + se_blr + + .section .text_vle +vle_reloc: + se_b sub1 + se_bl sub1 + se_bc 0,1,sub2 + se_bc 1,2,sub2 + + e_b sub3 + e_bl sub4 + e_bc 0,5,sub5 + e_bcl 1,10,sub5 Index: testsuite/ld-powerpc/vle-reloc-2.d =================================================================== RCS file: testsuite/ld-powerpc/vle-reloc-2.d diff -N testsuite/ld-powerpc/vle-reloc-2.d --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ testsuite/ld-powerpc/vle-reloc-2.d 12 Aug 2011 17:34:51 -0000 @@ -0,0 +1,87 @@ +.*: file format .* + +Disassembly of section .text_vle: + +01800098 <sub1>: + 1800098: 00 04 se_blr +0180009a <sub2>: + 180009a: 00 04 se_blr +0180009c <vle_reloc_2>: + 180009c: 70 20 c1 c2 e_or2i r1,450 + 18000a0: 70 40 c1 81 e_or2i r2,385 + 18000a4: 70 60 c1 81 e_or2i r3,385 + 18000a8: 70 80 c1 ce e_or2i r4,462 + 18000ac: 70 a0 c1 80 e_or2i r5,384 + 18000b0: 70 40 c1 81 e_or2i r2,385 + 18000b4: 70 20 c9 c2 e_and2i. r1,450 + 18000b8: 70 40 c9 81 e_and2i. r2,385 + 18000bc: 70 60 c9 81 e_and2i. r3,385 + 18000c0: 70 80 c9 ce e_and2i. r4,462 + 18000c4: 70 a0 c9 80 e_and2i. r5,384 + 18000c8: 70 40 c9 81 e_and2i. r2,385 + 18000cc: 70 20 d1 c2 e_or2is r1,450 + 18000d0: 70 40 d1 81 e_or2is r2,385 + 18000d4: 70 60 d1 81 e_or2is r3,385 + 18000d8: 70 80 d1 ce e_or2is r4,462 + 18000dc: 70 a0 d1 80 e_or2is r5,384 + 18000e0: 70 40 d1 81 e_or2is r2,385 + 18000e4: 70 20 e1 c2 e_lis r1,450 + 18000e8: 70 40 e1 81 e_lis r2,385 + 18000ec: 70 60 e1 81 e_lis r3,385 + 18000f0: 70 80 e1 ce e_lis r4,462 + 18000f4: 70 a0 e1 80 e_lis r5,384 + 18000f8: 70 40 e1 81 e_lis r2,385 + 18000fc: 70 20 e9 c2 e_and2is. r1,450 + 1800100: 70 40 e9 81 e_and2is. r2,385 + 1800104: 70 60 e9 81 e_and2is. r3,385 + 1800108: 70 80 e9 ce e_and2is. r4,462 + 180010c: 70 a0 e9 80 e_and2is. r5,384 + 1800110: 70 40 e9 81 e_and2is. r2,385 + 1800114: 70 01 99 c2 e_cmp16i r1,450 + 1800118: 70 02 99 81 e_cmp16i r2,385 + 180011c: 70 03 99 81 e_cmp16i r3,385 + 1800120: 70 04 99 ce e_cmp16i r4,462 + 1800124: 70 05 99 80 e_cmp16i r5,384 + 1800128: 70 02 99 81 e_cmp16i r2,385 + 180012c: 70 01 a9 c2 e_cmpl16i r1,450 + 1800130: 70 02 a9 81 e_cmpl16i r2,385 + 1800134: 70 03 a9 81 e_cmpl16i r3,385 + 1800138: 70 04 a9 ce e_cmpl16i r4,462 + 180013c: 70 05 a9 80 e_cmpl16i r5,384 + 1800140: 70 02 a9 81 e_cmpl16i r2,385 + 1800144: 70 01 b1 c2 e_cmph16i r1,450 + 1800148: 70 02 b1 81 e_cmph16i r2,385 + 180014c: 70 03 b1 81 e_cmph16i r3,385 + 1800150: 70 04 b1 ce e_cmph16i r4,462 + 1800154: 70 05 b1 80 e_cmph16i r5,384 + 1800158: 70 02 b1 81 e_cmph16i r2,385 + 180015c: 70 01 b9 c2 e_cmphl16i r1,450 + 1800160: 70 02 b9 81 e_cmphl16i r2,385 + 1800164: 70 03 b9 81 e_cmphl16i r3,385 + 1800168: 70 04 b9 ce e_cmphl16i r4,462 + 180016c: 70 05 b9 80 e_cmphl16i r5,384 + 1800170: 70 02 b9 81 e_cmphl16i r2,385 + 1800174: 70 01 89 c2 e_add2i. r1,450 + 1800178: 70 02 89 81 e_add2i. r2,385 + 180017c: 70 03 89 81 e_add2i. r3,385 + 1800180: 70 04 89 ce e_add2i. r4,462 + 1800184: 70 05 89 80 e_add2i. r5,384 + 1800188: 70 02 89 81 e_add2i. r2,385 + 180018c: 70 01 91 c2 e_add2is r1,450 + 1800190: 70 02 91 81 e_add2is r2,385 + 1800194: 70 03 91 81 e_add2is r3,385 + 1800198: 70 04 91 ce e_add2is r4,462 + 180019c: 70 05 91 80 e_add2is r5,384 + 18001a0: 70 02 91 81 e_add2is r2,385 + 18001a4: 70 01 a1 c2 e_mull2i r1,450 + 18001a8: 70 02 a1 81 e_mull2i r2,385 + 18001ac: 70 03 a1 81 e_mull2i r3,385 + 18001b0: 70 04 a1 ce e_mull2i r4,462 + 18001b4: 70 05 a1 80 e_mull2i r5,384 + 18001b8: 70 02 a1 81 e_mull2i r2,385 +018001bc <sub3>: + 18001bc: 00 04 se_blr +018001be <sub4>: + 18001be: 00 04 se_blr +018001c0 <sub5>: + 18001c0: 00 04 se_blr Index: testsuite/ld-powerpc/vle-reloc-2.s =================================================================== RCS file: testsuite/ld-powerpc/vle-reloc-2.s diff -N testsuite/ld-powerpc/vle-reloc-2.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ testsuite/ld-powerpc/vle-reloc-2.s 12 Aug 2011 17:34:51 -0000 @@ -0,0 +1,92 @@ + .section .text_vle +sub1: + se_blr + +sub2: + se_blr + + .section .text_vle +vle_reloc_2: + e_or2i 1, low@l + e_or2i 2, high@h + e_or2i 3, high_adjust@ha + e_or2i 4, low_sdarel@sdarel@l + e_or2i 5, high_sdarel@sdarel@h + e_or2i 2, high_adjust_sdarel@sdarel@ha + + e_and2i. 1, low@l + e_and2i. 2, high@h + e_and2i. 3, high_adjust@ha + e_and2i. 4, low_sdarel@sdarel@l + e_and2i. 5, high_sdarel@sdarel@h + e_and2i. 2, high_adjust_sdarel@sdarel@ha + + e_or2is 1, low@l + e_or2is 2, high@h + e_or2is 3, high_adjust@ha + e_or2is 4, low_sdarel@sdarel@l + e_or2is 5, high_sdarel@sdarel@h + e_or2is 2, high_adjust_sdarel@sdarel@ha + + e_lis 1, low@l + e_lis 2, high@h + e_lis 3, high_adjust@ha + e_lis 4, low_sdarel@sdarel@l + e_lis 5, high_sdarel@sdarel@h + e_lis 2, high_adjust_sdarel@sdarel@ha + + e_and2is. 1, low@l + e_and2is. 2, high@h + e_and2is. 3, high_adjust@ha + e_and2is. 4, low_sdarel@sdarel@l + e_and2is. 5, high_sdarel@sdarel@h + e_and2is. 2, high_adjust_sdarel@sdarel@ha + + e_cmp16i 1, low@l + e_cmp16i 2, high@h + e_cmp16i 3, high_adjust@ha + e_cmp16i 4, low_sdarel@sdarel@l + e_cmp16i 5, high_sdarel@sdarel@h + e_cmp16i 2, high_adjust_sdarel@sdarel@ha + + e_cmpl16i 1, low@l + e_cmpl16i 2, high@h + e_cmpl16i 3, high_adjust@ha + e_cmpl16i 4, low_sdarel@sdarel@l + e_cmpl16i 5, high_sdarel@sdarel@h + e_cmpl16i 2, high_adjust_sdarel@sdarel@ha + + e_cmph16i 1, low@l + e_cmph16i 2, high@h + e_cmph16i 3, high_adjust@ha + e_cmph16i 4, low_sdarel@sdarel@l + e_cmph16i 5, high_sdarel@sdarel@h + e_cmph16i 2, high_adjust_sdarel@sdarel@ha + + e_cmphl16i 1, low@l + e_cmphl16i 2, high@h + e_cmphl16i 3, high_adjust@ha + e_cmphl16i 4, low_sdarel@sdarel@l + e_cmphl16i 5, high_sdarel@sdarel@h + e_cmphl16i 2, high_adjust_sdarel@sdarel@ha + + e_add2i. 1, low@l + e_add2i. 2, high@h + e_add2i. 3, high_adjust@ha + e_add2i. 4, low_sdarel@sdarel@l + e_add2i. 5, high_sdarel@sdarel@h + e_add2i. 2, high_adjust_sdarel@sdarel@ha + + e_add2is 1, low@l + e_add2is 2, high@h + e_add2is 3, high_adjust@ha + e_add2is 4, low_sdarel@sdarel@l + e_add2is 5, high_sdarel@sdarel@h + e_add2is 2, high_adjust_sdarel@sdarel@ha + + e_mull2i 1, low@l + e_mull2i 2, high@h + e_mull2i 3, high_adjust@ha + e_mull2i 4, low_sdarel@sdarel@l + e_mull2i 5, high_sdarel@sdarel@h + e_mull2i 2, high_adjust_sdarel@sdarel@ha Index: testsuite/ld-powerpc/vle-reloc-3.d =================================================================== RCS file: testsuite/ld-powerpc/vle-reloc-3.d diff -N testsuite/ld-powerpc/vle-reloc-3.d --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ testsuite/ld-powerpc/vle-reloc-3.d 12 Aug 2011 17:34:51 -0000 @@ -0,0 +1,8 @@ +.*: file format .* + +Disassembly of section .text_vle: + +018000ac <sda21_test>: + 18000ac: 1c ad 80 08 e_add16i r5,r13,-32760 + 18000b0: 1c a2 80 04 e_add16i r5,r2,-32764 + 18000b4: 70 00 00 a0 e_li r0,160 Index: testsuite/ld-powerpc/vle-reloc-3.s =================================================================== RCS file: testsuite/ld-powerpc/vle-reloc-3.s diff -N testsuite/ld-powerpc/vle-reloc-3.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ testsuite/ld-powerpc/vle-reloc-3.s 12 Aug 2011 17:34:51 -0000 @@ -0,0 +1,10 @@ + .section .text_vle + .extern exdat1c + .extern exdat2b + .extern exdat1a + .globl sda21_test + +sda21_test: + e_add16i 5, 4, exdat1c@sda21 + e_add16i 5, 4, exdat2b@sda21 + e_add16i 5, 4, exdat0b@sda21 Index: testsuite/ld-powerpc/vle-reloc-def-1.s =================================================================== RCS file: testsuite/ld-powerpc/vle-reloc-def-1.s diff -N testsuite/ld-powerpc/vle-reloc-def-1.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ testsuite/ld-powerpc/vle-reloc-def-1.s 12 Aug 2011 17:34:51 -0000 @@ -0,0 +1,13 @@ + .section .text_vle + .globl sub3 +sub3: + se_blr + + .globl sub4 +sub4: + se_blr + + .globl sub5 +sub5: + se_blr + Index: testsuite/ld-powerpc/vle-reloc-def-2.s =================================================================== RCS file: testsuite/ld-powerpc/vle-reloc-def-2.s diff -N testsuite/ld-powerpc/vle-reloc-def-2.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ testsuite/ld-powerpc/vle-reloc-def-2.s 12 Aug 2011 17:34:51 -0000 @@ -0,0 +1,41 @@ + .section .text_vle + + .globl sub3 +sub3: + se_blr + + .globl sub4 +sub4: + se_blr + + .globl sub5 +sub5: + se_blr + + .section .sdata + .globl low_sdarel +low_sdarel: + .long 2 + + .globl high_adjust_sdarel +high_adjust_sdarel: + .long 0xff + + .section .sdata2 + .globl high_sdarel +high_sdarel: + .long 0xf + + + .data + .globl low +low: + .long 5 + + .globl high +high: + .long 0x10 + + .globl high_adjust +high_adjust: + .long 0xffff Index: testsuite/ld-powerpc/vle-reloc-def-3.s =================================================================== RCS file: testsuite/ld-powerpc/vle-reloc-def-3.s diff -N testsuite/ld-powerpc/vle-reloc-def-3.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ testsuite/ld-powerpc/vle-reloc-def-3.s 12 Aug 2011 17:34:51 -0000 @@ -0,0 +1,29 @@ + .section .sdata + .globl exdat1a + .globl exdat1b + .globl exdat1c +exdat1a: .long 6 +exdat1b: .long 7 +exdat1c: .long 8 + + .section .sdata2 + .globl exdat2a + .globl exdat2b + .globl exdat2c +exdat2a: .long 5 +exdat2b: .long 4 +exdat2c: .long 3 + + .section .PPC.EMB.sdata0 + .globl exdat0a + .globl exdat0b + .globl exdat0c +exdat0a: .long 1 +exdat0b: .long 2 +exdat0c: .long 3 + + .section .sbss + .globl exbss1a + .globl exbss1b +exbss1a: .int +exbss1b: .int
Attachment:
bfd.cl
Description: Text document
Index: archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.158
diff -u -r1.158 archures.c
--- archures.c 1 Aug 2011 23:04:19 -0000 1.158
+++ archures.c 12 Aug 2011 17:34:34 -0000
@@ -240,6 +240,7 @@
.#define bfd_mach_ppc_e500mc 5001
.#define bfd_mach_ppc_e500mc64 5005
.#define bfd_mach_ppc_titan 83
+.#define bfd_mach_ppc_vle 84
. bfd_arch_rs6000, {* IBM RS/6000 *}
.#define bfd_mach_rs6k 6000
.#define bfd_mach_rs6k_rs1 6001
Index: bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.547
diff -u -r1.547 bfd-in2.h
--- bfd-in2.h 9 Aug 2011 13:10:43 -0000 1.547
+++ bfd-in2.h 12 Aug 2011 17:34:34 -0000
@@ -1350,6 +1350,9 @@
when memory read flag isn't set. */
#define SEC_COFF_NOREAD 0x40000000
+ /* Indicate that the section has the VLE bit set. */
+#define SEC_PPC_VLE 0x80000000
+
/* End of section flags. */
/* Some internal packed boolean fields. */
@@ -1943,6 +1946,7 @@
#define bfd_mach_ppc_e500mc 5001
#define bfd_mach_ppc_e500mc64 5005
#define bfd_mach_ppc_titan 83
+#define bfd_mach_ppc_vle 84
bfd_arch_rs6000, /* IBM RS/6000 */
#define bfd_mach_rs6k 6000
#define bfd_mach_rs6k_rs1 6001
@@ -3050,6 +3054,23 @@
BFD_RELOC_PPC_EMB_RELST_HA,
BFD_RELOC_PPC_EMB_BIT_FLD,
BFD_RELOC_PPC_EMB_RELSDA,
+ BFD_RELOC_PPC_VLE_REL8,
+ BFD_RELOC_PPC_VLE_REL15,
+ BFD_RELOC_PPC_VLE_REL24,
+ BFD_RELOC_PPC_VLE_LO16A,
+ BFD_RELOC_PPC_VLE_LO16D,
+ BFD_RELOC_PPC_VLE_HI16A,
+ BFD_RELOC_PPC_VLE_HI16D,
+ BFD_RELOC_PPC_VLE_HA16A,
+ BFD_RELOC_PPC_VLE_HA16D,
+ BFD_RELOC_PPC_VLE_SDA21,
+ BFD_RELOC_PPC_VLE_SDA21_LO,
+ BFD_RELOC_PPC_VLE_SDAREL_LO16A,
+ BFD_RELOC_PPC_VLE_SDAREL_LO16D,
+ BFD_RELOC_PPC_VLE_SDAREL_HI16A,
+ BFD_RELOC_PPC_VLE_SDAREL_HI16D,
+ BFD_RELOC_PPC_VLE_SDAREL_HA16A,
+ BFD_RELOC_PPC_VLE_SDAREL_HA16D,
BFD_RELOC_PPC64_HIGHER,
BFD_RELOC_PPC64_HIGHER_S,
BFD_RELOC_PPC64_HIGHEST,
Index: cpu-powerpc.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-powerpc.c,v
retrieving revision 1.24
diff -u -r1.24 cpu-powerpc.c
--- cpu-powerpc.c 8 Feb 2010 01:59:34 -0000 1.24
+++ cpu-powerpc.c 12 Aug 2011 17:34:34 -0000
@@ -352,6 +352,20 @@
FALSE, /* not the default */
powerpc_compatible,
bfd_default_scan,
+ &bfd_powerpc_archs[19]
+ },
+ {
+ 16, /* 16 or 32 bits in a word */
+ 32, /* 32 bits in an address */
+ 8, /* 8 bits in a byte */
+ bfd_arch_powerpc,
+ bfd_mach_ppc_vle,
+ "powerpc",
+ "powerpc:vle",
+ 3,
+ FALSE, /* not the default */
+ powerpc_compatible,
+ bfd_default_scan,
0
}
};
Index: elf32-ppc.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-ppc.c,v
retrieving revision 1.300
diff -u -r1.300 elf32-ppc.c
--- elf32-ppc.c 5 Aug 2011 02:24:08 -0000 1.300
+++ elf32-ppc.c 12 Aug 2011 17:34:34 -0000
@@ -38,13 +38,25 @@
#include "elf-vxworks.h"
#include "dwarf2.h"
+typedef enum split16_format_type
+{
+ split16a_type = 0,
+ split16d_type
+}
+split16_format_type;
+
/* RELA relocations are used here. */
static bfd_reloc_status_type ppc_elf_addr16_ha_reloc
(bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
+static bfd_reloc_status_type ppc_elf_vle_addr16_split16a
+ (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
+static bfd_reloc_status_type ppc_elf_vle_addr16_split16d
+ (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
static bfd_reloc_status_type ppc_elf_unhandled_reloc
(bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
-
+static void ppc_elf_vle_split16
+ (bfd *, bfd_byte *, bfd_vma, bfd_vma, split16_format_type);
/* Branch prediction bit for branch taken relocs. */
#define BRANCH_PREDICT_BIT 0x200000
/* Mask to set RA in memory instructions. */
@@ -1392,6 +1404,262 @@
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
+ /* A relative 8 bit branch. */
+ HOWTO (R_PPC_VLE_REL8, /* type */
+ 1, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 8, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_REL8", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* A relative 15 bit branch. */
+ HOWTO (R_PPC_VLE_REL15, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 15, /* bitsize */
+ TRUE, /* pc_relative */
+ 1, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_REL15", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xfe, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* A relative 24 bit branch. */
+ HOWTO (R_PPC_VLE_REL24, /* type */
+ 1, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 24, /* bitsize */
+ TRUE, /* pc_relative */
+ 1, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_REL24", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1fffffe, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* The 16 LSBS in split16a format. */
+ HOWTO (R_PPC_VLE_LO16A, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */ /* FIXME: Does this apply to split relocs? */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16a, /* special_function */
+ "R_PPC_VLE_LO16A", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f00fff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* The 16 LSBS in split16d format. */
+ HOWTO (R_PPC_VLE_LO16D, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16d, /* special_function */
+ "R_PPC_VLE_LO16D", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f07ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Bits 16-31 split16a format. */
+ HOWTO (R_PPC_VLE_HI16A, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16a, /* special_function */
+ "R_PPC_VLE_HI16A", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f00fff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Bits 16-31 split16d format. */
+ HOWTO (R_PPC_VLE_HI16D, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16d, /* special_function */
+ "R_PPC_VLE_HI16D", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f07ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Bits 16-31 (High Adjusted) in split16a format. */
+ HOWTO (R_PPC_VLE_HA16A, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16a, /* special_function */
+ "R_PPC_VLE_HA16A", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f00fff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Bits 16-31 (High Adjusted) in split16d format. */
+ HOWTO (R_PPC_VLE_HA16D, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16d, /* special_function */
+ "R_PPC_VLE_HA16D", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f07ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* This reloc does nothing. */
+ HOWTO (R_PPC_VLE_SDA21, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_SDA21", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* This reloc does nothing. */
+ HOWTO (R_PPC_VLE_SDA21_LO, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_SDA21_LO", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* The 16 LSBS relative to _SDA_BASE_ in split16a format. */
+ HOWTO (R_PPC_VLE_SDAREL_LO16A,/* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16a, /* special_function */
+ "R_PPC_VLE_SDAREL_LO16A", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f00fff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* The 16 LSBS relative to _SDA_BASE_ in split16d format. */
+ /* This reloc does nothing. */
+ HOWTO (R_PPC_VLE_SDAREL_LO16D, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16d, /* special_function */
+ "R_PPC_VLE_SDAREL_LO16D", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f07ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Bits 16-31 relative to _SDA_BASE_ in split16a format. */
+ HOWTO (R_PPC_VLE_SDAREL_HI16A, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16a, /* special_function */
+ "R_PPC_VLE_SDAREL_HI16A", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f00fff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Bits 16-31 relative to _SDA_BASE_ in split16d format. */
+ HOWTO (R_PPC_VLE_SDAREL_HI16D, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16d, /* special_function */
+ "R_PPC_VLE_SDAREL_HI16D", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f07ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Bits 16-31 (HA) relative to _SDA_BASE split16a format. */
+ HOWTO (R_PPC_VLE_SDAREL_HA16A, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16a, /* special_function */
+ "R_PPC_VLE_SDAREL_HA16A", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f00fff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Bits 16-31 (HA) relative to _SDA_BASE split16d format. */
+ HOWTO (R_PPC_VLE_SDAREL_HA16D, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ ppc_elf_vle_addr16_split16a, /* special_function */
+ "R_PPC_VLE_SDAREL_HA16D", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f07ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
HOWTO (R_PPC_IRELATIVE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@@ -1628,6 +1896,36 @@
case BFD_RELOC_PPC_EMB_RELST_HA: r = R_PPC_EMB_RELST_HA; break;
case BFD_RELOC_PPC_EMB_BIT_FLD: r = R_PPC_EMB_BIT_FLD; break;
case BFD_RELOC_PPC_EMB_RELSDA: r = R_PPC_EMB_RELSDA; break;
+
+ case BFD_RELOC_PPC_VLE_REL8: r = R_PPC_VLE_REL8; break;
+ case BFD_RELOC_PPC_VLE_REL15: r = R_PPC_VLE_REL15; break;
+ case BFD_RELOC_PPC_VLE_REL24: r = R_PPC_VLE_REL24; break;
+ case BFD_RELOC_PPC_VLE_LO16A: r = R_PPC_VLE_LO16A; break;
+ case BFD_RELOC_PPC_VLE_LO16D: r = R_PPC_VLE_LO16D; break;
+ case BFD_RELOC_PPC_VLE_HI16A: r = R_PPC_VLE_HI16A; break;
+ case BFD_RELOC_PPC_VLE_HI16D: r = R_PPC_VLE_HI16D; break;
+ case BFD_RELOC_PPC_VLE_HA16A: r = R_PPC_VLE_HA16A; break;
+ case BFD_RELOC_PPC_VLE_HA16D: r = R_PPC_VLE_HA16D; break;
+ case BFD_RELOC_PPC_VLE_SDA21: r = R_PPC_VLE_SDA21; break;
+ case BFD_RELOC_PPC_VLE_SDA21_LO: r = R_PPC_VLE_SDA21_LO; break;
+ case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
+ r = R_PPC_VLE_SDAREL_LO16A;
+ break;
+ case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
+ r = R_PPC_VLE_SDAREL_LO16D;
+ break;
+ case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
+ r = R_PPC_VLE_SDAREL_HI16A;
+ break;
+ case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
+ r = R_PPC_VLE_SDAREL_HI16D;
+ break;
+ case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
+ r = R_PPC_VLE_SDAREL_HA16A;
+ break;
+ case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
+ r = R_PPC_VLE_SDAREL_HA16D;
+ break;
case BFD_RELOC_16_PCREL: r = R_PPC_REL16; break;
case BFD_RELOC_LO16_PCREL: r = R_PPC_REL16_LO; break;
case BFD_RELOC_HI16_PCREL: r = R_PPC_REL16_HI; break;
@@ -1719,6 +2017,80 @@
return bfd_reloc_continue;
}
+/* Handle the R_PPC_VLE_LO16A, R_PPC_VLE_HI16A,
+ and R_PPC_VLE_HA16A relocs. */
+
+static bfd_reloc_status_type
+ppc_elf_vle_addr16_split16a (bfd *abfd ATTRIBUTE_UNUSED,
+ arelent *reloc_entry,
+ asymbol *symbol,
+ void *data ATTRIBUTE_UNUSED,
+ asection *input_section,
+ bfd *output_bfd,
+ char **error_message ATTRIBUTE_UNUSED)
+{
+ bfd_vma relocation;
+
+ if (output_bfd != NULL)
+ {
+ reloc_entry->address += input_section->output_offset;
+ return bfd_reloc_ok;
+ }
+
+ if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
+ return bfd_reloc_outofrange;
+
+ if (bfd_is_com_section (symbol->section))
+ relocation = 0;
+ else
+ relocation = symbol->value;
+
+ relocation += symbol->section->output_section->vma;
+ relocation += symbol->section->output_offset;
+ relocation += reloc_entry->addend;
+
+ reloc_entry->addend += (relocation & 0x8000) << 1;
+
+ return bfd_reloc_continue;
+}
+
+/* Handle the R_PPC_VLE_LO16A, R_PPC_VLE_HI16A,
+ and R_PPC_VLE_HA16A relocs. */
+
+static bfd_reloc_status_type
+ppc_elf_vle_addr16_split16d (bfd *abfd ATTRIBUTE_UNUSED,
+ arelent *reloc_entry,
+ asymbol *symbol,
+ void *data ATTRIBUTE_UNUSED,
+ asection *input_section,
+ bfd *output_bfd,
+ char **error_message ATTRIBUTE_UNUSED)
+{
+ bfd_vma relocation;
+
+ if (output_bfd != NULL)
+ {
+ reloc_entry->address += input_section->output_offset;
+ return bfd_reloc_ok;
+ }
+
+ if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
+ return bfd_reloc_outofrange;
+
+ if (bfd_is_com_section (symbol->section))
+ relocation = 0;
+ else
+ relocation = symbol->value;
+
+ relocation += symbol->section->output_section->vma;
+ relocation += symbol->section->output_offset;
+ relocation += reloc_entry->addend;
+
+ reloc_entry->addend += (relocation & 0x8000) << 1;
+
+ return bfd_reloc_continue;
+}
+
static bfd_reloc_status_type
ppc_elf_unhandled_reloc (bfd *abfd,
arelent *reloc_entry,
@@ -1952,6 +2324,35 @@
}
}
+static bfd_boolean
+ppc_elf_section_flags (flagword *flags, const Elf_Internal_Shdr *hdr)
+{
+ if (hdr->sh_flags & SHF_PPC_VLE)
+ *flags |= SHF_PPC_VLE;
+ return TRUE;
+}
+
+static flagword
+ppc_elf_lookup_section_flags (char *flag_name)
+{
+
+ if (!strcmp (flag_name, "SHF_PPC_VLE"))
+ return SHF_PPC_VLE;
+
+ return 0;
+}
+
+/* Add the VLE flag if required. */
+
+bfd_boolean
+ppc_elf_section_processing (bfd *abfd, Elf_Internal_Shdr *shdr)
+{
+ if (bfd_get_mach (abfd) == bfd_mach_ppc_vle)
+ shdr->sh_flags |= SHF_PPC_VLE;
+
+ return TRUE;
+}
+
/* Return address for Ith PLT stub in section PLT, for relocation REL
or (bfd_vma) -1 if it should not be included. */
@@ -3502,6 +3903,9 @@
switch (r_type)
{
+ default:
+ break;
+
case R_PPC_TLSGD:
case R_PPC_TLSLD:
/* These special tls relocs tie a call to __tls_get_addr with
@@ -3614,10 +4018,21 @@
}
break;
+ case R_PPC_VLE_SDAREL_LO16A:
+ case R_PPC_VLE_SDAREL_LO16D:
+ case R_PPC_VLE_SDAREL_HI16A:
+ case R_PPC_VLE_SDAREL_HI16D:
+ case R_PPC_VLE_SDAREL_HA16A:
+ case R_PPC_VLE_SDAREL_HA16D:
case R_PPC_SDAREL16:
if (htab->sdata[0].sym == NULL
&& !create_sdata_sym (info, &htab->sdata[0]))
return FALSE;
+
+ if (htab->sdata[1].sym == NULL
+ && !create_sdata_sym (info, &htab->sdata[1]))
+ return FALSE;
+
if (h != NULL)
{
ppc_elf_hash_entry (h)->has_sda_refs = TRUE;
@@ -3641,6 +4056,8 @@
}
break;
+ case R_PPC_VLE_SDA21_LO:
+ case R_PPC_VLE_SDA21:
case R_PPC_EMB_SDA21:
case R_PPC_EMB_RELSDA:
if (info->shared)
@@ -4238,7 +4655,24 @@
return TRUE;
}
-
+
+static void
+ppc_elf_vle_split16 (bfd *output_bfd, bfd_byte *contents,
+ bfd_vma offset, bfd_vma relocation,
+ split16_format_type split16_format)
+
+{
+ bfd_vma insn, top5, bottom11;
+
+ insn = bfd_get_32 (output_bfd, contents + offset);
+ top5 = relocation >> 11;
+ top5 = top5 << (split16_format == split16a_type ? 20 : 16);
+ bottom11 = relocation & 0x7ff;
+ insn |= top5;
+ insn |= bottom11;
+ bfd_put_32 (output_bfd, insn, contents + offset);
+}
+
/* Choose which PLT scheme to use, and set .plt flags appropriately.
Returns -1 on error, 0 for old PLT, 1 for new PLT. */
int
@@ -7586,7 +8020,9 @@
case R_PPC_UADDR32:
case R_PPC_UADDR16:
goto dodyn;
-
+ case R_PPC_VLE_REL8:
+ case R_PPC_VLE_REL15:
+ case R_PPC_VLE_REL24:
case R_PPC_REL24:
case R_PPC_REL14:
case R_PPC_REL14_BRTAKEN:
@@ -7898,7 +8334,6 @@
}
break;
- /* Relocate against _SDA_BASE_. */
case R_PPC_SDAREL16:
{
const char *name;
@@ -7960,9 +8395,53 @@
}
break;
+ case R_PPC_VLE_LO16A:
+ relocation = (relocation + addend) & 0xffff;
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ relocation, split16a_type);
+ continue;
+
+ case R_PPC_VLE_LO16D:
+ relocation = (relocation + addend) & 0xffff;
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ relocation, split16d_type);
+ continue;
+
+ case R_PPC_VLE_HI16A:
+ relocation = ((relocation + addend) >> 16) & 0xffff;
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ relocation, split16a_type);
+ continue;
+
+ case R_PPC_VLE_HI16D:
+ relocation = ((relocation + addend) >> 16) & 0xffff;
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ relocation, split16d_type);
+ continue;
+
+ case R_PPC_VLE_HA16A:
+ {
+ bfd_vma value = relocation + addend;
+ value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ value, split16a_type);
+ }
+ continue;
+
+ case R_PPC_VLE_HA16D:
+ {
+ bfd_vma value = relocation + addend;
+ value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ value, split16d_type);
+ }
+ continue;
+
/* Relocate against either _SDA_BASE_, _SDA2_BASE_, or 0. */
case R_PPC_EMB_SDA21:
+ case R_PPC_VLE_SDA21:
case R_PPC_EMB_RELSDA:
+ case R_PPC_VLE_SDA21_LO:
{
const char *name;
int reg;
@@ -8019,10 +8498,28 @@
addend -= SYM_VAL (sda);
}
- if (r_type == R_PPC_EMB_SDA21)
+ if (reg == 0
+ && (r_type == R_PPC_VLE_SDA21
+ || r_type == R_PPC_VLE_SDA21_LO))
+ {
+ /* Use the split20 format. */
+ bfd_vma insn, bits12to15, bits21to31;
+ bfd_vma value = (relocation + rel->r_offset) & 0xffff;
+ /* Propagate sign bit, if necessary. */
+ insn = (value & 0x8000) ? 0x70107800 : 0x70000000;
+ bits12to15 = value & 0x700;
+ bits21to31 = value & 0x7ff;
+ insn |= bits12to15;
+ insn |= bits21to31;
+ bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
+ continue;
+ }
+ else if (r_type == R_PPC_EMB_SDA21
+ || r_type == R_PPC_VLE_SDA21
+ || r_type == R_PPC_VLE_SDA21_LO)
{
bfd_vma insn; /* Fill in register field. */
-
+
insn = bfd_get_32 (output_bfd, contents + rel->r_offset);
insn = (insn & ~RA_REGISTER_MASK) | (reg << RA_REGISTER_SHIFT);
bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
@@ -8030,6 +8527,107 @@
}
break;
+ case R_PPC_VLE_SDAREL_LO16A:
+ case R_PPC_VLE_SDAREL_LO16D:
+ case R_PPC_VLE_SDAREL_HI16A:
+ case R_PPC_VLE_SDAREL_HI16D:
+ case R_PPC_VLE_SDAREL_HA16A:
+ case R_PPC_VLE_SDAREL_HA16D:
+ {
+ bfd_vma value;
+ const char *name;
+ int reg;
+ struct elf_link_hash_entry *sda = NULL;
+
+ if (sec == NULL || sec->output_section == NULL)
+ {
+ unresolved_reloc = TRUE;
+ break;
+ }
+
+ name = bfd_get_section_name (abfd, sec->output_section);
+ if (((CONST_STRNEQ (name, ".sdata")
+ && (name[6] == 0 || name[6] == '.'))
+ || (CONST_STRNEQ (name, ".sbss")
+ && (name[5] == 0 || name[5] == '.'))))
+ {
+ reg = 13;
+ sda = htab->sdata[0].sym;
+ }
+ else if (CONST_STRNEQ (name, ".sdata2")
+ || CONST_STRNEQ (name, ".sbss2"))
+ {
+ reg = 2;
+ sda = htab->sdata[1].sym;
+ }
+ else
+ {
+ (*_bfd_error_handler)
+ (_("%B: the target (%s) of a %s relocation is "
+ "in the wrong output section (%s)"),
+ input_bfd,
+ sym_name,
+ howto->name,
+ name);
+
+ bfd_set_error (bfd_error_bad_value);
+ ret = FALSE;
+ continue;
+ }
+
+ if (sda != NULL)
+ {
+ if (!is_static_defined (sda))
+ {
+ unresolved_reloc = TRUE;
+ break;
+ }
+ }
+
+ value = sda->root.u.def.section->output_section->vma
+ + sda->root.u.def.section->output_offset;
+
+ if (r_type == R_PPC_VLE_SDAREL_LO16A)
+ {
+ value = (value + addend) & 0xffff;
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ value, split16a_type);
+ }
+ else if (r_type == R_PPC_VLE_SDAREL_LO16D)
+ {
+ value = (value + addend) & 0xffff;
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ value, split16d_type);
+ }
+ else if (r_type == R_PPC_VLE_SDAREL_HI16A)
+ {
+ value = ((value + addend) >> 16) & 0xffff;
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ value, split16a_type);
+ }
+ else if (r_type == R_PPC_VLE_SDAREL_HI16D)
+ {
+ value = ((value + addend) >> 16) & 0xffff;
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ value, split16d_type);
+ }
+ else if (r_type == R_PPC_VLE_SDAREL_HA16A)
+ {
+ value += addend;
+ value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ value, split16a_type);
+ }
+ else if (r_type == R_PPC_VLE_SDAREL_HA16D)
+ {
+ value += addend;
+ value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+ ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+ value, split16d_type);
+ }
+ }
+ continue;
+
/* Relocate against the beginning of the section. */
case R_PPC_SECTOFF:
case R_PPC_SECTOFF_LO:
@@ -9099,6 +9697,9 @@
#define elf_backend_action_discarded ppc_elf_action_discarded
#define elf_backend_init_index_section _bfd_elf_init_1_index_section
#define elf_backend_post_process_headers _bfd_elf_set_osabi
+#define elf_backend_lookup_section_flags_hook ppc_elf_lookup_section_flags
+#define elf_backend_section_flags ppc_elf_section_flags
+#define elf_backend_section_processing ppc_elf_section_processing
#include "elf32-target.h"
Index: elf32-ppc.h
===================================================================
RCS file: /cvs/src/src/bfd/elf32-ppc.h,v
retrieving revision 1.12
diff -u -r1.12 elf32-ppc.h
--- elf32-ppc.h 21 Sep 2009 11:51:01 -0000 1.12
+++ elf32-ppc.h 12 Aug 2011 17:34:34 -0000
@@ -31,3 +31,4 @@
asection *ppc_elf_tls_setup (bfd *, struct bfd_link_info *, int);
bfd_boolean ppc_elf_tls_optimize (bfd *, struct bfd_link_info *);
void ppc_elf_set_sdata_syms (bfd *, struct bfd_link_info *);
+extern bfd_boolean ppc_elf_section_processing (bfd *, Elf_Internal_Shdr *);
Index: libbfd.h
===================================================================
RCS file: /cvs/src/src/bfd/libbfd.h,v
retrieving revision 1.258
diff -u -r1.258 libbfd.h
--- libbfd.h 5 Aug 2011 03:17:11 -0000 1.258
+++ libbfd.h 12 Aug 2011 17:34:34 -0000
@@ -1318,6 +1318,23 @@
"BFD_RELOC_PPC_EMB_RELST_HA",
"BFD_RELOC_PPC_EMB_BIT_FLD",
"BFD_RELOC_PPC_EMB_RELSDA",
+ "BFD_RELOC_PPC_VLE_REL8",
+ "BFD_RELOC_PPC_VLE_REL15",
+ "BFD_RELOC_PPC_VLE_REL24",
+ "BFD_RELOC_PPC_VLE_LO16A",
+ "BFD_RELOC_PPC_VLE_LO16D",
+ "BFD_RELOC_PPC_VLE_HI16A",
+ "BFD_RELOC_PPC_VLE_HI16D",
+ "BFD_RELOC_PPC_VLE_HA16A",
+ "BFD_RELOC_PPC_VLE_HA16D",
+ "BFD_RELOC_PPC_VLE_SDA21",
+ "BFD_RELOC_PPC_VLE_SDA21_LO",
+ "BFD_RELOC_PPC_VLE_SDAREL_LO16A",
+ "BFD_RELOC_PPC_VLE_SDAREL_LO16D",
+ "BFD_RELOC_PPC_VLE_SDAREL_HI16A",
+ "BFD_RELOC_PPC_VLE_SDAREL_HI16D",
+ "BFD_RELOC_PPC_VLE_SDAREL_HA16A",
+ "BFD_RELOC_PPC_VLE_SDAREL_HA16D",
"BFD_RELOC_PPC64_HIGHER",
"BFD_RELOC_PPC64_HIGHER_S",
"BFD_RELOC_PPC64_HIGHEST",
Index: reloc.c
===================================================================
RCS file: /cvs/src/src/bfd/reloc.c,v
retrieving revision 1.216
diff -u -r1.216 reloc.c
--- reloc.c 24 Jul 2011 14:20:06 -0000 1.216
+++ reloc.c 12 Aug 2011 17:34:34 -0000
@@ -2750,6 +2750,40 @@
ENUMX
BFD_RELOC_PPC_EMB_RELSDA
ENUMX
+ BFD_RELOC_PPC_VLE_REL8
+ENUMX
+ BFD_RELOC_PPC_VLE_REL15
+ENUMX
+ BFD_RELOC_PPC_VLE_REL24
+ENUMX
+ BFD_RELOC_PPC_VLE_LO16A
+ENUMX
+ BFD_RELOC_PPC_VLE_LO16D
+ENUMX
+ BFD_RELOC_PPC_VLE_HI16A
+ENUMX
+ BFD_RELOC_PPC_VLE_HI16D
+ENUMX
+ BFD_RELOC_PPC_VLE_HA16A
+ENUMX
+ BFD_RELOC_PPC_VLE_HA16D
+ENUMX
+ BFD_RELOC_PPC_VLE_SDA21
+ENUMX
+ BFD_RELOC_PPC_VLE_SDA21_LO
+ENUMX
+ BFD_RELOC_PPC_VLE_SDAREL_LO16A
+ENUMX
+ BFD_RELOC_PPC_VLE_SDAREL_LO16D
+ENUMX
+ BFD_RELOC_PPC_VLE_SDAREL_HI16A
+ENUMX
+ BFD_RELOC_PPC_VLE_SDAREL_HI16D
+ENUMX
+ BFD_RELOC_PPC_VLE_SDAREL_HA16A
+ENUMX
+ BFD_RELOC_PPC_VLE_SDAREL_HA16D
+ENUMX
BFD_RELOC_PPC64_HIGHER
ENUMX
BFD_RELOC_PPC64_HIGHER_S
Index: section.c
===================================================================
RCS file: /cvs/src/src/bfd/section.c,v
retrieving revision 1.111
diff -u -r1.111 section.c
--- section.c 11 Jul 2011 15:03:07 -0000 1.111
+++ section.c 12 Aug 2011 17:34:34 -0000
@@ -352,6 +352,9 @@
. when memory read flag isn't set. *}
.#define SEC_COFF_NOREAD 0x40000000
.
+. {* Indicate that the section has the VLE bit set. *}
+.#define SEC_PPC_VLE 0x80000000
+.
. {* End of section flags. *}
.
. {* Some internal packed boolean fields. *}
Attachment:
binutils.cl
Description: Text document
Index: NEWS =================================================================== RCS file: /cvs/src/src/binutils/NEWS,v retrieving revision 1.103 diff -u -r1.103 NEWS --- NEWS 26 Jul 2011 21:31:37 -0000 1.103 +++ NEWS 12 Aug 2011 17:36:00 -0000 @@ -1,5 +1,7 @@ -*- text -*- +* Add support for the VLE extension to the PowerPC architecture. + * Add support for displaying the contents of .debug.macro sections. * Add --preprocessor-arg option to windres to specify additional options
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