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Re: [PATCH MIPS][LS3A] Add Loongson3A mul/div instructions
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: Mingming Sun <mingm dot sun at gmail dot com>
- Cc: binutils <binutils at sourceware dot org>
- Date: Wed, 01 Dec 2010 21:54:07 +0000
- Subject: Re: [PATCH MIPS][LS3A] Add Loongson3A mul/div instructions
- References: <AANLkTimcJGH87J91DtuDNk1iskGFAeQ-UT4r0OKP8p-M@mail.gmail.com> <87oc96wj7m.fsf@firetop.home> <AANLkTi=y6u1fgwYufoGaTxLRkMPz54Ra3-E92R63AwhK@mail.gmail.com>
Mingming Sun <mingm.sun@gmail.com> writes:
> Index: opcodes/mips-opc.c
> ===================================================================
> RCS file: /cvs/src/src/opcodes/mips-opc.c,v
> retrieving revision 1.82
> diff -u -p -r1.82 mips-opc.c
> --- opcodes/mips-opc.c 11 Nov 2010 10:23:39 -0000 1.82
> +++ opcodes/mips-opc.c 1 Dec 2010 02:54:33 -0000
> @@ -1838,28 +1838,40 @@ const struct mips_opcode mips_builtin_op
> /* ST Microelectronics Loongson-2E and -2F. */
> {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
> {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
> +{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
> {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
> {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
[...]
I can see why you listed the read and write flags in the same order as the
operands, but please follow the existing order (RD_s|RD_t|WR_d) instead.
Consistency is more important than logic here :-) Same goes for the
other instructions.
The patch is otherwise OK as far as it goes, but I'm afraid even this
change needs a test in the gas testsuite.
Richard