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powerpc gas -mcom
- From: Alan Modra <amodra at gmail dot com>
- To: binutils at sourceware dot org
- Date: Sat, 3 Jul 2010 12:47:42 +0930
- Subject: powerpc gas -mcom
This patch fixes a few issues with powerpc-as -mcom.
include/opcode/
* ppc.h (PPC_OPCODE_COMMON): Expand comment.
opcodes/
* ppc-opc.c (PWR2COM): Define.
(PPCPWR2): Add PPC_OPCODE_COMMON.
(powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
"fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
"rac" from -mcom.
The PPCPWR2 change is obvious. If an instruction is supported by both
PowerPC and POWER it belongs in -mcom. This adds "fsqrt" and "fsqrt."
to -mcom.
Adding "subc" and variants seems fairly obvious too. They are just
newer mnemonics with changed operand order for the "subfc" insns.
Adding "fcir" and variants is a little less clear, since "fcir"
differs in detail from "fctiw". However, if the PowerPC insn belongs
in -mcom then we probably ought to have the POWER variant too.
The instructions I removed are not present in the PowerPC
architecture.
Index: include/opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.40
diff -u -p -r1.40 ppc.h
--- include/opcode/ppc.h 14 Jun 2010 14:48:04 -0000 1.40
+++ include/opcode/ppc.h 3 Jul 2010 02:11:03 -0000
@@ -89,7 +89,10 @@ extern const int powerpc_num_opcodes;
#define PPC_OPCODE_601 0x20
/* Opcode is supported in both the Power and PowerPC architectures
- (ie, compiler's -mcpu=common or assembler's -mcom). */
+ (ie, compiler's -mcpu=common or assembler's -mcom). More than just
+ the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
+ and PPC_OPCODE_POWER2, because many instructions changed mnemonics
+ between POWER and POWERPC. */
#define PPC_OPCODE_COMMON 0x40
/* Opcode is supported for any Power or PowerPC platform (this is
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.132
diff -u -p -r1.132 ppc-opc.c
--- opcodes/ppc-opc.c 1 Jul 2010 02:29:12 -0000 1.132
+++ opcodes/ppc-opc.c 3 Jul 2010 02:15:58 -0000
@@ -1923,7 +1923,8 @@ extract_dm (unsigned long insn,
#define PPCVSX PPC_OPCODE_VSX
#define POWER PPC_OPCODE_POWER
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
-#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
+#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
+#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
@@ -3468,7 +3469,7 @@ const struct powerpc_opcode powerpc_opco
{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"subc", XO(31,8,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
+{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
@@ -4406,10 +4407,10 @@ const struct powerpc_opcode powerpc_opco
{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"subco", XO(31,8,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
+{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"subco.", XO(31,8,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
+{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}},
{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
@@ -4492,9 +4493,9 @@ const struct powerpc_opcode powerpc_opco
{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
-{"mfsri", X(31,627), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+{"mfsri", X(31,627), X_MASK, M601, PPCNONE, {RT, RA, RB}},
-{"dclst", X(31,630), XRB_MASK, PWRCOM, PPCNONE, {RS, RA}},
+{"dclst", X(31,630), XRB_MASK, M601, PPCNONE, {RS, RA}},
{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
@@ -4639,7 +4640,7 @@ const struct powerpc_opcode powerpc_opco
{"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
-{"rac", X(31,818), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+{"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}},
{"erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB}},
@@ -5154,14 +5155,14 @@ const struct powerpc_opcode powerpc_opco
{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
-{"fcir", XRC(63,14,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
+{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
-{"fcir.", XRC(63,14,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
+{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
-{"fcirz", XRC(63,15,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
+{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
-{"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}},
+{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
--
Alan Modra
Australia Development Lab, IBM