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PATCH: Support AVX Programming Reference (June, 2010)
- From: "H.J. Lu" <hongjiu dot lu at intel dot com>
- To: binutils at sourceware dot org
- Date: Thu, 1 Jul 2010 15:02:16 -0700
- Subject: PATCH: Support AVX Programming Reference (June, 2010)
- Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>
Hi,
I checked in this patch to support AVX Programming Reference (June,
2010):
http://software.intel.com/en-us/avx/
H.J.
---
gas/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
and .f16c.
* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.
gas/testsuite/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/arch-10.s: Add xsaveopt.
* gas/i386/x86-64-arch-2.s: Likwise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/f16c-intel.d: New.
* gas/i386/f16c.d: Likewise.
* gas/i386/f16c.s: Likewise.
* gas/i386/fsgs-intel.d: Likewise.
* gas/i386/fsgs.d: Likewise.
* gas/i386/fsgs.s: Likewise.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/rdrnd.s: Likewise.
* gas/i386/x86-64-f16c-intel.d: Likewise.
* gas/i386/x86-64-f16c.d: Likewise.
* gas/i386/x86-64-f16c.s: Likewise.
* gas/i386/x86-64-fsgs-intel.d: Likewise.
* gas/i386/x86-64-fsgs.d: Likewise.
* gas/i386/x86-64-fsgs.s: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.
* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.
* gas/i386/x86-64-xsave-intel.d: Updated.
* gas/i386/x86-64-xsave.d: Likewise.
opcodes/
2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (PREFIX_0FAE_REG_0): New.
(PREFIX_0FAE_REG_1): Likewise.
(PREFIX_0FAE_REG_2): Likewise.
(PREFIX_0FAE_REG_3): Likewise.
(PREFIX_VEX_3813): Likewise.
(PREFIX_VEX_3A1D): Likewise.
(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
PREFIX_VEX_3A1D.
(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
* i386-opc.h (CpuXsaveopt): New.
(CpuFSGSBase):Likewise.
(CpuRdRnd): Likewise.
(CpuF16C): Likewise.
(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
cpuf16c.
* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index f5c249a..d065b90 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -663,12 +663,20 @@ static const arch_entry cpu_arch[] =
CPU_SMX_FLAGS, 0 },
{ STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
CPU_XSAVE_FLAGS, 0 },
+ { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
+ CPU_XSAVEOPT_FLAGS, 0 },
{ STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
CPU_AES_FLAGS, 0 },
{ STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
CPU_PCLMUL_FLAGS, 0 },
{ STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
CPU_PCLMUL_FLAGS, 1 },
+ { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
+ CPU_FSGSBASE_FLAGS, 0 },
+ { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
+ CPU_RDRND_FLAGS, 0 },
+ { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
+ CPU_F16C_FLAGS, 0 },
{ STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
CPU_FMA_FLAGS, 0 },
{ STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index db78591..9f4d742 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -136,8 +136,12 @@ accept various extension mnemonics. For example,
@code{vmx},
@code{smx},
@code{xsave},
+@code{xsaveopt},
@code{aes},
@code{pclmul},
+@code{fsgsbase},
+@code{rdrnd},
+@code{f16c},
@code{fma},
@code{movbe},
@code{ept},
@@ -930,9 +934,10 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{generic32} @tab @samp{generic64}
@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
-@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
-@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe}
-@item @samp{.ept} @tab @samp{.clflush}
+@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
+@item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
+@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
+@item @samp{.rdrnd} @tab @samp{.f16c}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l
index 2e7e0a5..c0e98bb 100644
--- a/gas/testsuite/gas/i386/arch-10-1.l
+++ b/gas/testsuite/gas/i386/arch-10-1.l
@@ -27,6 +27,7 @@
.*:54: Error: .*
.*:56: Error: .*
.*:58: Error: .*
+.*:60: Error: .*
GAS LISTING .*
@@ -61,34 +62,36 @@ GAS LISTING .*
[ ]*28[ ]+getsec
[ ]*29[ ]+\# Xsave
[ ]*30[ ]+xgetbv
-[ ]*31[ ]+\# AES
-[ ]*32[ ]+aesenc \(%ecx\),%xmm0
-[ ]*33[ ]+\# PCLMUL
-[ ]*34[ ]+pclmulqdq \$8,%xmm1,%xmm0
-[ ]*35[ ]+\# AES \+ AVX
-[ ]*36[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
-[ ]*37[ ]+\# PCLMUL \+ AVX
-[ ]*38[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
-[ ]*39[ ]+\# FMA
-[ ]*40[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
-[ ]*41[ ]+\# MOVBE
-[ ]*42[ ]+movbe \(%ecx\),%ebx
-[ ]*43[ ]+\# EPT
-[ ]*44[ ]+invept \(%ecx\),%ebx
-[ ]*45[ ]+\# RDTSCP
-[ ]*46[ ]+rdtscp
-[ ]*47[ ]+\# 3DNow
-[ ]*48[ ]+pmulhrw %mm4,%mm3
-[ ]*49[ ]+\# 3DNow Extensions
-[ ]*50[ ]+pswapd %mm4,%mm3
-[ ]*51[ ]+\# SSE4a
-[ ]*52[ ]+insertq %xmm2,%xmm1
-[ ]*53[ ]+\# SVME
-[ ]*54[ ]+vmload
-[ ]*55[ ]+\# ABM
-[ ]*56[ ]+lzcnt %ecx,%ebx
+[ ]*31[ ]+\# Xsaveopt
+[ ]*32[ ]+xsaveopt \(%ecx\)
+[ ]*33[ ]+\# AES
+[ ]*34[ ]+aesenc \(%ecx\),%xmm0
+[ ]*35[ ]+\# PCLMUL
+[ ]*36[ ]+pclmulqdq \$8,%xmm1,%xmm0
+[ ]*37[ ]+\# AES \+ AVX
+[ ]*38[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
+[ ]*39[ ]+\# PCLMUL \+ AVX
+[ ]*40[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
+[ ]*41[ ]+\# FMA
+[ ]*42[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
+[ ]*43[ ]+\# MOVBE
+[ ]*44[ ]+movbe \(%ecx\),%ebx
+[ ]*45[ ]+\# EPT
+[ ]*46[ ]+invept \(%ecx\),%ebx
+[ ]*47[ ]+\# RDTSCP
+[ ]*48[ ]+rdtscp
+[ ]*49[ ]+\# 3DNow
+[ ]*50[ ]+pmulhrw %mm4,%mm3
+[ ]*51[ ]+\# 3DNow Extensions
+[ ]*52[ ]+pswapd %mm4,%mm3
+[ ]*53[ ]+\# SSE4a
+[ ]*54[ ]+insertq %xmm2,%xmm1
+[ ]*55[ ]+\# SVME
+[ ]*56[ ]+vmload
GAS LISTING .*
-[ ]*57[ ]+\# PadLock
-[ ]*58[ ]+xstorerng
+[ ]*57[ ]+\# ABM
+[ ]*58[ ]+lzcnt %ecx,%ebx
+[ ]*59[ ]+\# PadLock
+[ ]*60[ ]+xstorerng
diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l
index c245a89..8076b7a 100644
--- a/gas/testsuite/gas/i386/arch-10-2.l
+++ b/gas/testsuite/gas/i386/arch-10-2.l
@@ -26,6 +26,7 @@
.*:54: Error: .*
.*:56: Error: .*
.*:58: Error: .*
+.*:60: Error: .*
GAS LISTING .*
@@ -60,34 +61,36 @@ GAS LISTING .*
[ ]*28[ ]+getsec
[ ]*29[ ]+\# Xsave
[ ]*30[ ]+xgetbv
-[ ]*31[ ]+\# AES
-[ ]*32[ ]+aesenc \(%ecx\),%xmm0
-[ ]*33[ ]+\# PCLMUL
-[ ]*34[ ]+pclmulqdq \$8,%xmm1,%xmm0
-[ ]*35[ ]+\# AES \+ AVX
-[ ]*36[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
-[ ]*37[ ]+\# PCLMUL \+ AVX
-[ ]*38[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
-[ ]*39[ ]+\# FMA
-[ ]*40[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
-[ ]*41[ ]+\# MOVBE
-[ ]*42[ ]+movbe \(%ecx\),%ebx
-[ ]*43[ ]+\# EPT
-[ ]*44[ ]+invept \(%ecx\),%ebx
-[ ]*45[ ]+\# RDTSCP
-[ ]*46[ ]+rdtscp
-[ ]*47[ ]+\# 3DNow
-[ ]*48[ ]+pmulhrw %mm4,%mm3
-[ ]*49[ ]+\# 3DNow Extensions
-[ ]*50[ ]+pswapd %mm4,%mm3
-[ ]*51[ ]+\# SSE4a
-[ ]*52[ ]+insertq %xmm2,%xmm1
-[ ]*53[ ]+\# SVME
-[ ]*54[ ]+vmload
-[ ]*55[ ]+\# ABM
-[ ]*56[ ]+lzcnt %ecx,%ebx
+[ ]*31[ ]+\# Xsaveopt
+[ ]*32[ ]+xsaveopt \(%ecx\)
+[ ]*33[ ]+\# AES
+[ ]*34[ ]+aesenc \(%ecx\),%xmm0
+[ ]*35[ ]+\# PCLMUL
+[ ]*36[ ]+pclmulqdq \$8,%xmm1,%xmm0
+[ ]*37[ ]+\# AES \+ AVX
+[ ]*38[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
+[ ]*39[ ]+\# PCLMUL \+ AVX
+[ ]*40[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
+[ ]*41[ ]+\# FMA
+[ ]*42[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
+[ ]*43[ ]+\# MOVBE
+[ ]*44[ ]+movbe \(%ecx\),%ebx
+[ ]*45[ ]+\# EPT
+[ ]*46[ ]+invept \(%ecx\),%ebx
+[ ]*47[ ]+\# RDTSCP
+[ ]*48[ ]+rdtscp
+[ ]*49[ ]+\# 3DNow
+[ ]*50[ ]+pmulhrw %mm4,%mm3
+[ ]*51[ ]+\# 3DNow Extensions
+[ ]*52[ ]+pswapd %mm4,%mm3
+[ ]*53[ ]+\# SSE4a
+[ ]*54[ ]+insertq %xmm2,%xmm1
+[ ]*55[ ]+\# SVME
+[ ]*56[ ]+vmload
GAS LISTING .*
-[ ]*57[ ]+\# PadLock
-[ ]*58[ ]+xstorerng
+[ ]*57[ ]+\# ABM
+[ ]*58[ ]+lzcnt %ecx,%ebx
+[ ]*59[ ]+\# PadLock
+[ ]*60[ ]+xstorerng
diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l
index faa9bee..c4c3d34 100644
--- a/gas/testsuite/gas/i386/arch-10-3.l
+++ b/gas/testsuite/gas/i386/arch-10-3.l
@@ -19,6 +19,7 @@
.*:54: Error: .*
.*:56: Error: .*
.*:58: Error: .*
+.*:60: Error: .*
GAS LISTING .*
@@ -56,34 +57,36 @@ GAS LISTING .*
[ ]*28[ ]+getsec
[ ]*29[ ]+\# Xsave
[ ]*30[ ]+xgetbv
-[ ]*31[ ]+\# AES
-[ ]*32[ ]+aesenc \(%ecx\),%xmm0
-[ ]*33[ ]+\# PCLMUL
-[ ]*34[ ]+pclmulqdq \$8,%xmm1,%xmm0
-[ ]*35[ ]+\# AES \+ AVX
-[ ]*36[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
-[ ]*37[ ]+\# PCLMUL \+ AVX
-[ ]*38[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
-[ ]*39[ ]+\# FMA
-[ ]*40[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
-[ ]*41[ ]+\# MOVBE
-[ ]*42[ ]+movbe \(%ecx\),%ebx
-[ ]*43[ ]+\# EPT
-[ ]*44[ ]+invept \(%ecx\),%ebx
-[ ]*45[ ]+\# RDTSCP
-[ ]*46[ ]+rdtscp
-[ ]*47[ ]+\# 3DNow
-[ ]*48[ ]+pmulhrw %mm4,%mm3
-[ ]*49[ ]+\# 3DNow Extensions
-[ ]*50[ ]+pswapd %mm4,%mm3
-[ ]*51[ ]+\# SSE4a
-[ ]*52[ ]+insertq %xmm2,%xmm1
-[ ]*53[ ]+\# SVME
+[ ]*31[ ]+\# Xsaveopt
+[ ]*32[ ]+xsaveopt \(%ecx\)
+[ ]*33[ ]+\# AES
+[ ]*34[ ]+aesenc \(%ecx\),%xmm0
+[ ]*35[ ]+\# PCLMUL
+[ ]*36[ ]+pclmulqdq \$8,%xmm1,%xmm0
+[ ]*37[ ]+\# AES \+ AVX
+[ ]*38[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
+[ ]*39[ ]+\# PCLMUL \+ AVX
+[ ]*40[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
+[ ]*41[ ]+\# FMA
+[ ]*42[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
+[ ]*43[ ]+\# MOVBE
+[ ]*44[ ]+movbe \(%ecx\),%ebx
+[ ]*45[ ]+\# EPT
+[ ]*46[ ]+invept \(%ecx\),%ebx
+[ ]*47[ ]+\# RDTSCP
+[ ]*48[ ]+rdtscp
+[ ]*49[ ]+\# 3DNow
+[ ]*50[ ]+pmulhrw %mm4,%mm3
+[ ]*51[ ]+\# 3DNow Extensions
+[ ]*52[ ]+pswapd %mm4,%mm3
+[ ]*53[ ]+\# SSE4a
GAS LISTING .*
-[ ]*54[ ]+vmload
-[ ]*55[ ]+\# ABM
-[ ]*56[ ]+lzcnt %ecx,%ebx
-[ ]*57[ ]+\# PadLock
-[ ]*58[ ]+xstorerng
+[ ]*54[ ]+insertq %xmm2,%xmm1
+[ ]*55[ ]+\# SVME
+[ ]*56[ ]+vmload
+[ ]*57[ ]+\# ABM
+[ ]*58[ ]+lzcnt %ecx,%ebx
+[ ]*59[ ]+\# PadLock
+[ ]*60[ ]+xstorerng
diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l
index 30ffda8..e09167b 100644
--- a/gas/testsuite/gas/i386/arch-10-4.l
+++ b/gas/testsuite/gas/i386/arch-10-4.l
@@ -17,6 +17,7 @@
.*:54: Error: .*
.*:56: Error: .*
.*:58: Error: .*
+.*:60: Error: .*
GAS LISTING .*
@@ -54,34 +55,36 @@ GAS LISTING .*
[ ]*28[ ]+\?\?\?\? 0F37 getsec
[ ]*29[ ]+\# Xsave
[ ]*30[ ]+xgetbv
-[ ]*31[ ]+\# AES
-[ ]*32[ ]+aesenc \(%ecx\),%xmm0
-[ ]*33[ ]+\# PCLMUL
-[ ]*34[ ]+pclmulqdq \$8,%xmm1,%xmm0
-[ ]*35[ ]+\# AES \+ AVX
-[ ]*36[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
-[ ]*37[ ]+\# PCLMUL \+ AVX
-[ ]*38[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
-[ ]*39[ ]+\# FMA
-[ ]*40[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
-[ ]*41[ ]+\# MOVBE
-[ ]*42[ ]+movbe \(%ecx\),%ebx
-[ ]*43[ ]+\# EPT
-[ ]*44[ ]+invept \(%ecx\),%ebx
-[ ]*45[ ]+\# RDTSCP
-[ ]*46[ ]+rdtscp
-[ ]*47[ ]+\# 3DNow
-[ ]*48[ ]+pmulhrw %mm4,%mm3
-[ ]*49[ ]+\# 3DNow Extensions
-[ ]*50[ ]+pswapd %mm4,%mm3
-[ ]*51[ ]+\# SSE4a
-[ ]*52[ ]+insertq %xmm2,%xmm1
-[ ]*53[ ]+\# SVME
+[ ]*31[ ]+\# Xsaveopt
+[ ]*32[ ]+xsaveopt \(%ecx\)
+[ ]*33[ ]+\# AES
+[ ]*34[ ]+aesenc \(%ecx\),%xmm0
+[ ]*35[ ]+\# PCLMUL
+[ ]*36[ ]+pclmulqdq \$8,%xmm1,%xmm0
+[ ]*37[ ]+\# AES \+ AVX
+[ ]*38[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
+[ ]*39[ ]+\# PCLMUL \+ AVX
+[ ]*40[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
+[ ]*41[ ]+\# FMA
+[ ]*42[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
+[ ]*43[ ]+\# MOVBE
+[ ]*44[ ]+movbe \(%ecx\),%ebx
+[ ]*45[ ]+\# EPT
+[ ]*46[ ]+invept \(%ecx\),%ebx
+[ ]*47[ ]+\# RDTSCP
+[ ]*48[ ]+rdtscp
+[ ]*49[ ]+\# 3DNow
+[ ]*50[ ]+pmulhrw %mm4,%mm3
+[ ]*51[ ]+\# 3DNow Extensions
+[ ]*52[ ]+pswapd %mm4,%mm3
+[ ]*53[ ]+\# SSE4a
GAS LISTING .*
-[ ]*54[ ]+vmload
-[ ]*55[ ]+\# ABM
-[ ]*56[ ]+lzcnt %ecx,%ebx
-[ ]*57[ ]+\# PadLock
-[ ]*58[ ]+xstorerng
+[ ]*54[ ]+insertq %xmm2,%xmm1
+[ ]*55[ ]+\# SVME
+[ ]*56[ ]+vmload
+[ ]*57[ ]+\# ABM
+[ ]*58[ ]+lzcnt %ecx,%ebx
+[ ]*59[ ]+\# PadLock
+[ ]*60[ ]+xstorerng
diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d
index 4262b9c..1fe9f16 100644
--- a/gas/testsuite/gas/i386/arch-10.d
+++ b/gas/testsuite/gas/i386/arch-10.d
@@ -1,4 +1,4 @@
-#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
#objdump: -dw
#name: i386 arch 10
@@ -21,6 +21,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 01 c4 vmxoff
[ ]*[a-f0-9]+: 0f 37 getsec
[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
+[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%ecx\)
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%ecx\),%xmm0,%xmm2
diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s
index bee99ed..0f0218d 100644
--- a/gas/testsuite/gas/i386/arch-10.s
+++ b/gas/testsuite/gas/i386/arch-10.s
@@ -28,6 +28,8 @@ vmxoff
getsec
# Xsave
xgetbv
+# Xsaveopt
+xsaveopt (%ecx)
# AES
aesenc (%ecx),%xmm0
# PCLMUL
diff --git a/gas/testsuite/gas/i386/f16c-intel.d b/gas/testsuite/gas/i386/f16c-intel.d
new file mode 100644
index 0000000..8dd7e76
--- /dev/null
+++ b/gas/testsuite/gas/i386/f16c-intel.d
@@ -0,0 +1,31 @@
+#objdump: -dwMintel
+#name: i386 F16C (Intel disassembly)
+#source: f16c.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: c4 e2 7d 13 e4 vcvtph2ps ymm4,xmm4
+[ ]*[a-f0-9]+: c4 e2 7d 13 21 vcvtph2ps ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 79 13 f4 vcvtph2ps xmm6,xmm4
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps xmm4,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e3 7d 1d e4 02 vcvtps2ph xmm4,ymm4,0x2
+[ ]*[a-f0-9]+: c4 e3 7d 1d 21 02 vcvtps2ph XMMWORD PTR \[ecx\],ymm4,0x2
+[ ]*[a-f0-9]+: c4 e3 79 1d e4 02 vcvtps2ph xmm4,xmm4,0x2
+[ ]*[a-f0-9]+: c4 e3 79 1d 21 02 vcvtps2ph QWORD PTR \[ecx\],xmm4,0x2
+[ ]*[a-f0-9]+: c4 e2 7d 13 e4 vcvtph2ps ymm4,xmm4
+[ ]*[a-f0-9]+: c4 e2 7d 13 21 vcvtph2ps ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 7d 13 21 vcvtph2ps ymm4,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 79 13 f4 vcvtph2ps xmm6,xmm4
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps xmm4,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps xmm4,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e3 7d 1d e4 02 vcvtps2ph xmm4,ymm4,0x2
+[ ]*[a-f0-9]+: c4 e3 7d 1d 21 02 vcvtps2ph XMMWORD PTR \[ecx\],ymm4,0x2
+[ ]*[a-f0-9]+: c4 e3 7d 1d 21 02 vcvtps2ph XMMWORD PTR \[ecx\],ymm4,0x2
+[ ]*[a-f0-9]+: c4 e3 79 1d e4 02 vcvtps2ph xmm4,xmm4,0x2
+[ ]*[a-f0-9]+: c4 e3 79 1d 21 02 vcvtps2ph QWORD PTR \[ecx\],xmm4,0x2
+[ ]*[a-f0-9]+: c4 e3 79 1d 21 02 vcvtps2ph QWORD PTR \[ecx\],xmm4,0x2
+#pass
diff --git a/gas/testsuite/gas/i386/f16c.d b/gas/testsuite/gas/i386/f16c.d
new file mode 100644
index 0000000..8d772af
--- /dev/null
+++ b/gas/testsuite/gas/i386/f16c.d
@@ -0,0 +1,30 @@
+#objdump: -dw
+#name: i386 F16C
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: c4 e2 7d 13 e4 vcvtph2ps %xmm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 13 21 vcvtph2ps \(%ecx\),%ymm4
+[ ]*[a-f0-9]+: c4 e2 79 13 f4 vcvtph2ps %xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps \(%ecx\),%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 1d e4 02 vcvtps2ph \$0x2,%ymm4,%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 1d 21 02 vcvtps2ph \$0x2,%ymm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 1d e4 02 vcvtps2ph \$0x2,%xmm4,%xmm4
+[ ]*[a-f0-9]+: c4 e3 79 1d 21 02 vcvtps2ph \$0x2,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e2 7d 13 e4 vcvtph2ps %xmm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 13 21 vcvtph2ps \(%ecx\),%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 13 21 vcvtph2ps \(%ecx\),%ymm4
+[ ]*[a-f0-9]+: c4 e2 79 13 f4 vcvtph2ps %xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps \(%ecx\),%xmm4
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps \(%ecx\),%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 1d e4 02 vcvtps2ph \$0x2,%ymm4,%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 1d 21 02 vcvtps2ph \$0x2,%ymm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 7d 1d 21 02 vcvtps2ph \$0x2,%ymm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 1d e4 02 vcvtps2ph \$0x2,%xmm4,%xmm4
+[ ]*[a-f0-9]+: c4 e3 79 1d 21 02 vcvtps2ph \$0x2,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 1d 21 02 vcvtps2ph \$0x2,%xmm4,\(%ecx\)
+#pass
diff --git a/gas/testsuite/gas/i386/f16c.s b/gas/testsuite/gas/i386/f16c.s
new file mode 100644
index 0000000..803b68c
--- /dev/null
+++ b/gas/testsuite/gas/i386/f16c.s
@@ -0,0 +1,26 @@
+# Check F16C new instructions.
+
+ .text
+foo:
+ vcvtph2ps %xmm4,%ymm4
+ vcvtph2ps (%ecx),%ymm4
+ vcvtph2ps %xmm4,%xmm6
+ vcvtph2ps (%ecx),%xmm4
+ vcvtps2ph $0x2,%ymm4,%xmm4
+ vcvtps2ph $0x2,%ymm4,(%ecx)
+ vcvtps2ph $0x2,%xmm4,%xmm4
+ vcvtps2ph $0x2,%xmm4,(%ecx)
+
+ .intel_syntax noprefix
+ vcvtph2ps ymm4,xmm4
+ vcvtph2ps ymm4,XMMWORD PTR [ecx]
+ vcvtph2ps ymm4,[ecx]
+ vcvtph2ps xmm6,xmm4
+ vcvtph2ps xmm4,QWORD PTR [ecx]
+ vcvtph2ps xmm4,[ecx]
+ vcvtps2ph xmm4,ymm4,0x2
+ vcvtps2ph XMMWORD PTR [ecx],ymm4,0x2
+ vcvtps2ph [ecx],ymm4,0x2
+ vcvtps2ph xmm4,xmm4,0x2
+ vcvtps2ph QWORD PTR [ecx],xmm4,0x2
+ vcvtps2ph [ecx],xmm4,0x2
diff --git a/gas/testsuite/gas/i386/fsgs-intel.d b/gas/testsuite/gas/i386/fsgs-intel.d
new file mode 100644
index 0000000..1cb1ee3
--- /dev/null
+++ b/gas/testsuite/gas/i386/fsgs-intel.d
@@ -0,0 +1,19 @@
+#objdump: -dwMintel
+#name: i386 FSGSBase (Intel disassembly)
+#source: fsgs.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx
+[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx
+[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx
+[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx
+[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx
+[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx
+[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx
+[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx
+#pass
diff --git a/gas/testsuite/gas/i386/fsgs.d b/gas/testsuite/gas/i386/fsgs.d
new file mode 100644
index 0000000..2347375
--- /dev/null
+++ b/gas/testsuite/gas/i386/fsgs.d
@@ -0,0 +1,18 @@
+#objdump: -dw
+#name: i386 FSGSBase
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx
+[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx
+[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx
+[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx
+[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx
+[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx
+[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx
+[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx
+#pass
diff --git a/gas/testsuite/gas/i386/fsgs.s b/gas/testsuite/gas/i386/fsgs.s
new file mode 100644
index 0000000..8ad289c
--- /dev/null
+++ b/gas/testsuite/gas/i386/fsgs.s
@@ -0,0 +1,14 @@
+# Check FSGSBase new instructions.
+
+ .text
+foo:
+ rdfsbase %ebx
+ rdgsbase %ebx
+ wrfsbase %ebx
+ wrgsbase %ebx
+
+ .intel_syntax noprefix
+ rdfsbase ebx
+ rdgsbase ebx
+ wrfsbase ebx
+ wrgsbase ebx
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index ead1447..ccda6f5 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -168,6 +168,12 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "fma4"
run_dump_test "lwp"
run_dump_test "xop"
+ run_dump_test "f16c"
+ run_dump_test "f16c-intel"
+ run_dump_test "fsgs"
+ run_dump_test "fsgs-intel"
+ run_dump_test "rdrnd"
+ run_dump_test "rdrnd-intel"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
@@ -355,6 +361,12 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-fma4"
run_dump_test "x86-64-lwp"
run_dump_test "x86-64-xop"
+ run_dump_test "x86-64-f16c"
+ run_dump_test "x86-64-f16c-intel"
+ run_dump_test "x86-64-fsgs"
+ run_dump_test "x86-64-fsgs-intel"
+ run_dump_test "x86-64-rdrnd"
+ run_dump_test "x86-64-rdrnd-intel"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/rdrnd-intel.d b/gas/testsuite/gas/i386/rdrnd-intel.d
new file mode 100644
index 0000000..80dda0b
--- /dev/null
+++ b/gas/testsuite/gas/i386/rdrnd-intel.d
@@ -0,0 +1,15 @@
+#objdump: -dwMintel
+#name: i386 RdRnd (Intel disassembly)
+#source: rdrnd.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
+#pass
diff --git a/gas/testsuite/gas/i386/rdrnd.d b/gas/testsuite/gas/i386/rdrnd.d
new file mode 100644
index 0000000..f085c26
--- /dev/null
+++ b/gas/testsuite/gas/i386/rdrnd.d
@@ -0,0 +1,14 @@
+#objdump: -dw
+#name: i386 RdRnd
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
+#pass
diff --git a/gas/testsuite/gas/i386/rdrnd.s b/gas/testsuite/gas/i386/rdrnd.s
new file mode 100644
index 0000000..b3e0e69
--- /dev/null
+++ b/gas/testsuite/gas/i386/rdrnd.s
@@ -0,0 +1,10 @@
+# Check RdRnd new instructions.
+
+ .text
+foo:
+ rdrnd %bx
+ rdrnd %ebx
+
+ .intel_syntax noprefix
+ rdrnd bx
+ rdrnd ebx
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d
index 22ecba3..9cd1306 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
#objdump: -dw
#name: x86-64 arch 2
@@ -21,6 +21,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 01 c4 vmxoff
[ ]*[a-f0-9]+: 0f 37 getsec
[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
+[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%rcx\)
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%rcx\),%xmm0,%xmm2
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s
index d051441..ddc0d40 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.s
@@ -28,6 +28,8 @@ vmxoff
getsec
# Xsave
xgetbv
+# Xsaveopt
+xsaveopt (%rcx)
# AES
aesenc (%rcx),%xmm0
# PCLMUL
diff --git a/gas/testsuite/gas/i386/x86-64-f16c-intel.d b/gas/testsuite/gas/i386/x86-64-f16c-intel.d
new file mode 100644
index 0000000..737afaf
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-f16c-intel.d
@@ -0,0 +1,31 @@
+#objdump: -drwMintel
+#name: x86-64 F16C (Intel mode)
+#source: x86-64-f16c.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: c4 e2 7d 13 e4 vcvtph2ps ymm4,xmm4
+[ ]*[a-f0-9]+: c4 42 7d 13 00 vcvtph2ps ymm8,XMMWORD PTR \[r8\]
+[ ]*[a-f0-9]+: c4 e2 79 13 f4 vcvtph2ps xmm6,xmm4
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps xmm4,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e3 7d 1d e4 02 vcvtps2ph xmm4,ymm4,0x2
+[ ]*[a-f0-9]+: c4 43 7d 1d 00 02 vcvtps2ph XMMWORD PTR \[r8\],ymm8,0x2
+[ ]*[a-f0-9]+: c4 e3 79 1d e4 02 vcvtps2ph xmm4,xmm4,0x2
+[ ]*[a-f0-9]+: c4 e3 79 1d 21 02 vcvtps2ph QWORD PTR \[rcx\],xmm4,0x2
+[ ]*[a-f0-9]+: c4 e2 7d 13 e4 vcvtph2ps ymm4,xmm4
+[ ]*[a-f0-9]+: c4 42 7d 13 00 vcvtph2ps ymm8,XMMWORD PTR \[r8\]
+[ ]*[a-f0-9]+: c4 e2 7d 13 21 vcvtph2ps ymm4,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 79 13 f4 vcvtph2ps xmm6,xmm4
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps xmm4,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps xmm4,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e3 7d 1d e4 02 vcvtps2ph xmm4,ymm4,0x2
+[ ]*[a-f0-9]+: c4 e3 7d 1d 21 02 vcvtps2ph XMMWORD PTR \[rcx\],ymm4,0x2
+[ ]*[a-f0-9]+: c4 e3 7d 1d 21 02 vcvtps2ph XMMWORD PTR \[rcx\],ymm4,0x2
+[ ]*[a-f0-9]+: c4 e3 79 1d e4 02 vcvtps2ph xmm4,xmm4,0x2
+[ ]*[a-f0-9]+: c4 43 79 1d 00 02 vcvtps2ph QWORD PTR \[r8\],xmm8,0x2
+[ ]*[a-f0-9]+: c4 e3 79 1d 21 02 vcvtps2ph QWORD PTR \[rcx\],xmm4,0x2
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-f16c.d b/gas/testsuite/gas/i386/x86-64-f16c.d
new file mode 100644
index 0000000..3f4fd69
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-f16c.d
@@ -0,0 +1,30 @@
+#objdump: -dw
+#name: x86-64 F16C
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: c4 e2 7d 13 e4 vcvtph2ps %xmm4,%ymm4
+[ ]*[a-f0-9]+: c4 42 7d 13 00 vcvtph2ps \(%r8\),%ymm8
+[ ]*[a-f0-9]+: c4 e2 79 13 f4 vcvtph2ps %xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps \(%rcx\),%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 1d e4 02 vcvtps2ph \$0x2,%ymm4,%xmm4
+[ ]*[a-f0-9]+: c4 43 7d 1d 00 02 vcvtps2ph \$0x2,%ymm8,\(%r8\)
+[ ]*[a-f0-9]+: c4 e3 79 1d e4 02 vcvtps2ph \$0x2,%xmm4,%xmm4
+[ ]*[a-f0-9]+: c4 e3 79 1d 21 02 vcvtps2ph \$0x2,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e2 7d 13 e4 vcvtph2ps %xmm4,%ymm4
+[ ]*[a-f0-9]+: c4 42 7d 13 00 vcvtph2ps \(%r8\),%ymm8
+[ ]*[a-f0-9]+: c4 e2 7d 13 21 vcvtph2ps \(%rcx\),%ymm4
+[ ]*[a-f0-9]+: c4 e2 79 13 f4 vcvtph2ps %xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps \(%rcx\),%xmm4
+[ ]*[a-f0-9]+: c4 e2 79 13 21 vcvtph2ps \(%rcx\),%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 1d e4 02 vcvtps2ph \$0x2,%ymm4,%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 1d 21 02 vcvtps2ph \$0x2,%ymm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 7d 1d 21 02 vcvtps2ph \$0x2,%ymm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 1d e4 02 vcvtps2ph \$0x2,%xmm4,%xmm4
+[ ]*[a-f0-9]+: c4 43 79 1d 00 02 vcvtps2ph \$0x2,%xmm8,\(%r8\)
+[ ]*[a-f0-9]+: c4 e3 79 1d 21 02 vcvtps2ph \$0x2,%xmm4,\(%rcx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-f16c.s b/gas/testsuite/gas/i386/x86-64-f16c.s
new file mode 100644
index 0000000..9e47e2b
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-f16c.s
@@ -0,0 +1,26 @@
+# Check 64bit F16C new instructions.
+
+ .text
+foo:
+ vcvtph2ps %xmm4,%ymm4
+ vcvtph2ps (%r8),%ymm8
+ vcvtph2ps %xmm4,%xmm6
+ vcvtph2ps (%rcx),%xmm4
+ vcvtps2ph $0x2,%ymm4,%xmm4
+ vcvtps2ph $0x2,%ymm8,(%r8)
+ vcvtps2ph $0x2,%xmm4,%xmm4
+ vcvtps2ph $0x2,%xmm4,(%rcx)
+
+ .intel_syntax noprefix
+ vcvtph2ps ymm4,xmm4
+ vcvtph2ps ymm8,XMMWORD PTR [r8]
+ vcvtph2ps ymm4,[rcx]
+ vcvtph2ps xmm6,xmm4
+ vcvtph2ps xmm4,QWORD PTR [rcx]
+ vcvtph2ps xmm4,[rcx]
+ vcvtps2ph xmm4,ymm4,0x2
+ vcvtps2ph XMMWORD PTR [rcx],ymm4,0x2
+ vcvtps2ph [rcx],ymm4,0x2
+ vcvtps2ph xmm4,xmm4,0x2
+ vcvtps2ph QWORD PTR [r8],xmm8,0x2
+ vcvtps2ph [rcx],xmm4,0x2
diff --git a/gas/testsuite/gas/i386/x86-64-fsgs-intel.d b/gas/testsuite/gas/i386/x86-64-fsgs-intel.d
new file mode 100644
index 0000000..778f83d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-fsgs-intel.d
@@ -0,0 +1,43 @@
+#objdump: -drwMintel
+#name: x86-64 FSGSBase (Intel mode)
+#source: x86-64-fsgs.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx
+[ ]*[a-f0-9]+: f3 48 0f ae c3 rdfsbase rbx
+[ ]*[a-f0-9]+: f3 41 0f ae c0 rdfsbase r8d
+[ ]*[a-f0-9]+: f3 49 0f ae c0 rdfsbase r8
+[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx
+[ ]*[a-f0-9]+: f3 48 0f ae cb rdgsbase rbx
+[ ]*[a-f0-9]+: f3 41 0f ae c8 rdgsbase r8d
+[ ]*[a-f0-9]+: f3 49 0f ae c8 rdgsbase r8
+[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx
+[ ]*[a-f0-9]+: f3 48 0f ae d3 wrfsbase rbx
+[ ]*[a-f0-9]+: f3 41 0f ae d0 wrfsbase r8d
+[ ]*[a-f0-9]+: f3 49 0f ae d0 wrfsbase r8
+[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx
+[ ]*[a-f0-9]+: f3 48 0f ae db wrgsbase rbx
+[ ]*[a-f0-9]+: f3 41 0f ae d8 wrgsbase r8d
+[ ]*[a-f0-9]+: f3 49 0f ae d8 wrgsbase r8
+[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx
+[ ]*[a-f0-9]+: f3 48 0f ae c3 rdfsbase rbx
+[ ]*[a-f0-9]+: f3 41 0f ae c0 rdfsbase r8d
+[ ]*[a-f0-9]+: f3 49 0f ae c0 rdfsbase r8
+[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx
+[ ]*[a-f0-9]+: f3 48 0f ae cb rdgsbase rbx
+[ ]*[a-f0-9]+: f3 41 0f ae c8 rdgsbase r8d
+[ ]*[a-f0-9]+: f3 49 0f ae c8 rdgsbase r8
+[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx
+[ ]*[a-f0-9]+: f3 48 0f ae d3 wrfsbase rbx
+[ ]*[a-f0-9]+: f3 41 0f ae d0 wrfsbase r8d
+[ ]*[a-f0-9]+: f3 49 0f ae d0 wrfsbase r8
+[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx
+[ ]*[a-f0-9]+: f3 48 0f ae db wrgsbase rbx
+[ ]*[a-f0-9]+: f3 41 0f ae d8 wrgsbase r8d
+[ ]*[a-f0-9]+: f3 49 0f ae d8 wrgsbase r8
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-fsgs.d b/gas/testsuite/gas/i386/x86-64-fsgs.d
new file mode 100644
index 0000000..0549a3f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-fsgs.d
@@ -0,0 +1,42 @@
+#objdump: -dw
+#name: x86-64 FSGSBase
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx
+[ ]*[a-f0-9]+: f3 48 0f ae c3 rdfsbase %rbx
+[ ]*[a-f0-9]+: f3 41 0f ae c0 rdfsbase %r8d
+[ ]*[a-f0-9]+: f3 49 0f ae c0 rdfsbase %r8
+[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx
+[ ]*[a-f0-9]+: f3 48 0f ae cb rdgsbase %rbx
+[ ]*[a-f0-9]+: f3 41 0f ae c8 rdgsbase %r8d
+[ ]*[a-f0-9]+: f3 49 0f ae c8 rdgsbase %r8
+[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx
+[ ]*[a-f0-9]+: f3 48 0f ae d3 wrfsbase %rbx
+[ ]*[a-f0-9]+: f3 41 0f ae d0 wrfsbase %r8d
+[ ]*[a-f0-9]+: f3 49 0f ae d0 wrfsbase %r8
+[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx
+[ ]*[a-f0-9]+: f3 48 0f ae db wrgsbase %rbx
+[ ]*[a-f0-9]+: f3 41 0f ae d8 wrgsbase %r8d
+[ ]*[a-f0-9]+: f3 49 0f ae d8 wrgsbase %r8
+[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx
+[ ]*[a-f0-9]+: f3 48 0f ae c3 rdfsbase %rbx
+[ ]*[a-f0-9]+: f3 41 0f ae c0 rdfsbase %r8d
+[ ]*[a-f0-9]+: f3 49 0f ae c0 rdfsbase %r8
+[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx
+[ ]*[a-f0-9]+: f3 48 0f ae cb rdgsbase %rbx
+[ ]*[a-f0-9]+: f3 41 0f ae c8 rdgsbase %r8d
+[ ]*[a-f0-9]+: f3 49 0f ae c8 rdgsbase %r8
+[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx
+[ ]*[a-f0-9]+: f3 48 0f ae d3 wrfsbase %rbx
+[ ]*[a-f0-9]+: f3 41 0f ae d0 wrfsbase %r8d
+[ ]*[a-f0-9]+: f3 49 0f ae d0 wrfsbase %r8
+[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx
+[ ]*[a-f0-9]+: f3 48 0f ae db wrgsbase %rbx
+[ ]*[a-f0-9]+: f3 41 0f ae d8 wrgsbase %r8d
+[ ]*[a-f0-9]+: f3 49 0f ae d8 wrgsbase %r8
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-fsgs.s b/gas/testsuite/gas/i386/x86-64-fsgs.s
new file mode 100644
index 0000000..8234b85
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-fsgs.s
@@ -0,0 +1,38 @@
+# Check 64bit FSGS new instructions.
+
+ .text
+foo:
+ rdfsbase %ebx
+ rdfsbase %rbx
+ rdfsbase %r8d
+ rdfsbase %r8
+ rdgsbase %ebx
+ rdgsbase %rbx
+ rdgsbase %r8d
+ rdgsbase %r8
+ wrfsbase %ebx
+ wrfsbase %rbx
+ wrfsbase %r8d
+ wrfsbase %r8
+ wrgsbase %ebx
+ wrgsbase %rbx
+ wrgsbase %r8d
+ wrgsbase %r8
+
+ .intel_syntax noprefix
+ rdfsbase ebx
+ rdfsbase rbx
+ rdfsbase r8d
+ rdfsbase r8
+ rdgsbase ebx
+ rdgsbase rbx
+ rdgsbase r8d
+ rdgsbase r8
+ wrfsbase ebx
+ wrfsbase rbx
+ wrfsbase r8d
+ wrfsbase r8
+ wrgsbase ebx
+ wrgsbase rbx
+ wrgsbase r8d
+ wrgsbase r8
diff --git a/gas/testsuite/gas/i386/x86-64-rdrnd-intel.d b/gas/testsuite/gas/i386/x86-64-rdrnd-intel.d
new file mode 100644
index 0000000..293fe36
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rdrnd-intel.d
@@ -0,0 +1,23 @@
+#objdump: -drwMintel
+#name: x86-64 RdRnd(Intel mode)
+#source: x86-64-rdrnd.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
+[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd rbx
+[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd r8w
+[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd r8d
+[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd r8
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
+[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd rbx
+[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd r8w
+[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd r8d
+[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd r8
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-rdrnd.d b/gas/testsuite/gas/i386/x86-64-rdrnd.d
new file mode 100644
index 0000000..90c0f9a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rdrnd.d
@@ -0,0 +1,22 @@
+#objdump: -dw
+#name: x86-64 RdRnd
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
+[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd %rbx
+[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd %r8w
+[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd %r8d
+[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd %r8
+[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
+[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
+[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd %rbx
+[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd %r8w
+[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd %r8d
+[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd %r8
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-rdrnd.s b/gas/testsuite/gas/i386/x86-64-rdrnd.s
new file mode 100644
index 0000000..b1b3d1c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rdrnd.s
@@ -0,0 +1,18 @@
+# Check 64bit RdRnd new instructions.
+
+ .text
+foo:
+ rdrnd %bx
+ rdrnd %ebx
+ rdrnd %rbx
+ rdrnd %r8w
+ rdrnd %r8d
+ rdrnd %r8
+
+ .intel_syntax noprefix
+ rdrnd bx
+ rdrnd ebx
+ rdrnd rbx
+ rdrnd r8w
+ rdrnd r8d
+ rdrnd r8
diff --git a/gas/testsuite/gas/i386/x86-64-xsave-intel.d b/gas/testsuite/gas/i386/x86-64-xsave-intel.d
index ae506d6..f516402 100644
--- a/gas/testsuite/gas/i386/x86-64-xsave-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-xsave-intel.d
@@ -29,6 +29,15 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 49 0f ae 2c 00 xrstor64 \[r8\+rax\*1\]
[ ]*[a-f0-9]+: 4a 0f ae 2c 00 xrstor64 \[rax\+r8\*1\]
[ ]*[a-f0-9]+: 4b 0f ae 2c 38 xrstor64 \[r8\+r15\*1\]
+[ ]*[a-f0-9]+: 0f ae 30 xsaveopt \[rax\]
+[ ]*[a-f0-9]+: 41 0f ae 30 xsaveopt \[r8\]
+[ ]*[a-f0-9]+: 41 0f ae 34 00 xsaveopt \[r8\+rax\*1\]
+[ ]*[a-f0-9]+: 42 0f ae 34 00 xsaveopt \[rax\+r8\*1\]
+[ ]*[a-f0-9]+: 43 0f ae 34 38 xsaveopt \[r8\+r15\*1\]
+[ ]*[a-f0-9]+: 48 0f ae 30 xsaveopt64 \[rax\]
+[ ]*[a-f0-9]+: 49 0f ae 30 xsaveopt64 \[r8\]
+[ ]*[a-f0-9]+: 49 0f ae 34 00 xsaveopt64 \[r8\+rax\*1\]
+[ ]*[a-f0-9]+: 4a 0f ae 34 00 xsaveopt64 \[rax\+r8\*1\]
[ ]*[a-f0-9]+: 0f ae 20 xsave \[rax\]
[ ]*[a-f0-9]+: 41 0f ae 20 xsave \[r8\]
[ ]*[a-f0-9]+: 41 0f ae 24 00 xsave \[r8\+rax\*1\]
@@ -48,4 +57,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 49 0f ae 2c 00 xrstor64 \[r8\+rax\*1\]
[ ]*[a-f0-9]+: 4a 0f ae 2c 00 xrstor64 \[rax\+r8\*1\]
[ ]*[a-f0-9]+: 4b 0f ae 2c 38 xrstor64 \[r8\+r15\*1\]
+[ ]*[a-f0-9]+: 0f ae 30 xsaveopt \[rax\]
+[ ]*[a-f0-9]+: 41 0f ae 30 xsaveopt \[r8\]
+[ ]*[a-f0-9]+: 41 0f ae 34 00 xsaveopt \[r8\+rax\*1\]
+[ ]*[a-f0-9]+: 42 0f ae 34 00 xsaveopt \[rax\+r8\*1\]
+[ ]*[a-f0-9]+: 43 0f ae 34 38 xsaveopt \[r8\+r15\*1\]
+[ ]*[a-f0-9]+: 48 0f ae 30 xsaveopt64 \[rax\]
+[ ]*[a-f0-9]+: 49 0f ae 30 xsaveopt64 \[r8\]
+[ ]*[a-f0-9]+: 49 0f ae 34 00 xsaveopt64 \[r8\+rax\*1\]
+[ ]*[a-f0-9]+: 4a 0f ae 34 00 xsaveopt64 \[rax\+r8\*1\]
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-xsave.d b/gas/testsuite/gas/i386/x86-64-xsave.d
index 05114fb..46c07d4 100644
--- a/gas/testsuite/gas/i386/x86-64-xsave.d
+++ b/gas/testsuite/gas/i386/x86-64-xsave.d
@@ -27,6 +27,15 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 49 0f ae 2c 00 xrstor64 \(%r8,%rax,1\)
[ ]*[a-f0-9]+: 4a 0f ae 2c 00 xrstor64 \(%rax,%r8,1\)
[ ]*[a-f0-9]+: 4b 0f ae 2c 38 xrstor64 \(%r8,%r15,1\)
+[ ]*[a-f0-9]+: 0f ae 30 xsaveopt \(%rax\)
+[ ]*[a-f0-9]+: 41 0f ae 30 xsaveopt \(%r8\)
+[ ]*[a-f0-9]+: 41 0f ae 34 00 xsaveopt \(%r8,%rax,1\)
+[ ]*[a-f0-9]+: 42 0f ae 34 00 xsaveopt \(%rax,%r8,1\)
+[ ]*[a-f0-9]+: 43 0f ae 34 38 xsaveopt \(%r8,%r15,1\)
+[ ]*[a-f0-9]+: 48 0f ae 30 xsaveopt64 \(%rax\)
+[ ]*[a-f0-9]+: 49 0f ae 30 xsaveopt64 \(%r8\)
+[ ]*[a-f0-9]+: 49 0f ae 34 00 xsaveopt64 \(%r8,%rax,1\)
+[ ]*[a-f0-9]+: 4a 0f ae 34 00 xsaveopt64 \(%rax,%r8,1\)
[ ]*[a-f0-9]+: 0f ae 20 xsave \(%rax\)
[ ]*[a-f0-9]+: 41 0f ae 20 xsave \(%r8\)
[ ]*[a-f0-9]+: 41 0f ae 24 00 xsave \(%r8,%rax,1\)
@@ -46,4 +55,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 49 0f ae 2c 00 xrstor64 \(%r8,%rax,1\)
[ ]*[a-f0-9]+: 4a 0f ae 2c 00 xrstor64 \(%rax,%r8,1\)
[ ]*[a-f0-9]+: 4b 0f ae 2c 38 xrstor64 \(%r8,%r15,1\)
+[ ]*[a-f0-9]+: 0f ae 30 xsaveopt \(%rax\)
+[ ]*[a-f0-9]+: 41 0f ae 30 xsaveopt \(%r8\)
+[ ]*[a-f0-9]+: 41 0f ae 34 00 xsaveopt \(%r8,%rax,1\)
+[ ]*[a-f0-9]+: 42 0f ae 34 00 xsaveopt \(%rax,%r8,1\)
+[ ]*[a-f0-9]+: 43 0f ae 34 38 xsaveopt \(%r8,%r15,1\)
+[ ]*[a-f0-9]+: 48 0f ae 30 xsaveopt64 \(%rax\)
+[ ]*[a-f0-9]+: 49 0f ae 30 xsaveopt64 \(%r8\)
+[ ]*[a-f0-9]+: 49 0f ae 34 00 xsaveopt64 \(%r8,%rax,1\)
+[ ]*[a-f0-9]+: 4a 0f ae 34 00 xsaveopt64 \(%rax,%r8,1\)
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-xsave.s b/gas/testsuite/gas/i386/x86-64-xsave.s
index b32dc6e..e3316b2 100644
--- a/gas/testsuite/gas/i386/x86-64-xsave.s
+++ b/gas/testsuite/gas/i386/x86-64-xsave.s
@@ -24,6 +24,16 @@ _start:
xrstor64 (%rax, %r8)
xrstor64 (%r8, %r15)
+ xsaveopt (%rax)
+ xsaveopt (%r8)
+ xsaveopt (%r8, %rax)
+ xsaveopt (%rax, %r8)
+ xsaveopt (%r8, %r15)
+ xsaveopt64 (%rax)
+ xsaveopt64 (%r8)
+ xsaveopt64 (%r8, %rax)
+ xsaveopt64 (%rax, %r8)
+
.intel_syntax noprefix
xsave [rax]
xsave [r8]
@@ -44,3 +54,13 @@ _start:
xrstor64 [r8+rax*1]
xrstor64 [rax+r8*1]
xrstor64 [r8+r15*1]
+
+ xsaveopt [rax]
+ xsaveopt [r8]
+ xsaveopt [r8+rax*1]
+ xsaveopt [rax+r8*1]
+ xsaveopt [r8+r15*1]
+ xsaveopt64 [rax]
+ xsaveopt64 [r8]
+ xsaveopt64 [r8+rax*1]
+ xsaveopt64 [rax+r8*1]
diff --git a/gas/testsuite/gas/i386/xsave-intel.d b/gas/testsuite/gas/i386/xsave-intel.d
index 246d0cf..fc40a67 100644
--- a/gas/testsuite/gas/i386/xsave-intel.d
+++ b/gas/testsuite/gas/i386/xsave-intel.d
@@ -10,8 +10,10 @@ Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: 0f ae 2b xrstor \[ebx\]
[ ]*[a-f0-9]+: 0f ae 23 xsave \[ebx\]
+[ ]*[a-f0-9]+: 0f ae 33 xsaveopt \[ebx\]
[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
[ ]*[a-f0-9]+: 0f 01 d1 xsetbv
[ ]*[a-f0-9]+: 0f ae 29 xrstor \[ecx\]
[ ]*[a-f0-9]+: 0f ae 21 xsave \[ecx\]
+[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \[ecx\]
#pass
diff --git a/gas/testsuite/gas/i386/xsave.d b/gas/testsuite/gas/i386/xsave.d
index 4aedff5..2abb8ad 100644
--- a/gas/testsuite/gas/i386/xsave.d
+++ b/gas/testsuite/gas/i386/xsave.d
@@ -8,8 +8,10 @@ Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: 0f ae 2b xrstor \(%ebx\)
[ ]*[a-f0-9]+: 0f ae 23 xsave \(%ebx\)
+[ ]*[a-f0-9]+: 0f ae 33 xsaveopt \(%ebx\)
[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
[ ]*[a-f0-9]+: 0f 01 d1 xsetbv
[ ]*[a-f0-9]+: 0f ae 29 xrstor \(%ecx\)
[ ]*[a-f0-9]+: 0f ae 21 xsave \(%ecx\)
+[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%ecx\)
#pass
diff --git a/gas/testsuite/gas/i386/xsave.s b/gas/testsuite/gas/i386/xsave.s
index 5ed3ca5..37c7d50 100644
--- a/gas/testsuite/gas/i386/xsave.s
+++ b/gas/testsuite/gas/i386/xsave.s
@@ -3,9 +3,11 @@
_start:
xrstor (%ebx)
xsave (%ebx)
+ xsaveopt (%ebx)
xgetbv
xsetbv
.intel_syntax noprefix
xrstor [ecx]
xsave [ecx]
+ xsaveopt [ecx]
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index ecd8cca..224540e 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -741,6 +741,10 @@ enum
PREFIX_0F7D,
PREFIX_0F7E,
PREFIX_0F7F,
+ PREFIX_0FAE_REG_0,
+ PREFIX_0FAE_REG_1,
+ PREFIX_0FAE_REG_2,
+ PREFIX_0FAE_REG_3,
PREFIX_0FB8,
PREFIX_0FBD,
PREFIX_0FC2,
@@ -936,6 +940,7 @@ enum
PREFIX_VEX_380D,
PREFIX_VEX_380E,
PREFIX_VEX_380F,
+ PREFIX_VEX_3813,
PREFIX_VEX_3817,
PREFIX_VEX_3818,
PREFIX_VEX_3819,
@@ -1026,6 +1031,7 @@ enum
PREFIX_VEX_3A17,
PREFIX_VEX_3A18,
PREFIX_VEX_3A19,
+ PREFIX_VEX_3A1D,
PREFIX_VEX_3A20,
PREFIX_VEX_3A21,
PREFIX_VEX_3A22,
@@ -3033,6 +3039,30 @@ static const struct dis386 prefix_table[][4] = {
{ "movdqa", { EXxS, XM } },
},
+ /* PREFIX_0FAE_REG_0 */
+ {
+ { Bad_Opcode },
+ { "rdfsbase", { Ev } },
+ },
+
+ /* PREFIX_0FAE_REG_1 */
+ {
+ { Bad_Opcode },
+ { "rdgsbase", { Ev } },
+ },
+
+ /* PREFIX_0FAE_REG_2 */
+ {
+ { Bad_Opcode },
+ { "wrfsbase", { Ev } },
+ },
+
+ /* PREFIX_0FAE_REG_3 */
+ {
+ { Bad_Opcode },
+ { "wrgsbase", { Ev } },
+ },
+
/* PREFIX_0FB8 */
{
{ Bad_Opcode },
@@ -4419,6 +4449,13 @@ static const struct dis386 prefix_table[][4] = {
{ VEX_W_TABLE (VEX_W_380F_P_2) },
},
+ /* PREFIX_VEX_3813 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vcvtph2ps", { XM, EXxmmq } },
+ },
+
/* PREFIX_VEX_3817 */
{
{ Bad_Opcode },
@@ -5050,6 +5087,13 @@ static const struct dis386 prefix_table[][4] = {
{ VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
},
+ /* PREFIX_VEX_3A1D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vcvtps2ph", { EXxmmq, XM, Ib } },
+ },
+
/* PREFIX_VEX_3A20 */
{
{ Bad_Opcode },
@@ -7533,7 +7577,7 @@ static const struct dis386 vex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_3813) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -7835,7 +7879,7 @@ static const struct dis386 vex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_3A1D) },
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
@@ -10355,18 +10399,22 @@ static const struct dis386 mod_table[][2] = {
{
/* MOD_0FAE_REG_0 */
{ "fxsave", { FXSAVE } },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
},
{
/* MOD_0FAE_REG_1 */
{ "fxrstor", { FXSAVE } },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
},
{
/* MOD_0FAE_REG_2 */
{ "ldmxcsr", { Md } },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
},
{
/* MOD_0FAE_REG_3 */
{ "stmxcsr", { Md } },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
},
{
/* MOD_0FAE_REG_4 */
@@ -10379,7 +10427,7 @@ static const struct dis386 mod_table[][2] = {
},
{
/* MOD_0FAE_REG_6 */
- { Bad_Opcode },
+ { "xsaveopt", { FXSAVE } },
{ RM_TABLE (RM_0FAE_REG_6) },
},
{
@@ -10402,6 +10450,7 @@ static const struct dis386 mod_table[][2] = {
{
/* MOD_0FC7_REG_6 */
{ PREFIX_TABLE (PREFIX_0FC7_REG_6) },
+ { "rdrnd", { Ev } },
},
{
/* MOD_0FC7_REG_7 */
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 5cd9205..72371ed 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -122,6 +122,8 @@ static initializer cpu_flag_init[] =
"CpuSMX" },
{ "CPU_XSAVE_FLAGS",
"CpuXsave" },
+ { "CPU_XSAVEOPT_FLAGS",
+ "CpuXsaveopt" },
{ "CPU_AES_FLAGS",
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" },
{ "CPU_PCLMUL_FLAGS",
@@ -140,6 +142,12 @@ static initializer cpu_flag_init[] =
"CpuRdtscp" },
{ "CPU_EPT_FLAGS",
"CpuEPT" },
+ { "CPU_FSGSBASE_FLAGS",
+ "CpuFSGSBase" },
+ { "CPU_RDRND_FLAGS",
+ "CpuRdRnd" },
+ { "CPU_F16C_FLAGS",
+ "CpuF16C" },
{ "CPU_3DNOW_FLAGS",
"CpuMMX|Cpu3dnow" },
{ "CPU_3DNOWA_FLAGS",
@@ -300,6 +308,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuSMX),
BITFIELD (CpuABM),
BITFIELD (CpuXsave),
+ BITFIELD (CpuXsaveopt),
BITFIELD (CpuAES),
BITFIELD (CpuPCLMUL),
BITFIELD (CpuFMA),
@@ -310,6 +319,9 @@ static bitfield cpu_flags[] =
BITFIELD (CpuMovbe),
BITFIELD (CpuEPT),
BITFIELD (CpuRdtscp),
+ BITFIELD (CpuFSGSBase),
+ BITFIELD (CpuRdRnd),
+ BITFIELD (CpuF16C),
BITFIELD (Cpu64),
BITFIELD (CpuNo64),
#ifdef CpuUnused
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index ba4edd7..0fa7e85 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -94,6 +94,8 @@ enum
CpuL1OM,
/* Xsave/xrstor New Instuctions support required */
CpuXsave,
+ /* Xsaveopt New Instuctions support required */
+ CpuXsaveopt,
/* AES support required */
CpuAES,
/* PCLMUL support required */
@@ -112,6 +114,12 @@ enum
CpuEPT,
/* RDTSCP Instuction support required */
CpuRdtscp,
+ /* FSBSBASE Instructions required */
+ CpuFSGSBase,
+ /* RDRND Instructions required */
+ CpuRdRnd,
+ /* F16C Instructions required */
+ CpuF16C,
/* 64bit support available, used by -march= in assembler. */
CpuLM,
/* 64bit support required */
@@ -168,6 +176,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx:1;
unsigned int cpul1om:1;
unsigned int cpuxsave:1;
+ unsigned int cpuxsaveopt:1;
unsigned int cpuaes:1;
unsigned int cpupclmul:1;
unsigned int cpufma:1;
@@ -177,6 +186,9 @@ typedef union i386_cpu_flags
unsigned int cpumovbe:1;
unsigned int cpuept:1;
unsigned int cpurdtscp:1;
+ unsigned int cpufsgsbase:1;
+ unsigned int cpurdrnd:1;
+ unsigned int cpuf16c:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index bcb21c4..ef48720 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1754,6 +1754,10 @@ xrstor64, 1, 0xfae, 0x5, 2, CpuXsave|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSu
xgetbv, 0, 0xf01, 0xd0, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
xsetbv, 0, 0xf01, 0xd1, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
+// xsaveopt
+xsaveopt, 1, 0xfae, 0x6, 2, CpuXsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+xsaveopt64, 1, 0xfae, 0x6, 2, CpuXsaveopt|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+
// AES instructions.
aesdec, 2, 0x66de, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
@@ -2386,6 +2390,18 @@ vpclmulhqlqdq, 3, 0x6644, 0x1, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVV
vpclmullqhqdq, 3, 0x6644, 0x10, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+// FSGSBASE, RDRND and F16C
+
+rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
+rdgsbase, 1, 0xf30fae, 0x1, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
+rdrnd, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
+wrfsbase, 1, 0xf30fae, 0x2, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
+wrgsbase, 1, 0xf30fae, 0x3, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
+vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM }
+vcvtps2ph, 3, 0x661d, None, 1, CpuF16C, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
+vcvtps2ph, 3, 0x661d, None, 1, CpuF16C, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
+
// FMA instructions
vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }