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Re: PATCH: add ppca2 target
- From: Peter Bergner <bergner at vnet dot ibm dot com>
- To: Alan Modra <amodra at bigpond dot net dot au>
- Cc: Ben Elliston <bje at au1 dot ibm dot com>, binutils at sourceware dot org
- Date: Wed, 30 Sep 2009 20:41:47 -0500
- Subject: Re: PATCH: add ppca2 target
- References: <1253510550.22791.54.camel@helios> <20090921095019.GC11790@bubble.grove.modra.org>
On Mon, 2009-09-21 at 19:20 +0930, Alan Modra wrote:
> On Mon, Sep 21, 2009 at 03:22:30PM +1000, Ben Elliston wrote:
> > include/opcode/
> > * ppc.h (PPC_OPCODE_PPCA2): New.
> >
> > opcodes/
> > * ppc-dis.c (ppc_opts): Add "ppca2" entry.
> > * ppc-opc.c (powerpc_opcodes): Add eratilx, eratsx, eratsx.,
> > eratre, wchkall, eratwe, ldawx., mdfcrx., mfdcr. mtdcrx., icswx,
> > icswx., mtdcr., dci, wclrone, wclrall, wclr, erativax, tlbsrx.,
> > ici mnemonics. Update other mnemonics where required.
> > (ERAT_T): New operand.
> > (XWC_MASK): New mask.
> > (XOPL2): New macro.
> > (PPCA2): Define.
> >
> > gas/
> > * config/tc-ppc.c (md_show_usage): Document -mpcca2.
> > * doc/c-ppc.texi (PowerPC-Opts): Document -mppca2.
> >
> > gas/testsuite/
> > * gas/ppc/a2.s: New.
> > * gas/ppc/a2.d: Likewise.
> > * gas/ppc/ppc.exp: Run the a2 dump test.
>
> OK.
While submitting the associated GCC patch upstream, David asked that we
follow the precedent from other processors (eg, 403, 405, 440, etc.) and
use the option name "a2" rather than "ppca2". This patch makes binutils
use the same name "a2" as GCC. Tested with "make check" with no testsuite
failures.
Okay for the binutils mainline and 2.20 branch?
Peter
gas/
* config/tc-ppc.c (md_show_usage): Rename "ppca2" to "a2".
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
* gas/ppc/a2.d: Rename "ppca2" to "a2".
include/opcode/
* ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
opcodes/
* ppc-dis.c (ppc_opts): Rename "ppca2" to "a2".
Use renamed mask PPC_OPCODE_A2.
* ppc-opc.c (A2): Rename from PPCA2.
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.156
diff -u -p -r1.156 tc-ppc.c
--- gas/config/tc-ppc.c 21 Sep 2009 10:29:06 -0000 1.156
+++ gas/config/tc-ppc.c 30 Sep 2009 22:42:14 -0000
@@ -1195,7 +1195,7 @@ PowerPC options:\n\
-mppc64, -m620 generate code for PowerPC 620/625/630\n\
-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
-mbooke generate code for 32-bit PowerPC BookE\n\
--mppca2 generate code for A2 architecture\n\
+-ma2 generate code for A2 architecture\n\
-mpower4 generate code for Power4 architecture\n\
-mpower5 generate code for Power5 architecture\n\
-mpower6 generate code for Power6 architecture\n\
Index: gas/doc/c-ppc.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-ppc.texi,v
retrieving revision 1.16
diff -u -p -r1.16 c-ppc.texi
--- gas/doc/c-ppc.texi 21 Sep 2009 10:29:06 -0000 1.16
+++ gas/doc/c-ppc.texi 30 Sep 2009 22:42:14 -0000
@@ -73,7 +73,7 @@ Generate code for PowerPC 64, including
@item -mbooke
Generate code for 32-bit BookE.
-@item -mppca2
+@item -ma2
Generate code for A2 architecture.
@item -me300
Index: gas/testsuite/gas/ppc/a2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/a2.d,v
retrieving revision 1.2
diff -u -p -r1.2 a2.d
--- gas/testsuite/gas/ppc/a2.d 22 Sep 2009 03:10:25 -0000 1.2
+++ gas/testsuite/gas/ppc/a2.d 30 Sep 2009 22:42:14 -0000
@@ -1,6 +1,6 @@
-#as: -mppca2
-#objdump: -dr -Mppca2
-#name: PPCA2 tests
+#as: -ma2
+#objdump: -dr -Ma2
+#name: A2 tests
.*: +file format elf(32)?(64)?-powerpc.*
Index: include/opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.35
diff -u -p -r1.35 ppc.h
--- include/opcode/ppc.h 22 Sep 2009 02:36:26 -0000 1.35
+++ include/opcode/ppc.h 30 Sep 2009 22:42:14 -0000
@@ -168,7 +168,7 @@ extern const int powerpc_num_opcodes;
#define PPC_OPCODE_VSX 0x80000000
/* Opcode is supported by A2. */
-#define PPC_OPCODE_PPCA2 0x100000000ULL
+#define PPC_OPCODE_A2 0x100000000ULL
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.41
diff -u -p -r1.41 ppc-dis.c
--- opcodes/ppc-dis.c 21 Sep 2009 10:29:07 -0000 1.41
+++ opcodes/ppc-dis.c 30 Sep 2009 22:42:15 -0000
@@ -141,9 +141,9 @@ struct ppc_mopt ppc_opts[] = {
{ "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64_BRIDGE
| PPC_OPCODE_64),
0 },
- { "ppca2", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
+ { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK
- | PPC_OPCODE_64 | PPC_OPCODE_PPCA2),
+ | PPC_OPCODE_64 | PPC_OPCODE_A2),
0 },
{ "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
0 },
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.124
diff -u -p -r1.124 ppc-opc.c
--- opcodes/ppc-opc.c 29 Sep 2009 13:19:10 -0000 1.124
+++ opcodes/ppc-opc.c 30 Sep 2009 22:42:15 -0000
@@ -1933,7 +1933,7 @@ extract_dm (unsigned long insn,
#define PPCCHLK PPC_OPCODE_CACHELCK
#define PPCRFMCI PPC_OPCODE_RFMCI
#define E500MC PPC_OPCODE_E500MC
-#define PPCA2 PPC_OPCODE_PPCA2
+#define A2 PPC_OPCODE_A2
/* The opcode table.
@@ -1957,7 +1957,7 @@ extract_dm (unsigned long insn,
constrained otherwise by disassembler operation. */
const struct powerpc_opcode powerpc_opcodes[] = {
-{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPCNONE, {0}},
+{"attn", X(0,256), X_MASK, POWER4|A2, PPCNONE, {0}},
{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
@@ -3150,15 +3150,15 @@ const struct powerpc_opcode powerpc_opco
{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
{"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
-{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2, PPCNONE, {0}},
+{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|A2, PPCNONE, {0}},
{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}},
{"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}},
-{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2, PPCNONE, {0}},
+{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|A2, PPCNONE, {0}},
{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}},
-{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+{"rfgi", XL(19,102), 0xffffffff, E500MC|A2, PPCNONE, {0}},
{"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
@@ -3474,10 +3474,10 @@ const struct powerpc_opcode powerpc_opco
{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
-{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
-{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
-{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}},
-{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}},
+{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|A2, PPCNONE, {0}},
+{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|A2, PPCNONE, {0}},
+{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|A2, PPCNONE, {RA0, RB}},
+{"tlbilx", X(31,18), X_MASK, E500MC|A2, PPCNONE, {T, RA0, RB}},
{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}},
@@ -3487,7 +3487,7 @@ const struct powerpc_opcode powerpc_opco
{"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
-{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2, PPCNONE, {CT, RA, RB}},
+{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|A2, PPCNONE, {CT, RA, RB}},
{"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
{"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
@@ -3508,11 +3508,11 @@ const struct powerpc_opcode powerpc_opco
{"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
{"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
-{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
+{"maskg", XRC(31,29,0), X_MASK, M601, A2, {RA, RS, RB}},
+{"maskg.", XRC(31,29,1), X_MASK, M601, A2, {RA, RS, RB}},
-{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
-{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
+{"ldepx", X(31,29), X_MASK, E500MC|A2, PPCNONE, {RT, RA, RB}},
+{"lwepx", X(31,31), X_MASK, E500MC|A2, PPCNONE, {RT, RA, RB}},
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
@@ -3538,7 +3538,7 @@ const struct powerpc_opcode powerpc_opco
{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
-{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
+{"eratilx", X(31,51), X_MASK, A2, PPCNONE, {ERAT_T, RA, RB}},
{"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
@@ -3555,11 +3555,11 @@ const struct powerpc_opcode powerpc_opco
{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
-{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
-{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2, PPCNONE, {WC}},
+{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|A2, PPCNONE, {0}},
+{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|A2, PPCNONE, {0}},
+{"wait", X(31,62), XWC_MASK, POWER7|E500MC|A2, PPCNONE, {WC}},
-{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
+{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|A2, PPCNONE, {RA, RB}},
{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
@@ -3598,7 +3598,7 @@ const struct powerpc_opcode powerpc_opco
{"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
-{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
+{"lbepx", X(31,95), X_MASK, E500MC|A2, PPCNONE, {RT, RA, RB}},
{"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
@@ -3624,9 +3624,9 @@ const struct powerpc_opcode powerpc_opco
{"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
{"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
+{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|A2, PPCNONE, {RA, RB}},
-{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RS}},
+{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|A2, PPCNONE, {RS}},
{"dcbtstls", X(31,134), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
@@ -3651,8 +3651,8 @@ const struct powerpc_opcode powerpc_opco
{"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}},
-{"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
-{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
+{"eratsx", XRC(31,147,0), X_MASK, A2, PPCNONE, {RT, RA0, RB}},
+{"eratsx.", XRC(31,147,1), X_MASK, A2, PPCNONE, {RT, RA0, RB}},
{"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
@@ -3667,13 +3667,13 @@ const struct powerpc_opcode powerpc_opco
{"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
+{"prtyw", X(31,154), XRB_MASK, POWER6|A2, PPCNONE, {RA, RS}},
-{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
+{"stdepx", X(31,157), X_MASK, E500MC|A2, PPCNONE, {RS, RA, RB}},
-{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
+{"stwepx", X(31,159), X_MASK, E500MC|A2, PPCNONE, {RS, RA, RB}},
-{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {E}},
+{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|A2, PPCNONE, {E}},
{"dcbtls", X(31,166), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
@@ -3684,11 +3684,11 @@ const struct powerpc_opcode powerpc_opco
{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}},
-{"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}},
+{"eratre", X(31,179), X_MASK, A2, PPCNONE, {RT, RA, WS}},
{"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}},
-{"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}},
+{"wchkall", X(31,182), X_MASK, A2, PPCNONE, {OBF}},
{"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}},
{"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
@@ -3696,7 +3696,7 @@ const struct powerpc_opcode powerpc_opco
{"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
{"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
+{"prtyd", X(31,186), XRB_MASK, POWER6|A2, PPCNONE, {RA, RS}},
{"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
@@ -3711,13 +3711,13 @@ const struct powerpc_opcode powerpc_opco
{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE, {RB}},
+{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|A2, PPCNONE, {RB}},
{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, PPCNONE, {SR, RS}},
-{"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}},
+{"eratwe", X(31,211), X_MASK, A2, PPCNONE, {RS, RA, WS}},
-{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
+{"ldawx.", XRC(31,212,1), X_MASK, A2, PPCNONE, {RT, RA0, RB}},
{"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
@@ -3729,7 +3729,7 @@ const struct powerpc_opcode powerpc_opco
{"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
+{"stbepx", X(31,223), X_MASK, E500MC|A2, PPCNONE, {RS, RA, RB}},
{"icblc", X(31,230), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
@@ -3754,8 +3754,8 @@ const struct powerpc_opcode powerpc_opco
{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
-{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE, {RB}},
+{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|A2, {CT, RA, RB}},
+{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|A2, PPCNONE, {RB}},
{"mtsrin", X(31,242), XRA_MASK, PPC32, PPCNONE, {RS, RB}},
{"mtsri", X(31,242), XRA_MASK, POWER32, PPCNONE, {RS, RB}},
@@ -3768,12 +3768,12 @@ const struct powerpc_opcode powerpc_opco
{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, PPCNONE, {RA, RS, RB}},
+{"bpermd", X(31,252), X_MASK, POWER7|A2, PPCNONE, {RA, RS, RB}},
-{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
+{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|A2, PPCNONE, {RT, RA, RB}},
-{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2, PPCNONE, {RS, RA}},
-{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}},
+{"mfdcrx", X(31,259), X_MASK, BOOKE|A2, PPCNONE, {RS, RA}},
+{"mfdcrx.", XRC(31,259,1), X_MASK, A2, PPCNONE, {RS, RA}},
{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
@@ -3786,7 +3786,7 @@ const struct powerpc_opcode powerpc_opco
{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
+{"ehpriv", X(31,270), 0xffffffff, E500MC|A2, PPCNONE, {0}},
{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPCNONE, {RB, L}},
@@ -3806,7 +3806,7 @@ const struct powerpc_opcode powerpc_opco
{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
+{"lhepx", X(31,287), X_MASK, E500MC|A2, PPCNONE, {RT, RA, RB}},
{"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}},
@@ -3822,7 +3822,7 @@ const struct powerpc_opcode powerpc_opco
{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
+{"dcbtep", XRT(31,319,0), X_MASK, E500MC|A2, PPCNONE, {RT, RA, RB}},
{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}},
@@ -3858,8 +3858,8 @@ const struct powerpc_opcode powerpc_opco
{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
-{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RT, SPR}},
-{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
+{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|A2, PPCNONE, {RT, SPR}},
+{"mfdcr.", XRC(31,323,1), X_MASK, A2, PPCNONE, {RT, SPR}},
{"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
{"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
@@ -4072,7 +4072,7 @@ const struct powerpc_opcode powerpc_opco
{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
-{"mftb", X(31,371), X_MASK, CLASSIC|PPCA2, POWER7, {RT, TBR}},
+{"mftb", X(31,371), X_MASK, CLASSIC|A2, POWER7, {RT, TBR}},
{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
@@ -4080,10 +4080,10 @@ const struct powerpc_opcode powerpc_opco
{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
-{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
+{"popcntw", X(31,378), XRB_MASK, POWER7|A2, PPCNONE, {RA, RS}},
-{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2, PPCNONE, {RA, RS}},
-{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}},
+{"mtdcrx", X(31,387), X_MASK, BOOKE|A2, PPCNONE, {RA, RS}},
+{"mtdcrx.", XRC(31,387,1), X_MASK, A2, PPCNONE, {RA, RS}},
{"dcblc", X(31,390), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
@@ -4097,15 +4097,15 @@ const struct powerpc_opcode powerpc_opco
{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
-{"icswx", XRC(31,406,0), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
-{"icswx.", XRC(31,406,1), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
+{"icswx", XRC(31,406,0), X_MASK, A2, PPCNONE, {RS, RA, RB}},
+{"icswx.", XRC(31,406,1), X_MASK, A2, PPCNONE, {RS, RA, RB}},
{"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
{"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
{"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
+{"sthepx", X(31,415), X_MASK, E500MC|A2, PPCNONE, {RS, RA, RB}},
{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}},
@@ -4161,11 +4161,11 @@ const struct powerpc_opcode powerpc_opco
{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
-{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {SPR, RS}},
-{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
+{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|A2, PPCNONE, {SPR, RS}},
+{"mtdcr.", XRC(31,451,1), X_MASK, A2, PPCNONE, {SPR, RS}},
-{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, PPCA2, {RA, RB}},
-{"dci", X(31,454), XRARB_MASK, PPCA2, PPCNONE, {CT}},
+{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, A2, {RA, RB}},
+{"dci", X(31,454), XRARB_MASK, A2, PPCNONE, {CT}},
{"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
@@ -4336,7 +4336,7 @@ const struct powerpc_opcode powerpc_opco
{"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
-{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA, RB}},
+{"dcread", X(31,486), X_MASK, PPC403|PPC440, A2, {RT, RA, RB}},
{"icbtls", X(31,486), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
@@ -4357,9 +4357,9 @@ const struct powerpc_opcode powerpc_opco
{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}},
-{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
+{"popcntd", X(31,506), XRB_MASK, POWER7|A2, PPCNONE, {RA, RS}},
-{"cmpb", X(31,508), X_MASK, POWER6|PPCA2, PPCNONE, {RA, RS, RB}},
+{"cmpb", X(31,508), X_MASK, POWER6|A2, PPCNONE, {RA, RS, RB}},
{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}},
@@ -4384,7 +4384,7 @@ const struct powerpc_opcode powerpc_opco
{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
-{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}},
+{"ldbrx", X(31,532), X_MASK, CELL|POWER7|A2, PPCNONE, {RT, RA0, RB}},
{"lswx", X(31,533), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
@@ -4438,13 +4438,13 @@ const struct powerpc_opcode powerpc_opco
{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, PPCNONE, {0}},
{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE, {LS}},
-{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2, PPCNONE, {0}},
+{"msync", X(31,598), 0xffffffff, BOOKE|A2, PPCNONE, {0}},
{"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
{"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}},
{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
-{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, PPCNONE, {FRT, RA, RB}},
+{"lfdepx", X(31,607), X_MASK, E500MC|A2, PPCNONE, {FRT, RA, RB}},
{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
@@ -4479,7 +4479,7 @@ const struct powerpc_opcode powerpc_opco
{"mfsrin", X(31,659), XRA_MASK, PPC32, PPCNONE, {RT, RB}},
-{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}},
+{"stdbrx", X(31,660), X_MASK, CELL|POWER7|A2, PPCNONE, {RS, RA0, RB}},
{"stswx", X(31,661), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
@@ -4500,9 +4500,9 @@ const struct powerpc_opcode powerpc_opco
{"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
-{"wclrone", XOPL2(31,694,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
-{"wclrall", X(31,694), XRARB_MASK, PPCA2, PPCNONE, {L}},
-{"wclr", X(31,694), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}},
+{"wclrone", XOPL2(31,694,2),XRT_MASK, A2, PPCNONE, {RA0, RB}},
+{"wclrall", X(31,694), XRARB_MASK, A2, PPCNONE, {L}},
+{"wclr", X(31,694), X_MASK, A2, PPCNONE, {L, RA0, RB}},
{"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
@@ -4541,7 +4541,7 @@ const struct powerpc_opcode powerpc_opco
{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
-{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, PPCNONE, {FRS, RA, RB}},
+{"stfdepx", X(31,735), X_MASK, E500MC|A2, PPCNONE, {FRS, RA, RB}},
{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
@@ -4565,7 +4565,7 @@ const struct powerpc_opcode powerpc_opco
{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2, PPCNONE, {RA, RB}},
+{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|A2, PPCNONE, {RA, RB}},
{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
{"stfdux", X(31,759), X_MASK, COM, PPCNONE, {FRS, RAS, RB}},
@@ -4586,7 +4586,7 @@ const struct powerpc_opcode powerpc_opco
{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2, PPCNONE, {RA, RB}},
+{"tlbivax", X(31,786), XRT_MASK, BOOKE|A2, PPCNONE, {RA, RB}},
{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
@@ -4609,7 +4609,7 @@ const struct powerpc_opcode powerpc_opco
{"rac", X(31,818), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB}},
+{"erativax", X(31,819), X_MASK, A2, PPCNONE, {RS, RA0, RB}},
{"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
@@ -4630,17 +4630,17 @@ const struct powerpc_opcode powerpc_opco
{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA, RB}},
+{"tlbsrx.", XRC(31,850,1), XRT_MASK, A2, PPCNONE, {RA, RB}},
{"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
{"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
-{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2, {0}},
-{"mbar", X(31,854), X_MASK, BOOKE|PPCA2, PPCNONE, {MO}},
-{"eieio", X(31,854), 0xffffffff, PPCA2, PPCNONE, {0}},
+{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|A2, {0}},
+{"mbar", X(31,854), X_MASK, BOOKE|A2, PPCNONE, {MO}},
+{"eieio", X(31,854), 0xffffffff, A2, PPCNONE, {0}},
-{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2, PPCNONE, {FRT, RA0, RB}},
+{"lfiwax", X(31,855), X_MASK, POWER6|A2, PPCNONE, {FRT, RA0, RB}},
{"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
{"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
@@ -4650,7 +4650,7 @@ const struct powerpc_opcode powerpc_opco
{"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
-{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}},
+{"lfiwzx", X(31,887), X_MASK, POWER7|A2, PPCNONE, {FRT, RA0, RB}},
{"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
@@ -4662,8 +4662,8 @@ const struct powerpc_opcode powerpc_opco
{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RTO, RA, RB}},
-{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RTO, RA, RB}},
+{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|A2, PPCNONE, {RTO, RA, RB}},
+{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|A2, PPCNONE, {RTO, RA, RB}},
{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
@@ -4694,9 +4694,9 @@ const struct powerpc_opcode powerpc_opco
{"divweo", XO(31,427,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
{"divweo.", XO(31,427,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}},
-{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
-{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
-{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RSO, RAOPT, SHO}},
+{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, A2, {RT, RA}},
+{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, A2, {RT, RA}},
+{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|A2, PPCNONE, {RSO, RAOPT, SHO}},
{"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
@@ -4709,7 +4709,7 @@ const struct powerpc_opcode powerpc_opco
{"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}},
{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
-{"ici", X(31,966), XRARB_MASK, PPCA2, PPCNONE, {CT}},
+{"ici", X(31,966), XRARB_MASK, A2, PPCNONE, {CT}},
{"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
@@ -4719,10 +4719,10 @@ const struct powerpc_opcode powerpc_opco
{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2, {RB}},
+{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|A2, {RB}},
{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
-{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RSO, RAOPT, SHO}},
+{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|A2, PPCNONE, {RSO, RAOPT, SHO}},
{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
@@ -4733,7 +4733,7 @@ const struct powerpc_opcode powerpc_opco
{"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
-{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
+{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|A2, PPCNONE, {RA, RB}},
{"icread", X(31,998), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
@@ -4753,7 +4753,7 @@ const struct powerpc_opcode powerpc_opco
{"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
-{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
+{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|A2, PPCNONE, {RA, RB}},
{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPCNONE, {RA, RB}},
@@ -4937,14 +4937,14 @@ const struct powerpc_opcode powerpc_opco
{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
-{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
-{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|A2, PPCNONE, {FRT, FRB}},
+{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|A2, PPCNONE, {FRT, FRB}},
{"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
-{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|A2, PPCNONE, {FRT, FRB}},
+{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|A2, PPCNONE, {FRT, FRB}},
{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
@@ -5107,8 +5107,8 @@ const struct powerpc_opcode powerpc_opco
{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
-{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2, PPCNONE, {FRT, FRA, FRB}},
-{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2, PPCNONE, {FRT, FRA, FRB}},
+{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|A2, PPCNONE, {FRT, FRA, FRB}},
+{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|A2, PPCNONE, {FRT, FRA, FRB}},
{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
@@ -5217,10 +5217,10 @@ const struct powerpc_opcode powerpc_opco
{"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2, PPCNONE, {BFF, U, W}},
-{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2, {BFF, U}},
-{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2, PPCNONE, {BFF, U, W}},
-{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2, {BFF, U}},
+{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|A2, PPCNONE, {BFF, U, W}},
+{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|A2, {BFF, U}},
+{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|A2, PPCNONE, {BFF, U, W}},
+{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|A2, {BFF, U}},
{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
@@ -5276,10 +5276,10 @@ const struct powerpc_opcode powerpc_opco
{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2, PPCNONE, {FLM, FRB, XFL_L, W}},
-{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2, {FLM, FRB}},
-{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2, PPCNONE, {FLM, FRB, XFL_L, W}},
-{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2, {FLM, FRB}},
+{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|A2, PPCNONE, {FLM, FRB, XFL_L, W}},
+{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|A2, {FLM, FRB}},
+{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|A2, PPCNONE, {FLM, FRB, XFL_L, W}},
+{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|A2, {FLM, FRB}},
{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
@@ -5302,14 +5302,14 @@ const struct powerpc_opcode powerpc_opco
{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
-{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|A2, PPCNONE, {FRT, FRB}},
+{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|A2, PPCNONE, {FRT, FRB}},
-{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
-{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|A2, PPCNONE, {FRT, FRB}},
+{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|A2, PPCNONE, {FRT, FRB}},
-{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
-{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|A2, PPCNONE, {FRT, FRB}},
+{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|A2, PPCNONE, {FRT, FRB}},
};
const int powerpc_num_opcodes =