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Re: MIPS PLT entry
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: "Fu\, Chao-Ying" <fu at mips dot com>
- Cc: "Maciej W. Rozycki" <macro at linux-mips dot org>, <binutils at sourceware dot org>
- Date: Thu, 16 Jul 2009 20:28:21 +0100
- Subject: Re: MIPS PLT entry
- References: <94BD67F8AF3ED34FA362C662BA1F12C502BB5CC0@MTVEXCHANGE.mips.com> <94BD67F8AF3ED34FA362C662BA1F12C502BB5CE5@MTVEXCHANGE.mips.com>
"Fu, Chao-Ying" <fu@mips.com> writes:
>> >
>> > ... it's trivial to implement it flexibly, so that both MIPS
>> > I support is
>> > retained and newer platforms benefit from a faster sequence,
>> > and I plan to
>> > do so unless Chao-Ying beats me, ;) so I see no point in doing it
>> > otherwise.
>>
> Hi Maciej,
>
> I didn't see your patch, so I made a patch. Do you think
> this patch does what you plan to do? Thanks a lot!
Looks good.
> @@ -8630,10 +8638,12 @@ _bfd_mips_elf_size_dynamic_sections (bfd
> s->size += mips_elf_hash_table (info)->compact_rel_size;
> else if (s == htab->splt)
> {
> - /* If the last PLT entry has a branch delay slot, allocate
> + /* For MIPS1, if the last PLT entry has a branch delay slot, allocate
> room for an extra nop to fill the delay slot. */
> - if (!htab->is_vxworks && s->size > 0)
> - s->size += 4;
> + if (((elf_elfheader (output_bfd)->e_flags & EF_MIPS_ARCH)
> + == E_MIPS_ARCH_1)
> + && !htab->is_vxworks && s->size > 0)
> + s->size += 4;
I think the elf_elfheader condition ought to be in a macro:
#define LOAD_INTERLOCKS_P(abfd) \
((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_1)
since some MIPS I targets (like the tx39) had load interlocks too.
Put it with other similar macros like PIC_OBJECT_P.
OK with that change, thanks. Are there no regressions in the ld testsuite?
Richard