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soft-icache testcase
- From: Alan Modra <amodra at bigpond dot net dot au>
- To: binutils at sourceware dot org
- Date: Tue, 13 Jan 2009 12:24:59 +1030
- Subject: soft-icache testcase
Add soft-icache testcase.
ld/testsuite/
* ld-spu/icache1.s: New file.
* ld-spu/icache1.d: New file.
Index: ld/testsuite/ld-spu/icache1.d
===================================================================
RCS file: ld/testsuite/ld-spu/icache1.d
diff -N ld/testsuite/ld-spu/icache1.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-spu/icache1.d 13 Jan 2009 01:49:09 -0000
@@ -0,0 +1,202 @@
+#source: icache1.s
+#ld: --soft-icache --num-lines=4 --auto-overlay=tmpdir/icache1.lnk --auto-relink
+#objdump: -D
+
+.* elf32-spu
+
+
+Disassembly of section .ovl.init:
+00000800 <__icache_fileoff>:
+.* 00 00 00 00.*
+.* 00 00 07 80.*
+ \.\.\.
+
+Disassembly of section \.ovly1:
+
+00000800 <\.ovly1>:
+.* ai \$1,\$1,64 # 40
+.* lqd \$0,16\(\$1\)
+.* bi \$0
+ \.\.\.
+
+Disassembly of section \.ovly2:
+
+00000c00 <f1>:
+.* 40 20 00 00 nop \$0
+.* 24 00 40 80 stqd \$0,16\(\$1\)
+.* 1c f0 00 81 ai \$1,\$1,-64
+.* 24 00 00 81 stqd \$1,0\(\$1\)
+.* 33 00 73 80 brsl \$0,fac .*
+.* 33 00 77 00 brsl \$0,fcc .*
+ \.\.\.
+.* 32 00 16 80 br fec .*
+ \.\.\.
+ fa0: 00 00 00 02.*
+ fa4: 00 00 11 04.*
+ fa8: a0 00 0c 10.*
+ fac: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ fb0: 00 00 ed 00.*
+ \.\.\.
+ fc0: 00 00 00 02.*
+ fc4: 00 00 10 00.*
+ fc8: a0 00 0c 14.*
+ fcc: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ fd0: 00 00 00 00.*
+ fd4: 00 00 0a 80.*
+ \.\.\.
+ fe4: 00 00 08 00.*
+ fe8: 20 00 0f 38.*
+ fec: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ \.\.\.
+ ff8: 00 7f 0f 80.*
+ ffc: 00 00 00 00.*
+
+Disassembly of section \.ovly3:
+
+00001000 <f3>:
+ \.\.\.
+.* 35 00 00 00 bi \$0
+
+00001104 <f2>:
+.* 1c e0 00 81 ai \$1,\$1,-128
+.* 24 00 00 81 stqd \$1,0\(\$1\)
+ \.\.\.
+.* 1c 20 00 81 ai \$1,\$1,128 # 80
+.* 35 00 00 00 bi \$0
+ \.\.\.
+
+Disassembly of section \.ovly4:
+
+00001400 <f5>:
+.* 24 00 40 80 stqd \$0,16\(\$1\)
+.* 24 f8 00 81 stqd \$1,-512\(\$1\)
+.* 1c 80 00 81 ai \$1,\$1,-512
+.* 33 7f fe 80 brsl \$0,1400 <f5> # 1400
+ \.\.\.
+.* 42 01 00 03 ila \$3,200 <__icache_linked_list\+0x1c0>
+.* 18 00 c0 81 a \$1,\$1,\$3
+.* 34 00 40 80 lqd \$0,16\(\$1\)
+.* 35 00 00 00 bi \$0
+ \.\.\.
+
+Disassembly of section \.ovly5:
+
+00000800 <\.ovly5>:
+ \.\.\.
+.* 42 01 00 03 ila \$3,200 .*
+.* 18 00 c0 81 a \$1,\$1,\$3
+.* 34 00 40 80 lqd \$0,16\(\$1\)
+.* 30 01 7d 80 bra bec .*
+ \.\.\.
+ be0: 00 00 00 03.*
+ be4: 00 00 14 00.*
+ be8: a0 00 0b 2c.*
+ bec: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ \.\.\.
+ bfc: 00 03 fd 80.*
+
+Disassembly of section \.ovly6:
+
+00000c00 <\.ovly6>:
+.* 31 01 f5 80 brasl \$0,fac .*
+.* 33 00 79 00 brsl \$0,fcc .*
+ \.\.\.
+.* 32 00 18 80 br fec .*
+ \.\.\.
+ fa0: 00 00 00 07.*
+ fa4: 00 04 14 00.*
+ fa8: a0 00 0c 00.*
+ fac: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ fb0: 00 03 75 80.*
+ \.\.\.
+ fc0: 00 00 00 07.*
+ fc4: 00 04 14 00.*
+ fc8: a0 00 0c 04.*
+ fcc: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ fd0: 00 00 00 00.*
+ fd4: 00 00 86 80.*
+ \.\.\.
+ fe0: 00 00 00 04.*
+ fe4: 00 04 08 00.*
+ fe8: 20 00 0f 28.*
+ fec: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ \.\.\.
+ ff8: 00 7f 03 80.*
+ ffc: 00 00 00 00.*
+
+Disassembly of section \.ovly7:
+
+00001000 <\.ovly7>:
+.* 41 7f ff 83 ilhu \$3,65535 # ffff
+.* 60 f8 30 03 iohl \$3,61536 # f060
+.* 18 00 c0 84 a \$4,\$1,\$3
+.* 00 20 00 00 lnop
+.* 04 00 02 01 ori \$1,\$4,0
+.* 24 00 02 04 stqd \$4,0\(\$4\)
+.* 33 00 72 80 brsl \$0,13ac .*
+.* 33 00 76 00 brsl \$0,13cc .*
+.* 34 00 00 81 lqd \$1,0\(\$1\)
+ \.\.\.
+.* 32 00 15 00 br 13ec .*
+ \.\.\.
+ 13a0: 00 00 00 03.*
+ 13a4: 00 00 14 00.*
+ 13a8: a0 00 10 18.*
+ 13ac: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ \.\.\.
+ 13b8: 00 00 0f 80.*
+ 13bc: 00 00 00 00.*
+ 13c0: 00 00 00 07.*
+ 13c4: 00 04 14 00.*
+ 13c8: a0 00 10 1c.*
+ 13cc: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ \.\.\.
+ 13dc: 00 00 0a 80.*
+ 13e0: 00 00 00 05.*
+ 13e4: 00 04 0c 00.*
+ 13e8: 20 00 13 44.*
+ 13ec: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ 13f0: 00 00 00 00.*
+ 13f4: 00 7f 02 80.*
+ \.\.\.
+
+Disassembly of section \.ovly8:
+
+00001400 <f4>:
+.* 24 00 40 80 stqd \$0,16\(\$1\)
+.* 24 f8 00 81 stqd \$1,-512\(\$1\)
+.* 1c 80 00 81 ai \$1,\$1,-512
+.* 31 02 f9 80 brasl \$0,17cc .*
+ \.\.\.
+.* 32 00 17 80 br 17ec .*
+ \.\.\.
+ 17c0: 00 00 00 02.*
+ 17c4: 00 00 11 04.*
+ 17c8: a0 00 14 0c.*
+ 17cc: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ \.\.\.
+ 17dc: 00 00 d9 00.*
+ 17e0: 00 00 00 06.*
+ 17e4: 00 04 10 00.*
+ 17e8: 20 00 17 30.*
+ 17ec: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ 17f0: 00 7f 0d 80.*
+ \.\.\.
+
+Disassembly of section \.text:
+
+00001800 <_start>:
+.* 41 00 00 03 ilhu \$3,0
+.* 60 8a 00 03 iohl \$3,5120 # 1400
+.* 32 00 04 80 br 182c.*
+ \.\.\.
+ 1820: 00 00 00 01.*
+ 1824: 00 00 0c 00.*
+ 1828: a0 00 18 08.*
+ 182c: 31 03 0a 4b brasl \$75,1850 <__icache_br_handler>
+ \.\.\.
+ 1838: 00 7e 7b 80.*
+ \.\.\.
+
+00001850 <__icache_br_handler>:
+#pass
Index: ld/testsuite/ld-spu/icache1.s
===================================================================
RCS file: ld/testsuite/ld-spu/icache1.s
diff -N ld/testsuite/ld-spu/icache1.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-spu/icache1.s 13 Jan 2009 01:49:09 -0000
@@ -0,0 +1,111 @@
+ .text
+ .globl _start
+ .type _start,@function
+_start:
+ ilhu $3,f5@h
+ iohl $3,f5@l
+ br f1
+
+ .data
+ .word f1, f2, f3, f4
+
+ .section ".f1.part1","ax",@progbits
+ .globl f1
+ .type f1,@function
+f1:
+ nop
+ stqd $0,16($1)
+ ai $1,$1,-64
+ stqd $1,0($1)
+ brsl $0,f2
+ brsl $0,f3
+ .fill 800
+ br .Lf1.part2
+ .size f1,.-f1
+
+ .section ".f1.part2","ax",@progbits
+.Lf1.part2:
+ ai $1,$1,64
+ lqd $0,16($1)
+ bi $0
+ .fill 800
+ .size .Lf1.part2,.-.Lf1.part2
+
+ .section ".f2.part1","ax",@progbits
+ .globl f2
+ .type f2,@function
+f2:
+ ai $1,$1,-128
+ stqd $1,0($1)
+ .fill 512
+ ai $1,$1,128
+ bi $0
+ .size f2,.-f2
+
+ .section ".f3.part1","ax",@progbits
+ .type f3,@function
+f3:
+ .fill 256
+ bi $0
+ .size f3,.-f3
+
+ .section ".f4.part1","ax",@progbits
+ .type f4,@function
+f4:
+ stqd $(0),16($1)
+ stqd $1,-512($1)
+ ai $1,$1,-512
+ brasl $0,f2
+ .fill 800
+ br .Lf4.part2
+ .size f4,.-f4
+
+ .section ".f4.part2","ax",@progbits
+.Lf4.part2:
+#alloca
+ ilhu $3,-4000@h
+ iohl $3,-4000@l
+ a $4,$1,$3
+ lnop
+ ori $1,$4,0
+ stqd $4,0($4)
+ brsl $0,f5
+#recursion
+ brsl $0,f4
+ lqd $1,0($1)
+ .fill 800
+ br .Lf4.part3
+ .size .Lf4.part2,.-.Lf4.part2
+
+ .section ".f4.part3","ax",@progbits
+.Lf4.part3:
+#recursion
+ brasl $0,f4
+ brsl $0,f4
+ .fill 800
+ br .Lf4.part4
+ .size .Lf4.part3,.-.Lf4.part3
+
+ .section ".f4.part4","ax",@progbits
+.Lf4.part4:
+ .fill 800
+ ila $3,512
+ a $1,$1,$3
+ lqd $0,16($1)
+#sibling call
+ bra f5
+ .size .Lf4.part4,.-.Lf4.part4
+
+ .section ".f5.part1","ax",@progbits
+ .type f5,@function
+f5:
+ stqd $(0),16($1)
+ stqd $1,-512($1)
+ ai $1,$1,-512
+ brsl $0,f5
+ .fill 800
+ ila $3,512
+ a $1,$1,$3
+ lqd $0,16($1)
+ bi $0
+ .size f5,.-f5
--
Alan Modra
Australia Development Lab, IBM