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Re: [PATCH] Lexra support in binutils
Thiemo Seufer writes:
> Adam Nemet wrote:
> > Right so did I but isn't the "formula":
> >
> > mips64r2 - MIPS unaligned instructions + custom unaligned instructions = mips64r1.9?
>
> Anything without MIPS unaligned instructions would be mips0.9. I vaguely
> (mis-?)remembered some octeon coprocessor instruction are different, too,
> so I came up with mips0.8 for octeon.
Right. It's only an omission (certain cop2 instructions are not implemented).
Note that these instructions can be selectively implemented by processors so
defining an new ISA for each combination may not scale that well. (Hence was
my idea to create a way for a processor to be defined not just in terms of an
ISA + processor-specific instruction but also in terms of processor-specific
omissions.)
> Custom instructions of any sort would be processor specific, not
> part of an (Pseudo-)ISA. From that POV, the octeon would be a
> mips0.8 + mips2 + mips3 + mips4 + mips64 + mips64r2 + octeon
> part.
Sure but my question was targeted at the *ISA* that this "other" octeon would
be derived from. To avoid any misunderstanding, is this approximately what
you're proposing?:
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.59
diff -u -p -r1.59 mips.h
--- include/opcode/mips.h 12 Jun 2008 21:44:53 -0000 1.59
+++ include/opcode/mips.h 25 Oct 2008 20:01:32 -0000
@@ -511,6 +511,7 @@ struct mips_opcode
#define INSN_ISA_MASK 0x0000000ful
/* We cannot start at zero due to ISA_UNKNOWN below. */
+/* We're out values to define: INSN_ISA0_8 and INSN_ISA0_9. */
#define INSN_ISA1 1
#define INSN_ISA2 2
#define INSN_ISA3 3
@@ -519,16 +520,17 @@ struct mips_opcode
#define INSN_ISA32 6
#define INSN_ISA32R2 7
#define INSN_ISA64 8
-#define INSN_ISA64R2 9
+#define INSN_ISA64R2_0_9 9
+#define INSN_ISA64R2 10
/* Below this point the INSN_* values correspond to combinations of ISAs.
They are only for use in the opcodes table to indicate membership of
a combination of ISAs that cannot be expressed using the usual inclusion
ordering on the above INSN_* values. */
-#define INSN_ISA3_32 10
-#define INSN_ISA3_32R2 11
-#define INSN_ISA4_32 12
-#define INSN_ISA4_32R2 13
-#define INSN_ISA5_32R2 14
+#define INSN_ISA3_32 11
+#define INSN_ISA3_32R2 12
+#define INSN_ISA4_32 13
+#define INSN_ISA4_32R2 14
+#define INSN_ISA5_32R2 15
/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
@@ -539,7 +541,10 @@ struct mips_opcode
(mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
is non-zero. */
static const unsigned int mips_isa_table[] =
- { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
+ { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf,
+ /* Add INSN_ISA64R2_0_9 here: INSN_ISA0_8 + INSN_ISA2 ... + INSN_ISA64R2 */
+ 0x....,
+ 0x3fff };
/* Masks used for Chip specific instructions. */
#define INSN_CHIP_MASK 0xc3ff0800
@@ -605,6 +610,7 @@ static const unsigned int mips_isa_table
#define ISA_MIPS64 INSN_ISA64
#define ISA_MIPS32R2 INSN_ISA32R2
+#define ISA_MIPS64R2_0_9 INSN_ISA64R2_0_9
#define ISA_MIPS64R2 INSN_ISA64R2
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.394
diff -u -p -r1.394 tc-mips.c
--- gas/config/tc-mips.c 8 Aug 2008 19:24:49 -0000 1.394
+++ gas/config/tc-mips.c 25 Oct 2008 20:01:43 -0000
@@ -15173,6 +15173,7 @@ static const struct mips_cpu_info mips_c
ISA_MIPS64, CPU_SB1 },
/* Cavium Networks Octeon CPU core */
+ { "other-octeon" 0, ISA_MIPS64R2_0_9, CPU_OCTEON },
{ "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
/* End marker */
Adam