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Re: PING : [PATCH] Add support for Xilinx FP/APU to PowerPC
- From: Michael Eager <eager at eagercon dot com>
- To: binutils at sourceware dot org, Alan Modra <amodra at bigpond dot net dot au>
- Date: Tue, 03 Jun 2008 14:02:02 -0700
- Subject: Re: PING : [PATCH] Add support for Xilinx FP/APU to PowerPC
- References: <480CDDE3.3080103@eagercon.com> <48372E5F.4050505@eagercon.com> <20080527055620.GE10726@bubble.grove.modra.org>
Alan Modra wrote:
On Fri, May 23, 2008 at 01:51:43PM -0700, Michael Eager wrote:
Could someone please check this in?
No, it has some errors I think. I glanced at it a month ago, saw
one error and put it aside for a proper review, then forgot about it.
Sorry for the delay.
+/* Opcode is supported by PowerPC 405 processor. */
+#define PPC_OPCODE_405 0x10000000
Reuse PPC_OPCODE_PPCPS??
Oops. :-)
{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+
+{"get", APU(4,536), APU_RA_MASK, PPC405 | PPC32, { RT, FSL } },
This isn't the right place to insert these new opcodes. I'm trying to
keep the table more or less sorted, so that you can more easily see
when cpu variants use the same opcode for different instructions.
So "get" ought to go after "evnot", "cget" after "evcmpeq" and so on.
I revised the patch and changed the APU macro so that rc is factored
out, like the A() macro. This makes it easier to put the opcodes in
order. I did notice that there was a re-use of an opcode in one of
the added instructions. I removed this instruction (and the similar
ones) and will submit those as a patch when I resolve the conflict.
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
2008-04-21 Michael J. Eager <eager@eagercon.com>
* gas/config/tc-ppc.c: Add -m405, split definition
of PPC403 & PPC405
2008-04-21 Michael J. Eager <eager@eagercon.com>
* include/opcode/ppc.h: PPC_OPCODE_405: New CPU macro
PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI:
New field macros
2008-04-21 Michael J. Eager <eager@eagercon.com>
* opcodes/ppc-dis.c: Disassemble FSL/FCR/UDI fields
* opcodes/ppc-opc.c: FCRT, FSL, UDI_R[TABC]: New field macros
APU_MASK, APU_RT_MASK, APU_RA_MASK: New insn macros
PPC405: New processor macro
Add get/put/udi instructions
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn binutils-orig/gas/config/tc-ppc.c binutils/gas/config/tc-ppc.c
--- binutils-orig/gas/config/tc-ppc.c 2008-05-30 10:14:40.000000000 -0700
+++ binutils/gas/config/tc-ppc.c 2008-05-30 10:15:34.000000000 -0700
@@ -849,11 +849,12 @@ parse_cpu (const char *arg)
/* Do all PPC750s have paired single ops? */
else if (strcmp (arg, "750cl") == 0)
ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_PPCPS;
- /* -m403 and -m405 mean to assemble for the PowerPC 403/405. */
- else if (strcmp (arg, "403") == 0
- || strcmp (arg, "405") == 0)
+ else if (strcmp (arg, "403") == 0)
ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
| PPC_OPCODE_403 | PPC_OPCODE_32);
+ else if (strcmp (arg, "405") == 0)
+ ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
+ | PPC_OPCODE_403 | PPC_OPCODE_405 | PPC_OPCODE_32);
else if (strcmp (arg, "440") == 0)
ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI);
@@ -1121,7 +1122,8 @@ PowerPC options:\n\
-m601 generate code for PowerPC 601\n\
-mppc, -mppc32, -m603, -m604\n\
generate code for PowerPC 603/604\n\
--m403, -m405 generate code for PowerPC 403/405\n\
+-m403 generate code for PowerPC 403\n\
+-m405 generate code for PowerPC 405\n\
-m440 generate code for PowerPC 440\n\
-m7400, -m7410, -m7450, -m7455\n\
generate code for PowerPC 7400/7410/7450/7455\n\
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn binutils-orig/include/opcode/ppc.h binutils/include/opcode/ppc.h
--- binutils-orig/include/opcode/ppc.h 2008-05-30 10:14:51.000000000 -0700
+++ binutils/include/opcode/ppc.h 2008-05-30 10:15:34.000000000 -0700
@@ -152,6 +152,9 @@ extern const int powerpc_num_opcodes;
/* Opcode is supported by Power E500MC */
#define PPC_OPCODE_E500MC 0x20000000
+/* Opcode is supported by PowerPC 405 processor. */
+#define PPC_OPCODE_405 0x40000000
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
@@ -302,6 +305,11 @@ extern const unsigned int num_powerpc_op
/* Valid range of operand is 0..n rather than 0..n-1. */
#define PPC_OPERAND_PLUS1 (0x10000)
+
+/* Xilinx APU and FSL related operands */
+#define PPC_OPERAND_FSL (0x20000)
+#define PPC_OPERAND_FCR (0x40000)
+#define PPC_OPERAND_UDI (0x80000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn binutils-orig/opcodes/ppc-dis.c binutils/opcodes/ppc-dis.c
--- binutils-orig/opcodes/ppc-dis.c 2008-05-30 10:14:56.000000000 -0700
+++ binutils/opcodes/ppc-dis.c 2008-05-30 10:15:34.000000000 -0700
@@ -313,6 +313,12 @@ print_insn_powerpc (bfd_vma memaddr,
else if ((operand->flags & PPC_OPERAND_CR) == 0
|| (dialect & PPC_OPCODE_PPC) == 0)
(*info->fprintf_func) (info->stream, "%ld", value);
+ else if ((operand->flags & PPC_OPERAND_FSL) != 0)
+ (*info->fprintf_func) (info->stream, "fsl%ld", value);
+ else if ((operand->flags & PPC_OPERAND_FCR) != 0)
+ (*info->fprintf_func) (info->stream, "fcr%ld", value);
+ else if ((operand->flags & PPC_OPERAND_UDI) != 0)
+ (*info->fprintf_func) (info->stream, "%ld", value);
else
{
if (operand->bitm == 7)
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn binutils-orig/opcodes/ppc-opc.c binutils/opcodes/ppc-opc.c
--- binutils-orig/opcodes/ppc-opc.c 2008-05-30 10:14:57.000000000 -0700
+++ binutils/opcodes/ppc-opc.c 2008-06-01 13:18:30.000000000 -0700
@@ -576,6 +576,30 @@ const struct powerpc_operand powerpc_ope
/* The L field in an mtfsf or XFL form instruction. */
#define XFL_L EH + 1
{ 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
+
+ /* Xilinx APU related masks and macros */
+#define FCRT XFL_L + 1
+#define FCRT_MASK (0x1f << 21)
+ { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
+
+ /* Xilinx FSL related masks and macros */
+#define FSL FCRT + 1
+#define FSL_MASK (0x1f << 11)
+ { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
+
+ /* Xilinx UDI related masks and macros */
+#define UDI_RT FSL + 1
+ { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
+
+#define UDI_RA UDI_RT + 1
+ { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
+
+#define UDI_RB UDI_RA + 1
+ { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
+
+#define UDI_RC UDI_RB + 1
+ { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
+
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -1205,12 +1229,9 @@ insert_sprg (unsigned long insn,
int dialect,
const char **errmsg)
{
- /* This check uses PPC_OPCODE_403 because PPC405 is later defined
- as a synonym. If ever a 405 specific dialect is added this
- check should use that instead. */
if (value > 7
|| (value > 3
- && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
+ && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
*errmsg = _("invalid sprg number");
/* If this is mfsprg4..7 then use spr 260..263 which can be read in
@@ -1597,6 +1618,14 @@ extract_tbr (unsigned long insn,
/* The mask for a G form instruction. rc not supported at present. */
#define XW_MASK XW (0x3f, 0x3f, 0)
+/* An APU form instruction. */
+#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
+
+/* The mask for an APU form instruction. */
+#define APU_MASK APU (0x3f, 0x3ff, 1)
+#define APU_RT_MASK (APU_MASK | RT_MASK)
+#define APU_RA_MASK (APU_MASK | RA_MASK)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@@ -1664,7 +1693,7 @@ extract_tbr (unsigned long insn,
#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
#define PPC403 PPC_OPCODE_403
-#define PPC405 PPC403
+#define PPC405 PPC_OPCODE_405
#define PPC440 PPC_OPCODE_440
#define PPC750 PPC
#define PPC7450 PPC
@@ -1936,6 +1981,7 @@ const struct powerpc_opcode powerpc_opco
{"evor", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evnor", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evnot", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, BBA}},
+{"get", APU(4, 268,0), APU_RA_MASK, PPC405|PPC32, {RT, FSL}},
{"eveqv", VX (4, 537), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evorc", VX (4, 539), VX_MASK, PPCSPE, {RS, RA, RB}},
{"evnand", VX (4, 542), VX_MASK, PPCSPE, {RS, RA, RB}},
@@ -1958,6 +2004,7 @@ const struct powerpc_opcode powerpc_opco
{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, {CRFD, RA, RB}},
{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, {CRFD, RA, RB}},
{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, {CRFD, RA, RB}},
+{"cget", APU(4, 284,0), APU_RA_MASK, PPC405|PPC32, {RT, FSL}},
{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vminuh", VX (4, 578), VX_MASK, PPCVEC, {VD, VA, VB}},
{"vsrh", VX (4, 580), VX_MASK, PPCVEC, {VD, VA, VB}},
@@ -1967,6 +2014,8 @@ const struct powerpc_opcode powerpc_opco
{"vsplth", VX (4, 588), VX_MASK, PPCVEC, {VD, VB, UIMM}},
{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, {VD, VB}},
{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, {RS, RA, RB, CRFS}},
+{"nget", APU(4, 300,0), APU_RA_MASK, PPC405|PPC32, {RT, FSL}},
+{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405|PPC32, {RT, FSL}},
{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, {RS, RA, RB}},
{"vadduws", VX (4, 640), VX_MASK, PPCVEC, {VD, VA, VB}},
{"evfssub", VX (4, 641), VX_MASK, PPCSPE, {RS, RA, RB}},
@@ -1993,10 +2042,12 @@ const struct powerpc_opcode powerpc_opco
{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, {RS, RB}},
{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, {RS, RB}},
{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, {RS, RB}},
+{"put", APU(4, 332,0), APU_RT_MASK, PPC405|PPC32, {RA, FSL}},
{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, {RS, RB}},
{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, {CRFD, RA, RB}},
{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, {CRFD, RA, RB}},
{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, {CRFD, RA, RB}},
+{"cput", APU(4, 348,0), APU_RT_MASK, PPC405|PPC32, {RA, FSL}},
{"efsadd", VX (4, 704), VX_MASK, PPCEFS, {RS, RA, RB}},
{"efssub", VX (4, 705), VX_MASK, PPCEFS, {RS, RA, RB}},
{"efsabs", VX (4, 708), VX_MASK, PPCEFS, {RS, RA}},
@@ -2021,6 +2072,7 @@ const struct powerpc_opcode powerpc_opco
{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, {RS, RB}},
{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, {RS, RB}},
{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, {RS, RB}},
+{"nput", APU(4, 364,0), APU_RT_MASK, PPC405|PPC32, {RA, FSL}},
{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, {RS, RB}},
{"efststgt", VX (4, 732), VX_MASK, PPCEFS, {CRFD, RA, RB}},
{"efststlt", VX (4, 733), VX_MASK, PPCEFS, {CRFD, RA, RB}},
@@ -2049,6 +2101,7 @@ const struct powerpc_opcode powerpc_opco
{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, {RS, RB}},
{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, {RS, RB}},
{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, {RS, RB}},
+{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405|PPC32, {RA, FSL}},
{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, {RS, RB}},
{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, {CRFD, RA, RB}},
{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, {CRFD, RA, RB}},
@@ -2316,8 +2369,42 @@ const struct powerpc_opcode powerpc_opco
{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+
{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, {RA, RB}},
+{"udi0fcm.", APU(4,515,0), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi0fcm", APU(4,515,1), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi1fcm.", APU(4,547,0), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi1fcm", APU(4,547,1), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi2fcm.", APU(4,579,0), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi2fcm", APU(4,579,1), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi3fcm.", APU(4,611,0), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi3fcm", APU(4,611,1), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi4fcm.", APU(4,643,0), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi4fcm", APU(4,643,1), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi5fcm.", APU(4,675,0), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi5fcm", APU(4,675,1), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi6fcm.", APU(4,707,0), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi6fcm", APU(4,707,1), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi7fcm.", APU(4,739,0), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi7fcm", APU(4,739,1), APU_MASK, PPC405|PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi8fcm.", APU(4,771,0), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi8fcm", APU(4,771,1), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi9fcm.", APU(4,804,0), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi9fcm", APU(4,804,1), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi10fcm.", APU(4,835,0), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi10fcm", APU(4,835,1), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi11fcm.", APU(4,867,0), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi11fcm", APU(4,867,1), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi12fcm.", APU(4,899,0), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi12fcm", APU(4,899,1), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi13fcm.", APU(4,931,0), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi13fcm", APU(4,931,1), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi14fcm.", APU(4,963,0), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi14fcm", APU(4,963,1), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi15fcm.", APU(4,995,0), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+{"udi15fcm", APU(4,995,1), APU_MASK, PPC440|PPC32, {UDI_RT, UDI_RA, UDI_RB}},
+
{"mulli", OP(7), OP_MASK, PPCCOM, {RT, RA, SI}},
{"muli", OP(7), OP_MASK, PWRCOM, {RT, RA, SI}},
@@ -3187,6 +3274,7 @@ const struct powerpc_opcode powerpc_opco
{"lvsl", X(31,6), X_MASK, PPCVEC, {VD, RA, RB}},
{"lvebx", X(31,7), X_MASK, PPCVEC, {VD, RA, RB}},
+{"lbfcmx", APU(31,7,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
@@ -3254,6 +3342,7 @@ const struct powerpc_opcode powerpc_opco
{"lvsr", X(31,38), X_MASK, PPCVEC, {VD, RA, RB}},
{"lvehx", X(31,39), X_MASK, PPCVEC, {VD, RA, RB}},
+{"lhfcmx", APU(31,39,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"iselgt", X(31,47), X_MASK, PPCISEL, {RT, RA, RB}},
@@ -3305,6 +3394,7 @@ const struct powerpc_opcode powerpc_opco
{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, {RA, RB}},
{"td", X(31,68), X_MASK, PPC64, {TO, RA, RB}},
+{"lwfcmx", APU(31,71,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, {RT, RA, RB}},
{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, {RT, RA, RB}},
@@ -3331,6 +3421,7 @@ const struct powerpc_opcode powerpc_opco
{"lbepx", X(31,95), X_MASK, E500MC, {RT, RA, RB}},
{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}},
+{"lqfcmx", APU(31,103,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"neg", XO(31,104,0,0), XORB_MASK, COM, {RT, RA}},
{"neg.", XO(31,104,0,1), XORB_MASK, COM, {RT, RA}},
@@ -3362,6 +3453,7 @@ const struct powerpc_opcode powerpc_opco
{"dcbtstls", X(31,134), X_MASK, PPCCHLK, {CT, RA, RB}},
{"stvebx", X(31,135), X_MASK, PPCVEC, {VS, RA, RB}},
+{"stbfcmx", APU(31,135,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, {RT, RA, RB}},
{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, {RT, RA, RB}},
@@ -3408,6 +3500,7 @@ const struct powerpc_opcode powerpc_opco
{"dcbtls", X(31,166), X_MASK, PPCCHLK, {CT, RA, RB}},
{"stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}},
+{"sthfcmx", APU(31,167,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"dcbtlse", X(31,174), X_MASK, PPCCHLK64, {CT, RA, RB}},
@@ -3426,6 +3519,7 @@ const struct powerpc_opcode powerpc_opco
{"stwuxe", X(31,191), X_MASK, BOOKE64, {RS, RAS, RB}},
{"stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}},
+{"stwfcmx", APU(31,199,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, {RT, RA}},
{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, {RT, RA}},
@@ -3457,6 +3551,7 @@ const struct powerpc_opcode powerpc_opco
{"icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}},
{"stvx", X(31,231), X_MASK, PPCVEC, {VS, RA, RB}},
+{"stqfcmx", APU(31,231,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, {RT, RA}},
{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, {RT, RA}},
@@ -3498,6 +3593,7 @@ const struct powerpc_opcode powerpc_opco
{"icbt", X(31,262), XRT_MASK, PPC403, {RA, RB}},
+{"ldfcmx", APU(31,263,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"doz", XO(31,264,0,0), XO_MASK, M601, {RT, RA, RB}},
{"doz.", XO(31,264,0,1), XO_MASK, M601, {RT, RA, RB}},
@@ -3801,6 +3897,7 @@ const struct powerpc_opcode powerpc_opco
{"mtdcrx", X(31,387), X_MASK, BOOKE, {RA, RS}},
{"dcblc", X(31,390), X_MASK, PPCCHLK, {CT, RA, RB}},
+{"stdfcmx", APU(31,391,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
@@ -4081,6 +4178,7 @@ const struct powerpc_opcode powerpc_opco
{"bblels", X(31,518), X_MASK, PPCBRLK, {0}},
{"lvlx", X(31,519), X_MASK, CELL, {VD, RA0, RB}},
+{"lbfcmux", APU(31,519,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
@@ -4131,6 +4229,7 @@ const struct powerpc_opcode powerpc_opco
{"bbelr", X(31,550), X_MASK, PPCBRLK, {0}},
{"lvrx", X(31,551), X_MASK, CELL, {VD, RA0, RB}},
+{"lhfcmux", APU(31,551,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"subfo", XO(31,40,1,0), XO_MASK, PPC, {RT, RA, RB}},
{"subo", XO(31,40,1,0), XO_MASK, PPC, {RT, RB, RA}},
@@ -4145,6 +4244,8 @@ const struct powerpc_opcode powerpc_opco
{"lwdx", X(31,579), X_MASK, E500MC, {RT, RA, RB}},
+{"lwfcmux", APU(31,583,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
+
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, {RT, SR}},
{"lswi", X(31,597), X_MASK, PPCCOM, {RT, RA0, NB}},
@@ -4170,6 +4271,8 @@ const struct powerpc_opcode powerpc_opco
{"mulo", XO(31,107,1,0), XO_MASK, M601, {RT, RA, RB}},
{"mulo.", XO(31,107,1,1), XO_MASK, M601, {RT, RA, RB}},
+{"lqfcmux", APU(31,615,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
+
{"mfsri", X(31,627), X_MASK, PWRCOM, {RT, RA, RB}},
{"dclst", X(31,630), XRB_MASK, PWRCOM, {RS, RA}},
@@ -4181,6 +4284,7 @@ const struct powerpc_opcode powerpc_opco
{"stbdx", X(31,643), X_MASK, E500MC, {RS, RA, RB}},
{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}},
+{"stbfcmux", APU(31,647,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
@@ -4217,6 +4321,7 @@ const struct powerpc_opcode powerpc_opco
{"sthdx", X(31,675), X_MASK, E500MC, {RS, RA, RB}},
{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}},
+{"sthfcmux", APU(31,679,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"stfsux", X(31,695), X_MASK, COM, {FRS, RAS, RB}},
@@ -4272,6 +4377,8 @@ const struct powerpc_opcode powerpc_opco
{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
+{"stqfcmux", APU(31,743,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
+
{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, {RA, RB}},
{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, {RA, RB}},
@@ -4284,7 +4391,10 @@ const struct powerpc_opcode powerpc_opco
{"stfduxe", X(31,767), X_MASK, BOOKE64, {FRS, RAS, RB}},
+{"stwfcmux", APU(31,711,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
+
{"lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}},
+{"ldfcmux", APU(31,775,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"dozo", XO(31,264,1,0), XO_MASK, M601, {RT, RA, RB}},
{"dozo.", XO(31,264,1,1), XO_MASK, M601, {RT, RA, RB}},
@@ -4362,6 +4472,7 @@ const struct powerpc_opcode powerpc_opco
{"ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}},
{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}},
+{"stdfcmux", APU(31,903,0), APU_MASK, PPC405|PPC32, {FCRT, RA, RB}},
{"subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},