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Re: [PATCH]: More GAS sparc improvements.
- From: David Miller <davem at davemloft dot net>
- To: binutils at sourceware dot org
- Date: Tue, 29 Apr 2008 03:50:18 -0700 (PDT)
- Subject: Re: [PATCH]: More GAS sparc improvements.
- References: <20080424.020448.141605174.davem@davemloft.net>
From: David Miller <davem@davemloft.net>
Date: Thu, 24 Apr 2008 02:04:48 -0700 (PDT)
> The bulk of this change is the addition of a section on
> Sparc opcode translations to the GAS manual. The rest
> are minor fixups and clarifications in Sparc GAS and the
> disassembler.
>
> Ok to commit?
Ping?
> gas/
>
> 2008-04-24 David S. Miller <davem@davemloft.net>
>
> * config/tc-sparc.c: Accept 'softint_clear' and 'softint_set'
> %asr aliases.
>
> * doc/c-sparc.texi: Consistently refer to architecture 'versions',
> rather than occaisionally 'levels'. Consistently refer to Sun's
> UNIX variant as SunOS, every version of Solaris is also SunOS.
> Document new 'softint_clear' and 'softint_set' aliases. Clarify
> which architecture versions support '%dcr', '%cq', and '%gl'. Add
> section on 32-bit/64-bit opcode translations.
>
> Index: gas/config/tc-sparc.c
> ===================================================================
> RCS file: /cvs/src/src/gas/config/tc-sparc.c,v
> retrieving revision 1.72
> diff -u -p -r1.72 tc-sparc.c
> --- gas/config/tc-sparc.c 23 Apr 2008 07:49:33 -0000 1.72
> +++ gas/config/tc-sparc.c 24 Apr 2008 08:52:19 -0000
> @@ -779,6 +779,8 @@ struct priv_reg_entry v9a_asr_table[] =
> {"stick_cmpr", 25},
> {"stick", 24},
> {"softint", 22},
> + {"softint_clear", 21},
> + {"softint_set", 20},
> {"set_softint", 20},
> {"pic", 17},
> {"pcr", 16},
> Index: gas/doc/c-sparc.texi
> ===================================================================
> RCS file: /cvs/src/src/gas/doc/c-sparc.texi,v
> retrieving revision 1.8
> diff -u -p -r1.8 c-sparc.texi
> --- gas/doc/c-sparc.texi 23 Apr 2008 07:49:33 -0000 1.8
> +++ gas/doc/c-sparc.texi 24 Apr 2008 08:52:19 -0000
> @@ -28,9 +28,9 @@
> @cindex SPARC options
> @cindex architectures, SPARC
> @cindex SPARC architectures
> -The SPARC chip family includes several successive levels, using the same
> +The SPARC chip family includes several successive versions, using the same
> core instruction set, but including a few additional instructions at
> -each level. There are exceptions to this however. For details on what
> +each version. There are exceptions to this however. For details on what
> instructions each variant supports, please see the chip's architecture
> reference manual.
>
> @@ -40,7 +40,7 @@ successively higher architectures as it
> only exist in the higher levels.
>
> If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
> -passed sparclite by default, an option must be passed to enable the
> +past sparclite by default, an option must be passed to enable the
> v9 instructions.
>
> GAS treats sparclite as being compatible with v8, unless an architecture
> @@ -74,7 +74,7 @@ support.
> UltraSPARC extensions.
>
> @item -xarch=v8plus | -xarch=v8plusa
> -For compatibility with the Solaris v9 assembler. These options are
> +For compatibility with the SunOS v9 assembler. These options are
> equivalent to -Av8plus and -Av8plusa, respectively.
>
> @item -bump
> @@ -96,12 +96,12 @@ and require that the necessary BFD suppo
> @cindex SPARC data alignment
> SPARC GAS normally permits data to be misaligned. For example, it
> permits the @code{.long} pseudo-op to be used on a byte boundary.
> -However, the native SunOS and Solaris assemblers issue an error when
> -they see misaligned data.
> +However, the native SunOS assemblers issue an error when they see
> +misaligned data.
>
> @kindex --enforce-aligned-data
> You can use the @code{--enforce-aligned-data} option to make SPARC GAS
> -also issue an error about misaligned data, just as the SunOS and Solaris
> +also issue an error about misaligned data, just as the SunOS
> assemblers do.
>
> The @code{--enforce-aligned-data} option is not the default because gcc
> @@ -123,6 +123,7 @@ for their UltraSPARC and Niagara line of
> * Sparc-Regs:: Register Names
> * Sparc-Constants:: Constant Names
> * Sparc-Relocs:: Relocations
> +* Sparc-Size-Translations:: Size Translations
> @end menu
>
> @node Sparc-Chars
> @@ -177,7 +178,7 @@ is a legal floating point register, but
>
> Certain V9 instructions allow access to ancillary state registers.
> Most simply they can be referred to as @samp{%asr@var{n}} where
> -@var{n} can be from 16 to 31. However, there are some aliased
> +@var{n} can be from 16 to 31. However, there are some aliases
> defined to reference ASR registers defined for various UltraSPARC
> processors:
>
> @@ -200,10 +201,12 @@ The software interrupt register is refer
>
> @item
> The set software interrupt register is referred to as @samp{%set_softint}.
> +The mnemonic @samp{%softint_set} is provided as an alias.
>
> @item
> The clear software interrupt register is referred to as
> -@samp{%clear_softint}.
> +@samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided
> +as an alias.
>
> @item
> The performance instrumentation counters register is referred to as
> @@ -216,7 +219,7 @@ The performance control register is refe
> The graphics status register is referred to as @samp{%gsr}.
>
> @item
> -The dispatch control register is referred to as @samp{%dcr}.
> +The V9 dispatch control register is referred to as @samp{%dcr}.
> @end itemize
>
> Various V9 branch and conditional move instructions allow
> @@ -249,7 +252,7 @@ The V9 current window pointer register i
> The floating-point queue register is referred to as @samp{%fq}.
>
> @item
> -The co-processor queue register is referred to as @samp{%cq}.
> +The V8 co-processor queue register is referred to as @samp{%cq}.
>
> @item
> The floating point status register is referred to as @samp{%fsr}.
> @@ -312,7 +315,7 @@ The V8 window invalid mask register is r
> The V8 processor state register is referred to as @samp{%psr}.
>
> @item
> -The global register level register is referred to as @samp{%gl}.
> +The V9 global register level register is referred to as @samp{%gl}.
> @end itemize
>
> Several special register names exist for hypervisor mode code:
> @@ -644,6 +647,73 @@ specified in an address expression that
> an @code{R_SPARC_LO10} relocation, the assembler will emit an
> @code{R_SPARC_OLO10} instead.
>
> +@node Sparc-Size-Translations
> +@subsection Size Translations
> +@cindex Sparc size translations
> +@cindex size, translations, Sparc
> +
> +Often it is desirable to write code in an operand size agnostic
> +manner. @code{@value{AS}} provides support for this via
> +operand size opcode translations. Translations are supported
> +for loads, stores, shifts, compare-and-swap atomics, and the
> +@samp{clr} synthetic instruction.
> +
> +If generating 32-bit code, @code{@value{AS}} will generate the
> +32-bit opcode. Whereas if 64-bit code is being generated,
> +the 64-bit opcode will be emitted. For example @code{ldn}
> +will be transformed into @code{ld} for 32-bit code and
> +@code{ldx} for 64-bit code.
> +
> +Here is an example meant to demonstrate all the supported
> +opcode translations:
> +
> +@example
> +ldn [%o0], %o1
> +ldna [%o0] %asi, %o2
> +stn %o1, [%o0]
> +stna %o2, [%o0] %asi
> +slln %o3, 3, %o3
> +srln %o4, 8, %o4
> +sran %o5, 12, %o5
> +casn [%o0], %o1, %o2
> +casna [%o0] %asi, %o1, %o2
> +clrn %g1
> +@end example
> +
> +In 32-bit mode @code{@value{AS}} will emit:
> +
> +@example
> +ld [%o0], %o1
> +lda [%o0] %asi, %o2
> +st %o1, [%o0]
> +sta %o2, [%o0] %asi
> +sll %o3, 3, %o3
> +srl %o4, 8, %o4
> +sra %o5, 12, %o5
> +cas [%o0], %o1, %o2
> +casa [%o0] %asi, %o1, %o2
> +clr %g1
> +@end example
> +
> +And in 64-bit mode @code{@value{AS}} will emit:
> +
> +@example
> +ldx [%o0], %o1
> +ldxa [%o0] %asi, %o2
> +stx %o1, [%o0]
> +stxa %o2, [%o0] %asi
> +sllx %o3, 3, %o3
> +srlx %o4, 8, %o4
> +srax %o5, 12, %o5
> +casx [%o0], %o1, %o2
> +casxa [%o0] %asi, %o1, %o2
> +clrx %g1
> +@end example
> +
> +Finally, the @samp{.nword} translating directive is supported
> +as well. It is documented in the section on Sparc machine
> +directives.
> +
> @node Sparc-Float
> @section Floating Point
>
> opcodes/
>
> 2008-04-24 David S. Miller <davem@davemloft.net>
>
> * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
> instead of %sys_tick_cmpr, as suggested in architecture manuals.
>
> Index: opcodes/sparc-dis.c
> ===================================================================
> RCS file: /cvs/src/src/opcodes/sparc-dis.c,v
> retrieving revision 1.14
> diff -u -p -r1.14 sparc-dis.c
> --- opcodes/sparc-dis.c 5 Jul 2007 09:49:02 -0000 1.14
> +++ opcodes/sparc-dis.c 24 Apr 2008 08:52:24 -0000
> @@ -107,7 +107,7 @@ static char *v9_hpriv_reg_names[] =
> static char *v9a_asr_reg_names[] =
> {
> "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
> - "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
> + "softint", "tick_cmpr", "stick", "stick_cmpr"
> };
>
> /* Macros used to extract instruction fields. Not all fields have