Re: [PATCH] Add x86 SSE5 instructions to the GNU binary utilities

["H.J. Lu" <hjl at lucon dot org>]

On Thu, Sep 13, 2007 at 03:44:19PM -0500, rajagopal, dwarak wrote:
> Yes SSE5 uses the same opcode (0f 24) for move test registers. The only
> way to disambiguate is that the 3rd opcode does not have upper 2 bits
> set. 
> 
> It is better to do this test in print_insn() than in get_valid_dis386()
> because the only way to disambiguate this case is by using the 3rd
> opcode and not modrm bits. 
> That is why I removed OPC_EXT_45.
> 

OPC_EXT_45 is

  {
    /* OPC_EXT_45 */
    { "(bad)",          { XX } }, 
    { "movL",           { Td, Rd } }, 
  },

    { "(bad)",          { XX } }, 

is for instructions whose 3rd opcode has upper 2 bits cleared.
You just replace it with a table. Everything should work.


H.J.