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Re: PATCH: Properly handle x86 crc32 in Intel mode
- From: "H. J. Lu" <hjl at lucon dot org>
- To: Jan Beulich <jbeulich at novell dot com>
- Cc: binutils at sourceware dot org
- Date: Wed, 2 May 2007 05:56:02 -0700
- Subject: Re: PATCH: Properly handle x86 crc32 in Intel mode
- References: <20070430174005.GA9211@lucon.org> <46387217.76E4.0078.0@novell.com>
On Wed, May 02, 2007 at 10:12:23AM +0100, Jan Beulich wrote:
> >>> "H. J. Lu" <hjl@lucon.org> 30.04.07 19:40 >>>
> >This patch fixes crc32 in Intel mode. I will check it in if there
> >are no objections in a day or 2.
>
> I completely disagree here. No suffixes should be used in Intel mode unless
> there's no other way to distinguish multiple possible operand sizes. Hence the
> crc32-intel test is entirely wrong. The second operand's size of crc32 should
> be deduced from register size or memory operand size specifier, and if there's
> a memory operand without specifier it should be warned about just like in all
> other ambiguous cases.
crc32 is a very special instruction and doesn't follow the normal
rule.
>
> Also, while at this - could you have your doc people clarify the meaning of
> an operand size prefix used with this instruction? Since all other 3-byte SSE4
> insns use this prefix (I really wonder why), explicitly stating its meaning on
> crc32 would disambiguate things.
I don't believe the gas manual need to cover those kinds of things
in ISA spec.
H.J.