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--enable-checking for gas
- From: Alan Modra <amodra at bigpond dot net dot au>
- To: binutils at sourceware dot org
- Date: Sat, 21 Apr 2007 14:46:32 +0930
- Subject: --enable-checking for gas
Further cleanup of ppc-opc.c, and add --enable-checking configure
option to gas. --enable-checking, on by default except for a release,
turns on all the gas "know" assertions. We trigger quite a few...
gas/
* as.h (ENABLE_CHECKING): Default define to 0.
(know): Assert if ENABLE_CHECKING.
(struct relax_type): Remove superfluous declaration.
* configure.in (--enable-checking): New.
* configure: Regenerate.
* config.in: Regenerate.
* config/tc-ppc.c (ppc_setup_opcodes): Do checks when ENABLE_CHECKING.
Check for duplicate powerpc_operands entries.
opcodes/
* ppc-opc.c (powerpc_operands): Delete duplicate entries.
(BA_MASK, FXM_MASK, STRM_MASK, VA_MASK, VB_MASK, VC_MASK): Delete.
(VD_MASK, WS_MASK, MTMSRD_L, XRT_L): Delete.
(powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L.
Index: gas/as.h
===================================================================
RCS file: /cvs/src/src/gas/as.h,v
retrieving revision 1.55
diff -u -p -r1.55 as.h
--- gas/as.h 9 Mar 2007 07:14:23 -0000 1.55
+++ gas/as.h 21 Apr 2007 04:56:36 -0000
@@ -258,7 +258,11 @@ typedef addressT valueT;
#endif
/* COMMON now defined */
-#ifdef DEBUG
+#ifndef ENABLE_CHECKING
+#define ENABLE_CHECKING 0
+#endif
+
+#if ENABLE_CHECKING || defined (DEBUG)
#ifndef know
#define know(p) assert(p) /* Verify our assumptions! */
#endif /* not yet defined */
@@ -566,7 +570,6 @@ segT subseg_get (const char *, int);
struct expressionS;
struct fix;
typedef struct symbol symbolS;
-struct relax_type;
typedef struct frag fragS;
/* literal.c */
Index: gas/configure.in
===================================================================
RCS file: /cvs/src/src/gas/configure.in,v
retrieving revision 1.200
diff -u -p -r1.200 configure.in
--- gas/configure.in 15 Mar 2007 14:31:24 -0000 1.200
+++ gas/configure.in 21 Apr 2007 04:56:42 -0000
@@ -30,6 +30,7 @@ AC_ARG_ENABLE(targets,
no) enable_targets= ;;
*) enable_targets=$enableval ;;
esac])dnl
+
AC_ARG_ENABLE(commonbfdlib,
[ --enable-commonbfdlib build shared BFD/opcodes/libiberty library],
[case "${enableval}" in
@@ -38,6 +39,20 @@ AC_ARG_ENABLE(commonbfdlib,
*) AC_MSG_ERROR([bad value ${enableval} for BFD commonbfdlib option]) ;;
esac])dnl
+ac_checking=yes
+if grep '^RELEASE=y' ${srcdir}/../bfd/Makefile.am >/dev/null 2>/dev/null ; then
+ ac_checking=
+fi
+AC_ARG_ENABLE(checking,
+[ --enable-checking enable run-time checks],
+[case "${enableval}" in
+ no|none) ac_checking= ;;
+ *) ac_checking=yes ;;
+esac])dnl
+if test x$ac_checking != x ; then
+ AC_DEFINE(ENABLE_CHECKING, 1, [Define if you want run-time sanity checks.])
+fi
+
using_cgen=no
AM_BINUTILS_WARNINGS
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.117
diff -u -p -r1.117 tc-ppc.c
--- gas/config/tc-ppc.c 20 Apr 2007 13:42:03 -0000 1.117
+++ gas/config/tc-ppc.c 21 Apr 2007 04:56:49 -0000
@@ -1248,7 +1248,6 @@ ppc_setup_opcodes (void)
const struct powerpc_opcode *op_end;
const struct powerpc_macro *macro;
const struct powerpc_macro *macro_end;
- unsigned int i;
bfd_boolean bad_insn = FALSE;
if (ppc_hash != NULL)
@@ -1259,60 +1258,77 @@ ppc_setup_opcodes (void)
/* Insert the opcodes into a hash table. */
ppc_hash = hash_new ();
- /* Check operand masks. Code here and in the disassembler assumes
- all the 1's in the mask are contiguous. */
- for (i = 0; i < num_powerpc_operands; ++i)
- {
- unsigned long mask = powerpc_operands[i].bitm;
- unsigned long right_bit;
-
- right_bit = mask & -mask;
- mask += right_bit;
- right_bit = mask & -mask;
- if (mask != right_bit)
- {
- as_bad (_("powerpc_operands[%d].bitm invalid"), i);
- bad_insn = TRUE;
+ if (ENABLE_CHECKING)
+ {
+ unsigned int i;
+
+ /* Check operand masks. Code here and in the disassembler assumes
+ all the 1's in the mask are contiguous. */
+ for (i = 0; i < num_powerpc_operands; ++i)
+ {
+ unsigned long mask = powerpc_operands[i].bitm;
+ unsigned long right_bit;
+ unsigned int j;
+
+ right_bit = mask & -mask;
+ mask += right_bit;
+ right_bit = mask & -mask;
+ if (mask != right_bit)
+ {
+ as_bad (_("powerpc_operands[%d].bitm invalid"), i);
+ bad_insn = TRUE;
+ }
+ for (j = i + 1; j < num_powerpc_operands; ++j)
+ if (memcmp (&powerpc_operands[i], &powerpc_operands[j],
+ sizeof (powerpc_operands[0])) == 0)
+ {
+ as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
+ j, i);
+ bad_insn = TRUE;
+ }
}
}
op_end = powerpc_opcodes + powerpc_num_opcodes;
for (op = powerpc_opcodes; op < op_end; op++)
{
- const unsigned char *o;
- unsigned long omask = op->mask;
-
- /* The mask had better not trim off opcode bits. */
- if ((op->opcode & omask) != op->opcode)
+ if (ENABLE_CHECKING)
{
- as_bad (_("mask trims opcode bits for %s"),
- op->name);
- bad_insn = TRUE;
- }
+ const unsigned char *o;
+ unsigned long omask = op->mask;
- /* The operands must not overlap the opcode or each other. */
- for (o = op->operands; *o; ++o)
- if (*o >= num_powerpc_operands)
- {
- as_bad (_("operand index error for %s"),
- op->name);
- bad_insn = TRUE;
- }
- else
- {
- const struct powerpc_operand *operand = &powerpc_operands[*o];
- if (operand->shift >= 0)
+ /* The mask had better not trim off opcode bits. */
+ if ((op->opcode & omask) != op->opcode)
+ {
+ as_bad (_("mask trims opcode bits for %s"),
+ op->name);
+ bad_insn = TRUE;
+ }
+
+ /* The operands must not overlap the opcode or each other. */
+ for (o = op->operands; *o; ++o)
+ if (*o >= num_powerpc_operands)
+ {
+ as_bad (_("operand index error for %s"),
+ op->name);
+ bad_insn = TRUE;
+ }
+ else
{
- unsigned long mask = operand->bitm << operand->shift;
- if (omask & mask)
+ const struct powerpc_operand *operand = &powerpc_operands[*o];
+ if (operand->shift >= 0)
{
- as_bad (_("operand %d overlap in %s"),
- (int) (o - op->operands), op->name);
- bad_insn = TRUE;
+ unsigned long mask = operand->bitm << operand->shift;
+ if (omask & mask)
+ {
+ as_bad (_("operand %d overlap in %s"),
+ (int) (o - op->operands), op->name);
+ bad_insn = TRUE;
+ }
+ omask |= mask;
}
- omask |= mask;
}
- }
+ }
if ((op->flags & ppc_cpu & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) != 0
&& ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.93
diff -u -p -r1.93 ppc-opc.c
--- opcodes/ppc-opc.c 20 Apr 2007 12:25:13 -0000 1.93
+++ opcodes/ppc-opc.c 21 Apr 2007 04:57:14 -0000
@@ -76,7 +76,7 @@ static long extract_tbr (unsigned long,
/* The operands table.
- The fields are bits, shift, insert, extract, flags.
+ The fields are bitm, shift, insert, extract, flags.
We used to put parens around the various additions, like the one
for BA just below. However, that caused trouble with feeble
@@ -94,7 +94,9 @@ const struct powerpc_operand powerpc_ope
/* The BA field in an XL form instruction. */
#define BA UNUSED + 1
-#define BA_MASK (0x1f << 16)
+ /* The BI field in a B form or XL form instruction. */
+#define BI BA
+#define BI_MASK (0x1f << 16)
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
/* The BA field in an XL form instruction when it must be the same
@@ -148,6 +150,8 @@ const struct powerpc_operand powerpc_ope
/* The BF field in an X or XL form instruction. */
#define BF BDPA + 1
+ /* The CRFD field in an X form instruction. */
+#define CRFD BF
{ 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
/* An optional BF field. This is used for comparison instructions,
@@ -159,14 +163,9 @@ const struct powerpc_operand powerpc_ope
#define BFA OBF + 1
{ 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
- /* The BI field in a B form or XL form instruction. */
-#define BI BFA + 1
-#define BI_MASK (0x1f << 16)
- { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
-
/* The BO field in a B form instruction. Certain values are
illegal. */
-#define BO BI + 1
+#define BO BFA + 1
#define BO_MASK (0x1f << 21)
{ 0x1f, 21, insert_bo, extract_bo, 0 },
@@ -191,18 +190,19 @@ const struct powerpc_operand powerpc_ope
/* The CRB field in an X form instruction. */
#define CRB CR + 1
+ /* The MB field in an M form instruction. */
+#define MB CRB
+#define MB_MASK (0x1f << 6)
{ 0x1f, 6, NULL, NULL, 0 },
- /* The CRFD field in an X form instruction. */
-#define CRFD CRB + 1
- { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
-
/* The CRFS field in an X form instruction. */
-#define CRFS CRFD + 1
+#define CRFS CRB + 1
{ 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
/* The CT field in an X form instruction. */
#define CT CRFS + 1
+ /* The MO field in an mbar instruction. */
+#define MO CT
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The D field in a D form instruction. This is a displacement off
@@ -239,6 +239,8 @@ const struct powerpc_operand powerpc_ope
/* The FL1 field in a POWER SC form instruction. */
#define FL1 E + 1
+ /* The U field in an X form instruction. */
+#define U FL1
{ 0xf, 12, NULL, NULL, 0 },
/* The FL2 field in a POWER SC form instruction. */
@@ -272,7 +274,6 @@ const struct powerpc_operand powerpc_ope
/* The FXM field in an XFX instruction. */
#define FXM FRS + 1
-#define FXM_MASK (0xff << 12)
{ 0xff, 12, insert_fxm, extract_fxm, 0 },
/* Power4 version for mfcr. */
@@ -305,13 +306,8 @@ const struct powerpc_operand powerpc_ope
#define LS LIA + 1
{ 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
- /* The MB field in an M form instruction. */
-#define MB LS + 1
-#define MB_MASK (0x1f << 6)
- { 0x1f, 6, NULL, NULL, 0 },
-
/* The ME field in an M form instruction. */
-#define ME MB + 1
+#define ME LS + 1
#define ME_MASK (0x1f << 1)
{ 0x1f, 1, NULL, NULL, 0 },
@@ -330,13 +326,9 @@ const struct powerpc_operand powerpc_ope
#define MB6_MASK (0x3f << 5)
{ 0x3f, 5, insert_mb6, extract_mb6, 0 },
- /* The MO field in an mbar instruction. */
-#define MO MB6 + 1
- { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
/* The NB field in an X form instruction. The value 32 is stored as
0. */
-#define NB MO + 1
+#define NB MB6 + 1
{ 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
/* The NSI field in a D form instruction. This is the same as the
@@ -399,24 +391,22 @@ const struct powerpc_operand powerpc_ope
#define RT_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
- /* The RS field of the DS form stq instruction, which has special
- value restrictions. */
+ /* The RS and RT fields of the DS form stq instruction, which have
+ special value restrictions. */
#define RSQ RS + 1
- { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
-
- /* The RT field of the DQ form lq instruction, which has special
- value restrictions. */
-#define RTQ RSQ + 1
+#define RTQ RSQ
{ 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
/* The RS field of the tlbwe instruction, which is optional. */
-#define RSO RTQ + 1
+#define RSO RSQ + 1
#define RTO RSO
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
/* The SH field in an X or M form instruction. */
#define SH RSO + 1
#define SH_MASK (0x1f << 11)
+ /* The other UIMM field in a EVX form instruction. */
+#define EVUIMM SH
{ 0x1f, 11, NULL, NULL, 0 },
/* The SH field in an MD form instruction. This is split. */
@@ -459,7 +449,6 @@ const struct powerpc_operand powerpc_ope
/* The STRM field in an X AltiVec form instruction. */
#define STRM SR + 1
-#define STRM_MASK (0x3 << 21)
{ 0x3, 21, NULL, NULL, 0 },
/* The SV field in a POWER SC form instruction. */
@@ -476,33 +465,25 @@ const struct powerpc_operand powerpc_ope
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
- /* The U field in an X form instruction. */
-#define U TO + 1
- { 0xf, 12, NULL, NULL, 0 },
-
/* The UI field in a D form instruction. */
-#define UI U + 1
+#define UI TO + 1
{ 0xffff, 0, NULL, NULL, 0 },
/* The VA field in a VA, VX or VXR form instruction. */
#define VA UI + 1
-#define VA_MASK (0x1f << 16)
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
/* The VB field in a VA, VX or VXR form instruction. */
#define VB VA + 1
-#define VB_MASK (0x1f << 11)
{ 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
/* The VC field in a VA form instruction. */
#define VC VB + 1
-#define VC_MASK (0x1f << 6)
{ 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
/* The VD or VS field in a VA, VX, VXR or X form instruction. */
#define VD VC + 1
#define VS VD
-#define VD_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
/* The SIMM field in a VX form instruction. */
@@ -518,12 +499,8 @@ const struct powerpc_operand powerpc_ope
#define SHB UIMM + 1
{ 0xf, 6, NULL, NULL, 0 },
- /* The other UIMM field in a EVX form instruction. */
-#define EVUIMM SHB + 1
- { 0x1f, 11, NULL, NULL, 0 },
-
/* The other UIMM field in a half word EVX form instruction. */
-#define EVUIMM_2 EVUIMM + 1
+#define EVUIMM_2 SHB + 1
{ 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
/* The other UIMM field in a word EVX form instruction. */
@@ -536,12 +513,10 @@ const struct powerpc_operand powerpc_ope
/* The WS field. */
#define WS EVUIMM_8 + 1
-#define WS_MASK (0x7 << 11)
{ 0x7, 11, NULL, NULL, 0 },
/* The L field in an mtmsrd or A form instruction. */
-#define MTMSRD_L WS + 1
-#define A_L MTMSRD_L
+#define A_L WS + 1
{ 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
#define RMC A_L + 1
@@ -563,12 +538,8 @@ const struct powerpc_operand powerpc_ope
#define DGM DCM
{ 0x3f, 10, NULL, NULL, 0 },
- /* The L field in an X form with the RT field fixed instruction. */
-#define XRT_L SH16 + 1
- { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
/* The EH field in larx instruction. */
-#define EH XRT_L + 1
+#define EH SH16 + 1
{ 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
};
@@ -3236,7 +3207,7 @@ const struct powerpc_opcode powerpc_opco
{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
-{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
+{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
@@ -3325,7 +3296,7 @@ const struct powerpc_opcode powerpc_opco
{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
-{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
+{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
--
Alan Modra
IBM OzLabs - Linux Technology Centre