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New SPU instructions.


This adds some instructions available in newer SPU chips.
http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/76CA6C7304210F3987257060006F2C44

	* spu-insns.h: Add soma double-float insns.

Index: include/opcode/spu-insns.h
===================================================================
RCS file: /cvs/src/src/include/opcode/spu-insns.h,v
retrieving revision 1.1
diff -u -p -r1.1 spu-insns.h
--- include/opcode/spu-insns.h	25 Oct 2006 06:49:18 -0000	1.1
+++ include/opcode/spu-insns.h	27 Feb 2007 08:38:20 -0000
@@ -403,6 +403,13 @@ APUOPFB(M_BITE, 	RR,	0x129,	0x10,	"bite"
 APUOPFB(M_BIFD,		RR,	0x128,	0x20,	"bifd",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
 APUOPFB(M_BIFE,		RR,	0x128,	0x10,	"bife",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
 
+/* New soma double-float insns.  */
+APUOP(M_DFCEQ,		RR,	0x3c3,	"dfceq",	_A3(A_T,A_A,A_B),	00112,	FX2)	/* DFCEQ         RT<-(RA=RB) */
+APUOP(M_DFCMEQ,		RR,	0x3cb,	"dfcmeq",	_A3(A_T,A_A,A_B),	00112,	FX2)	/* DFCMEQ        RT<-(|RA|=|RB|) */
+APUOP(M_DFCGT,		RR,	0x2c3,	"dfcgt",	_A3(A_T,A_A,A_B),	00112,	FX2)	/* DFCGT         RT<-(RA>RB) */
+APUOP(M_DFCMGT,		RR,	0x2cb,	"dfcmgt",	_A3(A_T,A_A,A_B),	00112,	FX2)	/* DFCMGT        RT<-(|RA|>|RB|) */
+APUOP(M_DFTSV,		RI7,	0x3bf,	"dftsv",	_A3(A_T,A_A,A_U7),	00012,	FX2)	/* DFTSV         RT<-testspecial(RA,I7) */
+
 #undef _A0
 #undef _A1
 #undef _A2

-- 
Alan Modra
IBM OzLabs - Linux Technology Centre


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