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[patch] Incorrect Thumb-2 add encoding


The patch below fixes incorrect encoding of the Thumb-2 add instruction when 
only one register operand is specified. We carefully figure out what Rd and 
Rs should be, then ignore them.

Tested with cross to arm-none-eabi.
Ok?

Paul

2007-01-11  Paul Brook  <paul@codesourcery.com>

	gas/
	* config/tc-arm.c (do_t_add_sub): Use Rd and Rs.
	gas/testsuite/
	* gas/arm/thumb2_add.d: Add test for missing operand.

Index: gas/config/tc-arm.c
===================================================================
--- gas/config/tc-arm.c	(revision 159807)
+++ gas/config/tc-arm.c	(working copy)
@@ -8410,8 +8410,8 @@ do_t_add_sub (void)
 		  else
 		    inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
 		}
-	      inst.instruction |= inst.operands[0].reg << 8;
-	      inst.instruction |= inst.operands[1].reg << 16;
+	      inst.instruction |= Rd << 8;
+	      inst.instruction |= Rs << 16;
 	    }
 	}
       else
Index: gas/testsuite/gas/arm/thumb2_add.d
===================================================================
--- gas/testsuite/gas/arm/thumb2_add.d	(revision 159807)
+++ gas/testsuite/gas/arm/thumb2_add.d	(working copy)
@@ -16,3 +16,5 @@ Disassembly of section .text:
 0+024 <[^>]+> f5a9 6880 	sub.w	r8, r9, #1024	; 0x400
 0+028 <[^>]+> f2a9 1801 	subw	r8, r9, #257	; 0x101
 0+02c <[^>]+> f2a1 1301 	subw	r3, r1, #257	; 0x101
+0+030 <[^>]+> f103 0301 	add.w	r3, r3, #1	; 0x1
+0+034 <[^>]+> f1a3 0301 	sub.w	r3, r3, #1	; 0x1
Index: gas/testsuite/gas/arm/thumb2_add.s
===================================================================
--- gas/testsuite/gas/arm/thumb2_add.s	(revision 159807)
+++ gas/testsuite/gas/arm/thumb2_add.s	(working copy)
@@ -18,3 +18,5 @@ thumb2_add:
 	sub r8, r9, #0x400
 	sub r8, r9, #0x101
 	sub r3, r1, #0x101
+	add r3, #1
+	sub r3, #1


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