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[m32c] cpu tweaks: jsri, index*
- From: DJ Delorie <dj at redhat dot com>
- To: binutils at sourceware dot org
- Date: Tue, 13 Dec 2005 22:29:24 -0500
- Subject: [m32c] cpu tweaks: jsri, index*
* m32c.cpu (jsri): Fix order so register names aren't treated as
symbols.
(indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
indexwd, indexws): Fix encodings.
* m32c-desc.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
Index: cpu/m32c.cpu
===================================================================
RCS file: /cvs/src/src/cpu/m32c.cpu,v
retrieving revision 1.7
diff -p -U3 -r1.7 cpu/m32c.cpu
--- cpu/m32c.cpu 27 Oct 2005 23:54:17 -0000 1.7
+++ cpu/m32c.cpu 14 Dec 2005 03:27:25 -0000
@@ -7979,33 +7979,36 @@
(define-pmacro (indexls-sem mode d)
(set SrcIndex (sll d (const 2))) (set DstIndex (const 0)))
+; Note that "wbit" not where the size bit goes here, hence, it's
+; always 0 in these calls but op2 differs instead.
+
; indexb src (index byte)
(unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem)
-(unary32-defn HI .w 1 indexb #x8 1 #x3 indexb-sem)
+(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem)
; indexbd src (index byte dest)
(unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem)
-(unary32-defn HI .w 1 indexbd #xA 1 3 indexbd-sem)
+(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem)
; indexbs src (index byte src)
(unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem)
-(unary32-defn HI .w 1 indexbs #xC 1 3 indexbs-sem)
+(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem)
; indexl src (index long)
(unary32-defn QI .b 0 indexl 9 2 3 indexl-sem)
-(unary32-defn HI .w 1 indexl 9 3 3 indexl-sem)
+(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem)
; indexld src (index long dest)
(unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem)
-(unary32-defn HI .w 1 indexld #xB 3 3 indexld-sem)
+(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem)
; indexls src (index long src)
(unary32-defn QI .b 0 indexls 9 0 3 indexls-sem)
-(unary32-defn HI .w 1 indexls 9 1 3 indexls-sem)
+(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem)
; indexw src (index word)
(unary32-defn QI .b 0 indexw 8 2 3 indexw-sem)
-(unary32-defn HI .w 1 indexw 8 3 3 indexw-sem)
+(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem)
; indexwd src (index word dest)
(unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem)
-(unary32-defn HI .w 1 indexwd #xA 3 3 indexwd-sem)
+(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem)
; indexws (index word src)
(unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem)
-(unary32-defn HI .w 1 indexws #xC 3 3 indexws-sem)
+(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem)
;-------------------------------------------------------------
; jcc - jump on condition
@@ -8218,12 +8221,12 @@
)
)
; jsri.w dst (m16 #1 m32 #1))
-(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
- dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2)
(jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3)
(jsri-defn w dst16-16-16-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
dst32-16-16-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4)
+(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
+ dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2)
(dni jsri32.w "jsr.w dst32-16-24-Unprefixed-HI" ((machine 32))
("jsri.w ${dst32-16-24-Unprefixed-HI}")
(+ (f-0-4 #xC) (f-7-1 1) dst32-16-24-Unprefixed-HI (f-10-2 #x1) (f-12-4 #xF))
@@ -8231,12 +8234,13 @@
())
; jsri.a (m16 #2 m32 #2)
-(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
- dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2)
(jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3)
(jsri-defn a dst16-16-16-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
dst32-16-16-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4)
+(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
+ dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2)
+
(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" ((machine 32))
("jsri.w ${dst32-16-24-Unprefixed-SI}")
(+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1))
Index: opcodes/m32c-desc.c
===================================================================
RCS file: /cvs/src/src/opcodes/m32c-desc.c,v
retrieving revision 1.8
diff -p -U3 -r1.8 opcodes/m32c-desc.c
--- opcodes/m32c-desc.c 8 Nov 2005 16:16:47 -0000 1.8
+++ opcodes/m32c-desc.c 14 Dec 2005 03:27:27 -0000
@@ -34340,6 +34340,36 @@ static const CGEN_IBASE m32c_cgen_insn_t
M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.w", 40,
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jsri.a $Dst32RnUnprefixedSI */
+ {
+ M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "jsri.a", 16,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsri.a $Dst32AnUnprefixedSI */
+ {
+ M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "jsri.a", 16,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsri.a [$Dst32AnUnprefixed] */
+ {
+ M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "jsri.a", 16,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsri.a $Dst16RnSI */
+ {
+ M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-Rn-direct-SI", "jsri.a", 16,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsri.a $Dst16AnSI */
+ {
+ M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-direct-SI", "jsri.a", 16,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsri.a [$Dst16An] */
+ {
+ M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "jsri.a", 32,
@@ -34405,45 +34435,45 @@ static const CGEN_IBASE m32c_cgen_insn_t
M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-FB-relative-SI", "jsri.a", 24,
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
-/* jsri.a $Dst32RnUnprefixedSI */
+/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
- M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "jsri.a", 16,
+ M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
-/* jsri.a $Dst32AnUnprefixedSI */
+/* jsri.w ${Dsp-16-u24} */
{
- M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "jsri.a", 16,
+ M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
-/* jsri.a [$Dst32AnUnprefixed] */
+/* jsri.w $Dst32RnUnprefixedHI */
{
- M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "jsri.a", 16,
+ M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16,
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
-/* jsri.a $Dst16RnSI */
+/* jsri.w $Dst32AnUnprefixedHI */
{
- M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-Rn-direct-SI", "jsri.a", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "jsri.w", 16,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
-/* jsri.a $Dst16AnSI */
+/* jsri.w [$Dst32AnUnprefixed] */
{
- M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-direct-SI", "jsri.a", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "jsri.w", 16,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
-/* jsri.a [$Dst16An] */
+/* jsri.w $Dst16RnHI */
{
- M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16,
+ M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-Rn-direct-HI", "jsri.w", 16,
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
-/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* jsri.w $Dst16AnHI */
{
- M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-direct-HI", "jsri.w", 16,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
-/* jsri.w ${Dsp-16-u24} */
+/* jsri.w [$Dst16An] */
{
- M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
@@ -34510,36 +34540,6 @@ static const CGEN_IBASE m32c_cgen_insn_t
M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24,
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
-/* jsri.w $Dst32RnUnprefixedHI */
- {
- M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
- },
-/* jsri.w $Dst32AnUnprefixedHI */
- {
- M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "jsri.w", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
- },
-/* jsri.w [$Dst32AnUnprefixed] */
- {
- M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "jsri.w", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
- },
-/* jsri.w $Dst16RnHI */
- {
- M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-Rn-direct-HI", "jsri.w", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
- },
-/* jsri.w $Dst16AnHI */
- {
- M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-direct-HI", "jsri.w", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
- },
-/* jsri.w [$Dst16An] */
- {
- M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
- },
/* jmpi.a $Dst32RnUnprefixedSI */
{
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "jmpi.a", 16,
Index: opcodes/m32c-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/m32c-opc.c,v
retrieving revision 1.7
diff -p -U3 -r1.7 opcodes/m32c-opc.c
--- opcodes/m32c-opc.c 28 Oct 2005 19:49:21 -0000 1.7
+++ opcodes/m32c-opc.c 14 Dec 2005 03:27:29 -0000
@@ -6985,6 +6985,18 @@ static const CGEN_IFMT ifmt_stc16_src_ds
32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
};
+static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI ATTRIBUTE_UNUSED = {
+ 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI ATTRIBUTE_UNUSED = {
+ 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI ATTRIBUTE_UNUSED = {
+ 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
+};
+
static const CGEN_IFMT ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_An_relative_SI ATTRIBUTE_UNUSED = {
32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
};
@@ -7009,18 +7021,6 @@ static const CGEN_IFMT ifmt_jsri16a_dst1
24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
};
-static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI ATTRIBUTE_UNUSED = {
- 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI ATTRIBUTE_UNUSED = {
- 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI ATTRIBUTE_UNUSED = {
- 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
-};
-
static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
};
@@ -45884,6 +45884,42 @@ static const CGEN_OPCODE m32c_cgen_insn_
{ { MNEM, ' ', OP (DSP_16_U24), 0 } },
& ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x96810000 }
},
+/* jsri.a $Dst32RnUnprefixedSI */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
+ & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x9801 }
+ },
+/* jsri.a $Dst32AnUnprefixedSI */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
+ & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x9081 }
+ },
+/* jsri.a [$Dst32AnUnprefixed] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+ & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x9001 }
+ },
+/* jsri.a $Dst16RnSI */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DST16RNSI), 0 } },
+ & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d10 }
+ },
+/* jsri.a $Dst16AnSI */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DST16ANSI), 0 } },
+ & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d14 }
+ },
+/* jsri.a [$Dst16An] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
+ & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d16 }
+ },
/* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
@@ -45962,53 +45998,53 @@ static const CGEN_OPCODE m32c_cgen_insn_
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
& ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d1b00 }
},
-/* jsri.a $Dst32RnUnprefixedSI */
+/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
- & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x9801 }
+ { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+ & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc71f0000 }
},
-/* jsri.a $Dst32AnUnprefixedSI */
+/* jsri.w ${Dsp-16-u24} */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
- & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x9081 }
+ { { MNEM, ' ', OP (DSP_16_U24), 0 } },
+ & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc79f0000 }
},
-/* jsri.a [$Dst32AnUnprefixed] */
+/* jsri.w $Dst32RnUnprefixedHI */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x9001 }
+ { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
+ & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc91f }
},
-/* jsri.a $Dst16RnSI */
+/* jsri.w $Dst32AnUnprefixedHI */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DST16RNSI), 0 } },
- & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d10 }
+ { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
+ & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc19f }
},
-/* jsri.a $Dst16AnSI */
+/* jsri.w [$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DST16ANSI), 0 } },
- & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d14 }
+ { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+ & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc11f }
},
-/* jsri.a [$Dst16An] */
+/* jsri.w $Dst16RnHI */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
- & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d16 }
+ { { MNEM, ' ', OP (DST16RNHI), 0 } },
+ & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d30 }
},
-/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* jsri.w $Dst16AnHI */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc71f0000 }
+ { { MNEM, ' ', OP (DST16ANHI), 0 } },
+ & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d34 }
},
-/* jsri.w ${Dsp-16-u24} */
+/* jsri.w [$Dst16An] */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSP_16_U24), 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc79f0000 }
+ { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
+ & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d36 }
},
/* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
@@ -46088,42 +46124,6 @@ static const CGEN_OPCODE m32c_cgen_insn_
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
& ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d3b00 }
},
-/* jsri.w $Dst32RnUnprefixedHI */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
- & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc91f }
- },
-/* jsri.w $Dst32AnUnprefixedHI */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
- & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc19f }
- },
-/* jsri.w [$Dst32AnUnprefixed] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc11f }
- },
-/* jsri.w $Dst16RnHI */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DST16RNHI), 0 } },
- & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d30 }
- },
-/* jsri.w $Dst16AnHI */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DST16ANHI), 0 } },
- & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d34 }
- },
-/* jsri.w [$Dst16An] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
- & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d36 }
- },
/* jmpi.a $Dst32RnUnprefixedSI */
{
{ 0, 0, 0, 0 },
@@ -46380,73 +46380,73 @@ static const CGEN_OPCODE m32c_cgen_insn_
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
- & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc933 }
+ & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc833 }
},
/* indexws.w $Dst32AnUnprefixedHI */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
- & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1b3 }
+ & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc0b3 }
},
/* indexws.w [$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc133 }
+ & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc033 }
},
/* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc33300 }
+ & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc23300 }
},
/* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5330000 }
+ & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4330000 }
},
/* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7330000 }
+ & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6330000 }
},
/* indexws.w ${Dsp-16-u8}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3b300 }
+ & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc2b300 }
},
/* indexws.w ${Dsp-16-u16}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5b30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4b30000 }
},
/* indexws.w ${Dsp-16-s8}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3f300 }
+ & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2f300 }
},
/* indexws.w ${Dsp-16-s16}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5f30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4f30000 }
},
/* indexws.w ${Dsp-16-u16} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7f30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6f30000 }
},
/* indexws.w ${Dsp-16-u24} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7b30000 }
+ & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6b30000 }
},
/* indexws.b $Dst32RnUnprefixedQI */
{
@@ -46524,73 +46524,73 @@ static const CGEN_OPCODE m32c_cgen_insn_
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
- & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa933 }
+ & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa833 }
},
/* indexwd.w $Dst32AnUnprefixedHI */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
- & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1b3 }
+ & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa0b3 }
},
/* indexwd.w [$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa133 }
+ & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa033 }
},
/* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33300 }
+ & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa23300 }
},
/* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa5330000 }
+ & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4330000 }
},
/* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa7330000 }
+ & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6330000 }
},
/* indexwd.w ${Dsp-16-u8}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3b300 }
+ & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa2b300 }
},
/* indexwd.w ${Dsp-16-u16}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5b30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4b30000 }
},
/* indexwd.w ${Dsp-16-s8}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3f300 }
+ & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2f300 }
},
/* indexwd.w ${Dsp-16-s16}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5f30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4f30000 }
},
/* indexwd.w ${Dsp-16-u16} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7f30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6f30000 }
},
/* indexwd.w ${Dsp-16-u24} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7b30000 }
+ & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6b30000 }
},
/* indexwd.b $Dst32RnUnprefixedQI */
{
@@ -46668,73 +46668,73 @@ static const CGEN_OPCODE m32c_cgen_insn_
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
- & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8933 }
+ & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8833 }
},
/* indexw.w $Dst32AnUnprefixedHI */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
- & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x81b3 }
+ & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x80b3 }
},
/* indexw.w [$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8133 }
+ & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8033 }
},
/* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x833300 }
+ & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x823300 }
},
/* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x85330000 }
+ & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84330000 }
},
/* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x87330000 }
+ & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86330000 }
},
/* indexw.w ${Dsp-16-u8}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83b300 }
+ & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x82b300 }
},
/* indexw.w ${Dsp-16-u16}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85b30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84b30000 }
},
/* indexw.w ${Dsp-16-s8}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83f300 }
+ & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82f300 }
},
/* indexw.w ${Dsp-16-s16}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85f30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84f30000 }
},
/* indexw.w ${Dsp-16-u16} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87f30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86f30000 }
},
/* indexw.w ${Dsp-16-u24} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x87b30000 }
+ & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86b30000 }
},
/* indexw.b $Dst32RnUnprefixedQI */
{
@@ -46812,73 +46812,73 @@ static const CGEN_OPCODE m32c_cgen_insn_
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
- & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9913 }
+ & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9813 }
},
/* indexls.w $Dst32AnUnprefixedHI */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
- & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9193 }
+ & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9093 }
},
/* indexls.w [$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9113 }
+ & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9013 }
},
/* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x931300 }
+ & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x921300 }
},
/* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x95130000 }
+ & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94130000 }
},
/* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x97130000 }
+ & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96130000 }
},
/* indexls.w ${Dsp-16-u8}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939300 }
+ & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x929300 }
},
/* indexls.w ${Dsp-16-u16}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95930000 }
+ & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94930000 }
},
/* indexls.w ${Dsp-16-s8}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93d300 }
+ & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92d300 }
},
/* indexls.w ${Dsp-16-s16}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95d30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94d30000 }
},
/* indexls.w ${Dsp-16-u16} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97d30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96d30000 }
},
/* indexls.w ${Dsp-16-u24} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x97930000 }
+ & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96930000 }
},
/* indexls.b $Dst32RnUnprefixedQI */
{
@@ -46956,73 +46956,73 @@ static const CGEN_OPCODE m32c_cgen_insn_
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
- & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb933 }
+ & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb833 }
},
/* indexld.w $Dst32AnUnprefixedHI */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
- & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1b3 }
+ & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb0b3 }
},
/* indexld.w [$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb133 }
+ & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb033 }
},
/* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb33300 }
+ & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb23300 }
},
/* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb5330000 }
+ & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb4330000 }
},
/* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb7330000 }
+ & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb6330000 }
},
/* indexld.w ${Dsp-16-u8}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3b300 }
+ & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb2b300 }
},
/* indexld.w ${Dsp-16-u16}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5b30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb4b30000 }
},
/* indexld.w ${Dsp-16-s8}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3f300 }
+ & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb2f300 }
},
/* indexld.w ${Dsp-16-s16}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5f30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb4f30000 }
},
/* indexld.w ${Dsp-16-u16} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7f30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb6f30000 }
},
/* indexld.w ${Dsp-16-u24} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7b30000 }
+ & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb6b30000 }
},
/* indexld.b $Dst32RnUnprefixedQI */
{
@@ -47100,73 +47100,73 @@ static const CGEN_OPCODE m32c_cgen_insn_
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
- & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9933 }
+ & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9833 }
},
/* indexl.w $Dst32AnUnprefixedHI */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
- & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x91b3 }
+ & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x90b3 }
},
/* indexl.w [$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9133 }
+ & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9033 }
},
/* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x933300 }
+ & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x923300 }
},
/* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x95330000 }
+ & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94330000 }
},
/* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x97330000 }
+ & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96330000 }
},
/* indexl.w ${Dsp-16-u8}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93b300 }
+ & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x92b300 }
},
/* indexl.w ${Dsp-16-u16}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95b30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94b30000 }
},
/* indexl.w ${Dsp-16-s8}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93f300 }
+ & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92f300 }
},
/* indexl.w ${Dsp-16-s16}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95f30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94f30000 }
},
/* indexl.w ${Dsp-16-u16} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97f30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96f30000 }
},
/* indexl.w ${Dsp-16-u24} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x97b30000 }
+ & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96b30000 }
},
/* indexl.b $Dst32RnUnprefixedQI */
{
@@ -47244,73 +47244,73 @@ static const CGEN_OPCODE m32c_cgen_insn_
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
- & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc913 }
+ & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc813 }
},
/* indexbs.w $Dst32AnUnprefixedHI */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
- & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc193 }
+ & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc093 }
},
/* indexbs.w [$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc113 }
+ & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc013 }
},
/* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31300 }
+ & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc21300 }
},
/* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5130000 }
+ & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4130000 }
},
/* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7130000 }
+ & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6130000 }
},
/* indexbs.w ${Dsp-16-u8}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39300 }
+ & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc29300 }
},
/* indexbs.w ${Dsp-16-u16}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5930000 }
+ & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4930000 }
},
/* indexbs.w ${Dsp-16-s8}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3d300 }
+ & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2d300 }
},
/* indexbs.w ${Dsp-16-s16}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5d30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4d30000 }
},
/* indexbs.w ${Dsp-16-u16} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7d30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6d30000 }
},
/* indexbs.w ${Dsp-16-u24} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7930000 }
+ & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6930000 }
},
/* indexbs.b $Dst32RnUnprefixedQI */
{
@@ -47388,73 +47388,73 @@ static const CGEN_OPCODE m32c_cgen_insn_
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
- & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa913 }
+ & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa813 }
},
/* indexbd.w $Dst32AnUnprefixedHI */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
- & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa193 }
+ & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa093 }
},
/* indexbd.w [$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa113 }
+ & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa013 }
},
/* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31300 }
+ & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa21300 }
},
/* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa5130000 }
+ & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4130000 }
},
/* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa7130000 }
+ & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6130000 }
},
/* indexbd.w ${Dsp-16-u8}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39300 }
+ & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa29300 }
},
/* indexbd.w ${Dsp-16-u16}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5930000 }
+ & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4930000 }
},
/* indexbd.w ${Dsp-16-s8}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3d300 }
+ & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2d300 }
},
/* indexbd.w ${Dsp-16-s16}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5d30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4d30000 }
},
/* indexbd.w ${Dsp-16-u16} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7d30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6d30000 }
},
/* indexbd.w ${Dsp-16-u24} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7930000 }
+ & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6930000 }
},
/* indexbd.b $Dst32RnUnprefixedQI */
{
@@ -47532,73 +47532,73 @@ static const CGEN_OPCODE m32c_cgen_insn_
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
- & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8913 }
+ & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8813 }
},
/* indexb.w $Dst32AnUnprefixedHI */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
- & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8193 }
+ & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8093 }
},
/* indexb.w [$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8113 }
+ & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8013 }
},
/* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x831300 }
+ & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x821300 }
},
/* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x85130000 }
+ & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84130000 }
},
/* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x87130000 }
+ & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86130000 }
},
/* indexb.w ${Dsp-16-u8}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839300 }
+ & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x829300 }
},
/* indexb.w ${Dsp-16-u16}[sb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85930000 }
+ & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84930000 }
},
/* indexb.w ${Dsp-16-s8}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83d300 }
+ & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82d300 }
},
/* indexb.w ${Dsp-16-s16}[fb] */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85d30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84d30000 }
},
/* indexb.w ${Dsp-16-u16} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U16), 0 } },
- & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87d30000 }
+ & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86d30000 }
},
/* indexb.w ${Dsp-16-u24} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSP_16_U24), 0 } },
- & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x87930000 }
+ & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86930000 }
},
/* indexb.b $Dst32RnUnprefixedQI */
{
Index: opcodes/m32c-opc.h
===================================================================
RCS file: /cvs/src/src/opcodes/m32c-opc.h,v
retrieving revision 1.6
diff -p -U3 -r1.6 opcodes/m32c-opc.h
--- opcodes/m32c-opc.h 27 Oct 2005 23:54:17 -0000 1.6
+++ opcodes/m32c-opc.h 14 Dec 2005 03:27:29 -0000
@@ -1629,17 +1629,17 @@ typedef enum cgen_insn_type {
, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI
, M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI
, M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI
- , M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI
- , M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI
- , M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI
+ , M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI
+ , M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI
+ , M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI
, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI