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MIPS R5900 support => Disabling a few I2 instructions
- From: Doug Evans <dje at transmeta dot com>
- To: Ed Schouten <ed at fxq dot nl>
- Cc: Binutils Hackers <binutils at sourceware dot org>
- Date: Sun, 1 May 2005 14:06:43 -0700 (PDT)
- Subject: MIPS R5900 support => Disabling a few I2 instructions
- References: <20050430212229.GD30486@fxq.nl>
Ed Schouten writes:
> Hi everyone,
>
> The last couple of weeks I've been working on Binutils from CVS to
> support the Toshiba R5900 CPU (found in Sony's Playstation 2).
>
> The Toshiba R5900 supports the following instructions:
> - It implements almost all MIPS3 instructions, though it supports
> MIPS4's movn/movz.
> - It has a lot of instructions which allow you to do 128 bits register
> manipulations (vector rotations, etc)
> - It *doesn't* support load linked and store conditional instructions
> (ll/lld/sc/scd, MIPS2).
>
> That's why I chose to define it as a MIPS3 CPU.
>
> When I look in opcodes/mips-opc.c, I see a lot of ways to add
> instructions to a certain CPU, but I can't find a way to just disable
> ll/lld/sc/scd (I can't just say I2&!T59 or something).
>
> What would be the best way to disable ll/lld/sc/scd *only* on the MIPS
> R5900?
I'm confused by "That's why I chose to define it as a MIPS3 CPU."
That suggests all of Cygnus's work circa 1998/1999 didn't get
folded back into the FSF tree. I know the dvp stuff didn't get
folded back :-(, but the mips stuff too?