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Thumb32 assembler (50/69)
- From: Zack Weinberg <zack at codesourcery dot com>
- To: binutils <binutils at sourceware dot org>
- Date: Tue, 26 Apr 2005 02:56:59 -0700
- Subject: Thumb32 assembler (50/69)
I've been leading up to this patch for a long time. It removes the
call to parse_operands from all the encoder functions; they are now
responsible only for encoding the instruction with the information
from the operands array. The operand-parse vectors move into insns
and tinsns.
This renders a bunch of wrapper functions unnecessary.
zw
* config/tc-arm.c (struct asm_opcodes): Add operands field.
Rename parms to encode and remove its argument.
(parse_operands): Skip whitespace before entering loop.
(md_assemble): Call parse_operands here, then opcode->encode.
(CE, CM, UE, UF, TI): Add nops and ops arguments.
(insns): Specify instruction operands here.
Use mlas for mla, mls.
(do_mlas): Look at inst.instruction to determine whether this is mls.
(do_mav_binops_1, do_mav_binops_2, do_mav_triple_1, do_mav_triple_2)
New encoding functions for Maverick instructions, which take no
arguments.
(do_mav_quad): Hardwire register offsets.
(do_mav_dspsc_2): Rename do_mav_dspsc_0.
(all functions called from insns and tinsns):
Do not call parse_operands. Take no arguments.
(MAV_MODE1, MAV_MODE2, MAVE_MODE3, MAV_MODE4, MAV_MODE5, MAV_MODE6)
(do_mla, do_mls, do_mav_binops, do_mav_triple, do_mav_binops_1a)
(do_mav_binops_1b, do_mav_binops_1c, do_mav_binops_1d)
(do_mav_binops_1e, do_mav_binops_1f, do_mav_binops_1g)
(do_mav_binops_1h, do_mav_binops_1i, do_mav_binops_1j)
(do_mav_binops_1k, do_mav_binops_1l, do_mav_binops_1m)
(do_mav_binops_1n, do_mav_binops_1o, do_mav_binops_2a)
(do_mav_binops_2b, do_mav_binops_2c, do_mav_binops_3a)
(do_mav_binops_3b, do_mav_binops_3c, do_mav_binops_3d)
(do_mav_triple_4a, do_mav_triple_4b, do_mav_triple_5a)
(do_mav_triple_5b, do_mav_triple_5c, do_mav_binops_5d)
(do_mav_triple_5e, do_mav_triple_5f, do_mav_binops_5g)
(do_mav_triple_5h, do_mav_quad_6a, do_mav_quad_6b)
(do_mav_shift_1, do_mav_shift_2, do_mav_ldst_1, do_mav_ldst_2)
(do_mav_ldst_3, do_mav_ldst_4): Delete.
===================================================================
Index: gas/config/tc-arm.c
--- gas/config/tc-arm.c (revision 52)
+++ gas/config/tc-arm.c (revision 53)
@@ -350,24 +350,6 @@
take 2: */
#define INSN_SIZE 4
-/* "INSN<cond> X,Y" where X:bit12, Y:bit16. */
-#define MAV_MODE1 0x100c
-
-/* "INSN<cond> X,Y" where X:bit16, Y:bit12. */
-#define MAV_MODE2 0x0c10
-
-/* "INSN<cond> X,Y" where X:bit12, Y:bit16. */
-#define MAV_MODE3 0x100c
-
-/* "INSN<cond> X,Y,Z" where X:16, Y:0, Z:12. */
-#define MAV_MODE4 0x0c0010
-
-/* "INSN<cond> X,Y,Z" where X:12, Y:16, Z:0. */
-#define MAV_MODE5 0x00100c
-
-/* "INSN<cond> W,X,Y,Z" where W:5, X:12, Y:16, Z:0. */
-#define MAV_MODE6 0x00100c05
-
struct asm_opcode
{
/* Basic string to match. */
@@ -379,8 +361,11 @@
/* Which architecture variant provides this instruction. */
unsigned long variant;
- /* Function to call to parse args. */
- void (* parms) (char *);
+ /* Parameters to instruction. */
+ const char *operands;
+
+ /* Function to call to encode instruction. */
+ void (* encode) (void);
};
/* Defines for various bits that we will want to toggle. */
@@ -3912,6 +3897,8 @@
inst.operands[i].imm = val; \
} while (0)
+ skip_whitespace (str);
+
/* Check for a no-operand instruction, or an instruction with only
optional operands given none, and bypass the loop if so. */
if (*p == OP_(stop) || ((*p & 0200) && *str == 0))
@@ -4235,9 +4222,8 @@
/* Functions for instruction parsing, sorted by subarchitecture. */
static void
-do_empty (char * str)
+do_empty (void)
{
- parse_operands (str, OPERANDS0());
}
/* ARM instructions, in alphabetical order by function name (except
@@ -4248,11 +4234,8 @@
into a relative address of the form "add rd, pc, #label-.-8". */
static void
-do_adr (char * str)
+do_adr (void)
{
- if (parse_operands (str, OPERANDS2(RR,EXP)) == FAIL)
- return;
-
inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
/* Frag hacking will turn this into a sub instruction if the offset turns
@@ -4270,11 +4253,8 @@
add rd, rd, #high(label-.-8)" */
static void
-do_adrl (char * str)
+do_adrl (void)
{
- if (parse_operands (str, OPERANDS2(RR,EXP)) == FAIL)
- return;
-
inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
/* Frag hacking will turn this into a sub instruction if the offset turns
@@ -4288,23 +4268,17 @@
}
static void
-do_arit (char * str)
+do_arit (void)
{
- if (parse_operands (str, OPERANDS3(RR,RR,SHOP)))
- return;
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg << 16;
encode_shifter_operand_arm (2);
}
static void
-do_bfc (char *str)
+do_bfc (void)
{
- unsigned int msb;
- if (parse_operands (str, OPERANDS3(RRnpc,I31,I32)))
- return;
-
- msb = inst.operands[1].imm + inst.operands[2].imm;
+ unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
if (msb > 32)
{
inst.error = _("bit-field extends past end of register");
@@ -4319,11 +4293,9 @@
}
static void
-do_bfi (char *str)
+do_bfi (void)
{
unsigned int msb;
- if (parse_operands (str, OPERANDS4(RRnpc,RRnpc_I0,I31,I32)))
- return;
/* #0 in second position is alternative syntax for bfc, which is
the same instruction but with REG_PC in the Rm field. */
@@ -4346,11 +4318,8 @@
}
static void
-do_bfx (char *str)
+do_bfx (void)
{
- if (parse_operands (str, OPERANDS4(RR,RR,I31,I32)))
- return;
-
if (inst.operands[2].imm + inst.operands[3].imm > 32)
{
inst.error = _("bit-field extends past end of register");
@@ -4370,13 +4339,8 @@
and it is an error if the caller tried to override that. */
static void
-do_bkpt (char * str)
+do_bkpt (void)
{
- /* As a convenience, we allow BKPT with no immediate (corresponding
- to BKPT #0). */
- if (parse_operands (str, OPERANDS1(obIffff)))
- return;
-
/* Top 12 of 16 bits to bits 19:8. */
inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
@@ -4405,11 +4369,8 @@
}
static void
-do_branch (char * str)
+do_branch (void)
{
- if (parse_operands (str, OPERANDS1(EXPr)))
- return;
-
encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
}
@@ -4422,11 +4383,8 @@
Also, the <target_addr> can be 25 bits, hence has its own reloc. */
static void
-do_blx (char * str)
+do_blx (void)
{
- if (parse_operands (str, OPERANDS1(RR_EXr)))
- return;
-
if (inst.operands[0].isreg)
{
/* Arg is a register; the opcode provided by insns[] is correct.
@@ -4451,11 +4409,8 @@
}
static void
-do_bx (char * str)
+do_bx (void)
{
- if (parse_operands (str, OPERANDS1(RR)) == FAIL)
- return;
-
if (inst.operands[0].reg == REG_PC)
as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
@@ -4466,11 +4421,8 @@
/* ARM v5TEJ. Jump to Jazelle code. */
static void
-do_bxj (char * str)
+do_bxj (void)
{
- if (parse_operands (str, OPERANDS1(RR)) == FAIL)
- return;
-
if (inst.operands[0].reg == REG_PC)
as_tsktsk (_("use of r15 in bxj is not really useful"));
@@ -4481,11 +4433,8 @@
CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
static void
-do_cdp (char * str)
+do_cdp (void)
{
- if (parse_operands (str, OPERANDS6(RCP,bI15,RCN,RCN,RCN,obI7)))
- return;
-
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].imm << 20;
inst.instruction |= inst.operands[2].reg << 12;
@@ -4500,20 +4449,15 @@
Error if Rd or Rm are R15. */
static void
-do_clz (char * str)
+do_clz (void)
{
- if (parse_operands (str, OPERANDS2(RRnpc,RRnpc)) == FAIL)
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 0);
}
static void
-do_cmp (char * str)
+do_cmp (void)
{
- if (parse_operands (str, OPERANDS2(RR,SHOP)))
- return;
inst.instruction |= inst.operands[0].reg << 16;
encode_shifter_operand_arm (1);
}
@@ -4527,11 +4471,8 @@
No special properties. */
static void
-do_co_reg (char * str)
+do_co_reg (void)
{
- if (parse_operands (str, OPERANDS6(RCP,bI7,RR,RCN,RCN,obI7)))
- return;
-
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].imm << 21;
inst.instruction |= inst.operands[2].reg << 12;
@@ -4554,11 +4495,8 @@
Result unpredicatable if Rd or Rn is R15. */
static void
-do_co_reg2c (char * str)
+do_co_reg2c (void)
{
- if (parse_operands (str, OPERANDS5(RCP,bI15,RRnpc,RRnpc,RCN)))
- return;
-
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].imm << 4;
inst.instruction |= inst.operands[2].reg << 12;
@@ -4570,34 +4508,24 @@
CPS, CPSIE, CSPID . */
static void
-do_cps (char * str)
+do_cps (void)
{
- if (parse_operands (str, OPERANDS1(bI31)))
- return;
inst.instruction |= inst.operands[0].imm;
}
static void
-do_cpsi (char * str)
+do_cpsi (void)
{
- if (parse_operands (str, OPERANDS2(CPSF,obI31)))
- return;
-
inst.instruction |= inst.operands[0].imm << 6;
inst.instruction |= inst.operands[1].imm;
}
static void
-do_ldmstm (char * str)
+do_ldmstm (void)
{
- int base_reg;
- int range;
- if (parse_operands (str, OPERANDS2(RRw,REGLST)))
- return;
+ int base_reg = inst.operands[0].reg;
+ int range = inst.operands[1].imm;
- base_reg = inst.operands[0].reg;
- range = inst.operands[1].imm;
-
inst.instruction |= base_reg << 16;
inst.instruction |= range;
@@ -4638,11 +4566,8 @@
STRccD R, mode. */
static void
-do_ldrd (char * str)
+do_ldrd (void)
{
- if (parse_operands (str, OPERANDS2(RR,ADDR)))
- return;
-
if (!inst.operands[1].isreg)
{
inst.error = _("'[' expected");
@@ -4690,21 +4615,15 @@
See ARMARMv6 A4.1.27: LDREX. */
static void
-do_ldrex (char * str)
+do_ldrex (void)
{
- if (parse_operands (str, OPERANDS2(RRnpc,bRRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
}
static void
-do_ldst (char * str)
+do_ldst (void)
{
- if (parse_operands (str, OPERANDS2(RR,ADDR)))
- return;
-
inst.instruction |= inst.operands[0].reg << 12;
if (!inst.operands[1].isreg)
if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
@@ -4713,11 +4632,8 @@
}
static void
-do_ldstt (char * str)
+do_ldstt (void)
{
- if (parse_operands (str, OPERANDS2(RR,ADDR)))
- return;
-
/* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
reject [Rn,...]. */
if (inst.operands[1].preind)
@@ -4741,11 +4657,8 @@
/* Halfword and signed-byte load/store operations. */
static void
-do_ldstv4 (char * str)
+do_ldstv4 (void)
{
- if (parse_operands (str, OPERANDS2(RR,ADDR)))
- return;
-
inst.instruction |= inst.operands[0].reg << 12;
if (!inst.operands[1].isreg)
if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
@@ -4754,11 +4667,8 @@
}
static void
-do_ldsttv4 (char * str)
+do_ldsttv4 (void)
{
- if (parse_operands (str, OPERANDS2(RR,ADDR)))
- return;
-
/* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
reject [Rn,...]. */
if (inst.operands[1].preind)
@@ -4782,62 +4692,40 @@
/* Co-processor register load/store.
Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
static void
-do_lstc (char * str)
+do_lstc (void)
{
- if (parse_operands (str, OPERANDS3(RCP,RCN,ADDR)))
- return;
-
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].reg << 12;
encode_cp_address_arm (2, TRUE, TRUE, 0);
}
static void
-do_mlas (char * str, bfd_boolean is_mls)
+do_mlas (void)
{
- if (parse_operands (str, OPERANDS4(RRnpc,RRnpc,RRnpc,RRnpc)))
- return;
+ /* This restriction does not apply to mls (nor to mla in v6, but
+ that's hard to detect at present). */
+ if (inst.operands[0].reg == inst.operands[1].reg
+ && !(inst.instruction & 0x00400000))
+ as_tsktsk (_("rd and rm should be different in mla"));
inst.instruction |= (inst.operands[0].reg << 16);
inst.instruction |= (inst.operands[1].reg << 0);
inst.instruction |= (inst.operands[2].reg << 8);
inst.instruction |= (inst.operands[3].reg << 12);
- /* This restriction does not apply to mls (nor to mla in v6, but
- that's hard to detect at present). */
- if (inst.operands[0].reg == inst.operands[1].reg && !is_mls)
- as_tsktsk (_("rd and rm should be different in mla"));
}
static void
-do_mla (char *str)
+do_mov (void)
{
- do_mlas (str, FALSE);
-}
-
-static void
-do_mls (char *str)
-{
- do_mlas (str, TRUE);
-}
-
-static void
-do_mov (char * str)
-{
- if (parse_operands (str, OPERANDS2(RR,SHOP)))
- return;
-
inst.instruction |= inst.operands[0].reg << 12;
encode_shifter_operand_arm (1);
}
/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
static void
-do_mov16 (char *str)
+do_mov16 (void)
{
- if (parse_operands (str, OPERANDS2(RRnpc,Iffff)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
/* The value is in two pieces: 0:11, 16:19. */
inst.instruction |= (inst.operands[1].imm & 0x00000fff);
@@ -4845,11 +4733,8 @@
}
static void
-do_mrs (char * str)
+do_mrs (void)
{
- if (parse_operands (str, OPERANDS2(RR,PSR)))
- return;
-
/* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
if ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) != (PSR_c|PSR_f))
{
@@ -4866,11 +4751,8 @@
"{C|S}PSR_f, #expression". */
static void
-do_msr (char * str)
+do_msr (void)
{
- if (parse_operands (str, OPERANDS2(PSR,RR_iEX)))
- return;
-
inst.instruction |= inst.operands[0].imm;
if (inst.operands[1].isreg)
inst.instruction |= inst.operands[1].reg;
@@ -4883,11 +4765,8 @@
}
static void
-do_mul (char * str)
+do_mul (void)
{
- if (parse_operands (str, OPERANDS3(RRnpc,RRnpc,RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 16);
inst.instruction |= (inst.operands[1].reg << 0);
inst.instruction |= (inst.operands[2].reg << 8);
@@ -4903,11 +4782,8 @@
SMLAL RdLo, RdHi, Rm, Rs. */
static void
-do_mull (char * str)
+do_mull (void)
{
- if (parse_operands (str, OPERANDS4(RRnpc,RRnpc,RRnpc,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= (inst.operands[2].reg << 0);
@@ -4921,11 +4797,8 @@
}
static void
-do_nop (char * str)
+do_nop (void)
{
- if (parse_operands (str, OPERANDS1(ocI255)))
- return;
-
if (inst.operands[0].present)
{
/* Architectural NOP hints are CPSR sets with no bits selected. */
@@ -4940,10 +4813,8 @@
Error if Rd, Rn or Rm are R15. */
static void
-do_pkhbt (char * str)
+do_pkhbt (void)
{
- if (parse_operands (str, OPERANDS4(RRnpc,RRnpc,RRnpc,oSHll)))
- return;
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg << 16;
inst.instruction |= inst.operands[2].reg << 0;
@@ -4954,11 +4825,8 @@
/* ARM V6 PKHTB (Argument Parse). */
static void
-do_pkhtb (char * str)
+do_pkhtb (void)
{
- if (parse_operands (str, OPERANDS4(RRnpc,RRnpc,RRnpc,oSHar)))
- return;
-
if (!inst.operands[3].present)
{
/* If the shift specifier is omitted, turn the instruction
@@ -4984,11 +4852,8 @@
Syntactically, like LDR with B=1, W=0, L=1. */
static void
-do_pld (char * str)
+do_pld (void)
{
- if (parse_operands (str, OPERANDS1(ADDR)))
- return;
-
if (!inst.operands[0].isreg)
{
inst.error = _("'[' expected after PLD mnemonic");
@@ -5019,11 +4884,8 @@
Error if any register is R15. */
static void
-do_qadd (char * str)
+do_qadd (void)
{
- if (parse_operands (str, OPERANDS3(RRnpc,RRnpc,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 0);
inst.instruction |= (inst.operands[2].reg << 16);
@@ -5035,22 +4897,16 @@
Error if Rd, Rn or Rm are R15. */
static void
-do_qadd16 (char * str)
+do_qadd16 (void)
{
- if (parse_operands (str, OPERANDS3(RRnpc,RRnpc,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= (inst.operands[2].reg << 0);
}
static void
-do_rbit (char *str)
+do_rbit (void)
{
- if (parse_operands (str, OPERANDS2(RR,RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 0);
}
@@ -5062,11 +4918,8 @@
Error if Rd or Rm are R15. */
static void
-do_rev (char * str)
+do_rev (void)
{
- if (parse_operands (str, OPERANDS2(RRnpc,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 0);
}
@@ -5078,11 +4931,8 @@
Error if Rn is R15. */
static void
-do_rfe (char * str)
+do_rfe (void)
{
- if (parse_operands (str, OPERANDS1(RRw)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 16);
if (inst.operands[0].writeback)
inst.instruction |= WRITE_BACK;
@@ -5091,11 +4941,8 @@
/* ARM V6 ssat (argument parse). */
static void
-do_ssat (char * str)
+do_ssat (void)
{
- if (parse_operands (str, OPERANDS4(RRnpc,I32,RRnpc,oSHllar)))
- return;
-
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= (inst.operands[1].imm - 1) << 16;
inst.instruction |= inst.operands[2].reg << 0;
@@ -5107,11 +4954,8 @@
/* ARM V6 usat (argument parse). */
static void
-do_usat (char * str)
+do_usat (void)
{
- if (parse_operands (str, OPERANDS4(RRnpc,I31,RRnpc,oSHllar)))
- return;
-
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].imm << 16;
inst.instruction |= inst.operands[2].reg << 0;
@@ -5123,22 +4967,16 @@
/* ARM V6 ssat16 (argument parse). */
static void
-do_ssat16 (char * str)
+do_ssat16 (void)
{
- if (parse_operands (str, OPERANDS3(RRnpc,I16,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= ((inst.operands[1].imm - 1) << 16);
inst.instruction |= (inst.operands[2].reg << 0);
}
static void
-do_usat16 (char * str)
+do_usat16 (void)
{
- if (parse_operands (str, OPERANDS3(RRnpc,I15,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].imm << 16);
inst.instruction |= (inst.operands[2].reg << 0);
@@ -5151,31 +4989,22 @@
BE or LE. */
static void
-do_setend (char * str)
+do_setend (void)
{
- if (parse_operands (str, OPERANDS1(ENDI)))
- return;
-
if (inst.operands[0].imm)
inst.instruction |= 0x200;
}
static void
-do_smi (char * str)
+do_smi (void)
{
- if (parse_operands (str, OPERANDS1(iEXP)))
- return;
-
inst.reloc.type = BFD_RELOC_ARM_SMI;
inst.reloc.pc_rel = 0;
}
static void
-do_swi (char * str)
+do_swi (void)
{
- if (parse_operands (str, OPERANDS1(iEXP)))
- return;
-
inst.reloc.type = BFD_RELOC_ARM_SWI;
inst.reloc.pc_rel = 0;
}
@@ -5186,11 +5015,8 @@
Error if any register is R15. */
static void
-do_smla (char * str)
+do_smla (void)
{
- if (parse_operands (str, OPERANDS4(RRnpc,RRnpc,RRnpc,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 16);
inst.instruction |= (inst.operands[1].reg << 0);
inst.instruction |= (inst.operands[2].reg << 8);
@@ -5203,11 +5029,8 @@
Warning if Rdlo == Rdhi. */
static void
-do_smlal (char * str)
+do_smlal (void)
{
- if (parse_operands (str, OPERANDS4(RRnpc,RRnpc,RRnpc,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= (inst.operands[2].reg << 0);
@@ -5222,11 +5045,8 @@
Error if any register is R15. */
static void
-do_smul (char * str)
+do_smul (void)
{
- if (parse_operands (str, OPERANDS3(RRnpc,RRnpc,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 16);
inst.instruction |= (inst.operands[1].reg << 0);
inst.instruction |= (inst.operands[2].reg << 8);
@@ -5235,11 +5055,8 @@
/* ARM V6 srs (argument parse). */
static void
-do_srs (char * str)
+do_srs (void)
{
- if (parse_operands (str, OPERANDS1(I31w)))
- return;
-
inst.instruction |= inst.operands[0].imm;
if (inst.operands[0].writeback)
inst.instruction |= WRITE_BACK;
@@ -5248,10 +5065,8 @@
/* ARM V6 strex (argument parse). */
static void
-do_strex (char * str)
+do_strex (void)
{
- if (parse_operands (str, OPERANDS3(RRnpc,RRnpc,bRRnpc)))
- return;
if (reject_overlap (2, 0,1, 0,2))
return;
@@ -5261,11 +5076,8 @@
}
static void
-do_swap (char * str)
+do_swap (void)
{
- if (parse_operands (str, OPERANDS3(RRnpc,RRnpc,bRRnpc)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 0);
inst.instruction |= (inst.operands[2].reg << 16);
@@ -5280,11 +5092,8 @@
Error if any register uses R15. */
static void
-do_sxtah (char * str)
+do_sxtah (void)
{
- if (parse_operands (str, OPERANDS4(RRnpc,RRnpc,RRnpc,oROR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= (inst.operands[2].reg << 0);
@@ -5298,11 +5107,8 @@
Error if any register uses R15. */
static void
-do_sxth (char * str)
+do_sxth (void)
{
- if (parse_operands (str, OPERANDS3(RRnpc,RRnpc,oROR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 0);
inst.instruction |= (inst.operands[2].imm << 10);
@@ -5315,13 +5121,11 @@
is set if the opcode was SUB. */
static void
-do_t_add_sub (char * str)
+do_t_add_sub (void)
{
int Rd, Rs, Rn;
int subtract = !!(inst.instruction & 0x8000);
- if (parse_operands (str, OPERANDS3(RR,RR_iEX,oRR_iEX)))
- return;
Rd = inst.operands[0].reg;
if (inst.operands[2].present)
{
@@ -5383,11 +5187,8 @@
}
static void
-do_t_adr (char * str)
+do_t_adr (void)
{
- if (parse_operands (str, OPERANDS2(RL,EXP)))
- return;
-
inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
inst.reloc.pc_rel = 1;
@@ -5400,11 +5201,8 @@
BIC and MVN. */
static void
-do_t_arit (char * str)
+do_t_arit (void)
{
- if (parse_operands (str, OPERANDS3(RL,RL,oRL)))
- return;
-
if (inst.operands[2].present)
{
/* Three operand format not allowed for TST, CMN, NEG and MVN.
@@ -5437,11 +5235,8 @@
BKPT <immed_8>. */
static void
-do_t_bkpt (char * str)
+do_t_bkpt (void)
{
- if (parse_operands (str, OPERANDS1(obI255)))
- return;
-
inst.instruction |= inst.operands[0].imm;
}
@@ -5453,11 +5248,8 @@
into inst.instruction. */
static void
-do_t_blx (char * str)
+do_t_blx (void)
{
- if (parse_operands (str, OPERANDS1(RR_EX)))
- return;
-
if (inst.operands[0].isreg)
/* We have a register, so this is BLX(2). */
inst.instruction |= (inst.operands[0].reg << 3);
@@ -5472,31 +5264,22 @@
}
static void
-do_t_branch9 (char * str)
+do_t_branch9 (void)
{
- if (parse_operands (str, OPERANDS1(EXP)))
- return;
-
inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
inst.reloc.pc_rel = 1;
}
static void
-do_t_branch12 (char * str)
+do_t_branch12 (void)
{
- if (parse_operands (str, OPERANDS1(EXP)))
- return;
-
inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
inst.reloc.pc_rel = 1;
}
static void
-do_t_branch23 (char * str)
+do_t_branch23 (void)
{
- if (parse_operands (str, OPERANDS1(EXP)))
- return;
-
inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
inst.reloc.pc_rel = 1;
@@ -5513,11 +5296,8 @@
}
static void
-do_t_bx (char * str)
+do_t_bx (void)
{
- if (parse_operands (str, OPERANDS1(RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 3);
/* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
should cause the alignment to be checked once it is known. This is
@@ -5527,33 +5307,24 @@
/* THUMB CPS instruction (argument parse). */
static void
-do_t_cps (char * str)
+do_t_cps (void)
{
- if (parse_operands (str, OPERANDS1(CPSF)))
- return;
-
inst.instruction |= inst.operands[0].imm;
}
/* THUMB CPY instruction (argument parse). */
static void
-do_t_cpy (char * str)
+do_t_cpy (void)
{
- if (parse_operands (str, OPERANDS2(RR,RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
inst.instruction |= (inst.operands[0].reg & 0x7) << 0;
inst.instruction |= inst.operands[1].reg << 3;
}
static void
-do_t_ldmstm (char * str)
+do_t_ldmstm (void)
{
- if (parse_operands (str, OPERANDS2(RLw,REGLST)))
- return;
-
if (inst.reloc.type != BFD_RELOC_UNUSED)
{
/* This really doesn't seem worth it. */
@@ -5579,10 +5350,8 @@
}
static void
-do_t_lds (char * str)
+do_t_lds (void)
{
- if (parse_operands (str, OPERANDS2(RL,ADDR)))
- return;
/* Only [Rn,Rm] is acceptable. */
if (!inst.operands[1].isreg || !inst.operands[1].immisreg
|| inst.operands[1].postind || inst.operands[1].shifted
@@ -5603,11 +5372,8 @@
}
static void
-do_t_ldst (char *str)
+do_t_ldst (void)
{
- if (parse_operands (str, OPERANDS2(RL,ADDR)))
- return;
-
if (!inst.operands[1].isreg)
if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
return;
@@ -5695,11 +5461,8 @@
}
static void
-do_t_mov_cmp (char * str)
+do_t_mov_cmp (void)
{
- if (parse_operands (str, OPERANDS2(RR,RR_iEX)))
- return;
-
if (inst.operands[1].isreg)
{
if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
@@ -5742,21 +5505,16 @@
static void
-do_t_setend (char * str)
+do_t_setend (void)
{
- if (parse_operands (str, OPERANDS1(ENDI)))
- return;
-
if (inst.operands[0].imm)
inst.instruction |= 0x8;
}
static void
-do_t_shift (char * str)
+do_t_shift (void)
{
int Rs;
- if (parse_operands (str, OPERANDS3(RL,RL_iEX,oRL_iEX)))
- return;
if (inst.operands[2].present)
{
@@ -5802,19 +5560,14 @@
}
static void
-do_t_swi (char * str)
+do_t_swi (void)
{
- if (parse_operands (str, OPERANDS1(EXP)))
- return;
-
inst.reloc.type = BFD_RELOC_ARM_SWI;
}
static void
-do_t_push_pop (char * str)
+do_t_push_pop (void)
{
- if (parse_operands (str, OPERANDS1(REGLST)))
- return;
if (inst.operands[0].writeback)
{
inst.error = _("push/pop do not support {reglist}^");
@@ -5851,100 +5604,71 @@
before dyad, arithmetic then move then load/store. */
static void
-do_vfp_sp_monadic (char * str)
+do_vfp_sp_monadic (void)
{
- if (parse_operands (str, OPERANDS2(RVS,RVS)))
- return;
-
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sd);
vfp_sp_encode_reg (inst.operands[1].reg, VFP_REG_Sm);
}
static void
-do_vfp_dp_monadic (char * str)
+do_vfp_dp_monadic (void)
{
- if (parse_operands (str, OPERANDS2(RVD,RVD)))
- return;
-
inst.instruction |= (inst.operands[0].reg << VFP_REG_Dd);
inst.instruction |= (inst.operands[1].reg << VFP_REG_Dm);
}
static void
-do_vfp_sp_dyadic (char * str)
+do_vfp_sp_dyadic (void)
{
- if (parse_operands (str, OPERANDS3(RVS,RVS,RVS)))
- return;
-
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sd);
vfp_sp_encode_reg (inst.operands[1].reg, VFP_REG_Sn);
vfp_sp_encode_reg (inst.operands[2].reg, VFP_REG_Sm);
}
static void
-do_vfp_dp_dyadic (char * str)
+do_vfp_dp_dyadic (void)
{
- if (parse_operands (str, OPERANDS3(RVD,RVD,RVD)))
- return;
-
inst.instruction |= (inst.operands[0].reg << VFP_REG_Dd);
inst.instruction |= (inst.operands[1].reg << VFP_REG_Dn);
inst.instruction |= (inst.operands[2].reg << VFP_REG_Dm);
}
static void
-do_vfp_sp_compare_z (char * str)
+do_vfp_sp_compare_z (void)
{
- if (parse_operands (str, OPERANDS1(RVS)))
- return;
-
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sd);
}
static void
-do_vfp_dp_compare_z (char * str)
+do_vfp_dp_compare_z (void)
{
- if (parse_operands (str, OPERANDS1(RVD)))
- return;
-
inst.instruction |= (inst.operands[0].reg << VFP_REG_Dd);
}
static void
-do_vfp_dp_sp_cvt (char * str)
+do_vfp_dp_sp_cvt (void)
{
- if (parse_operands (str, OPERANDS2(RVD,RVS)))
- return;
-
inst.instruction |= (inst.operands[0].reg << VFP_REG_Dd);
vfp_sp_encode_reg (inst.operands[1].reg, VFP_REG_Sm);
}
static void
-do_vfp_sp_dp_cvt (char * str)
+do_vfp_sp_dp_cvt (void)
{
- if (parse_operands (str, OPERANDS2(RVS,RVD)))
- return;
-
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sd);
inst.instruction |= (inst.operands[1].reg << VFP_REG_Dm);
}
static void
-do_vfp_reg_from_sp (char * str)
+do_vfp_reg_from_sp (void)
{
- if (parse_operands (str, OPERANDS2(RR,RVS)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
vfp_sp_encode_reg (inst.operands[1].reg, VFP_REG_Sn);
}
static void
-do_vfp_reg2_from_sp2 (char * str)
+do_vfp_reg2_from_sp2 (void)
{
- if (parse_operands (str, OPERANDS3(RR,RR,VRSLST)))
- return;
if (inst.operands[2].imm != 2)
{
inst.error = _("only two consecutive VFP SP registers allowed here");
@@ -5957,20 +5681,15 @@
}
static void
-do_vfp_sp_from_reg (char * str)
+do_vfp_sp_from_reg (void)
{
- if (parse_operands (str, OPERANDS2(RVS,RR)))
- return;
-
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sn);
inst.instruction |= (inst.operands[1].reg << 12);
}
static void
-do_vfp_sp2_from_reg2 (char * str)
+do_vfp_sp2_from_reg2 (void)
{
- if (parse_operands (str, OPERANDS3(VRSLST,RR,RR)))
- return;
if (inst.operands[0].imm != 2)
{
inst.error = _("only two consecutive VFP SP registers allowed here");
@@ -5983,93 +5702,67 @@
}
static void
-do_vfp_reg_from_dp (char * str)
+do_vfp_reg_from_dp (void)
{
- if (parse_operands (str, OPERANDS2(RR,RVD)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << VFP_REG_Dn);
}
static void
-do_vfp_reg2_from_dp (char * str)
+do_vfp_reg2_from_dp (void)
{
- if (parse_operands (str, OPERANDS3(RR,RR,RVD)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= (inst.operands[2].reg << VFP_REG_Dm);
}
static void
-do_vfp_dp_from_reg (char * str)
+do_vfp_dp_from_reg (void)
{
- if (parse_operands (str, OPERANDS2(RVD,RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << VFP_REG_Dn);
inst.instruction |= (inst.operands[1].reg << 12);
}
static void
-do_vfp_dp_from_reg2 (char * str)
+do_vfp_dp_from_reg2 (void)
{
- if (parse_operands (str, OPERANDS3(RVD,RR,RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << VFP_REG_Dm);
inst.instruction |= (inst.operands[1].reg << 12);
inst.instruction |= (inst.operands[2].reg << 16);
}
static void
-do_vfp_reg_from_ctrl (char * str)
+do_vfp_reg_from_ctrl (void)
{
- if (parse_operands (str, OPERANDS2(RR,RVC)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
}
static void
-do_vfp_ctrl_from_reg (char * str)
+do_vfp_ctrl_from_reg (void)
{
- if (parse_operands (str, OPERANDS2(RVC,RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 16);
inst.instruction |= (inst.operands[1].reg << 12);
}
static void
-do_vfp_sp_ldst (char * str)
+do_vfp_sp_ldst (void)
{
- if (parse_operands (str, OPERANDS2(RVS,ADDR)))
- return;
-
vfp_sp_encode_reg (inst.operands[0].reg, VFP_REG_Sd);
encode_cp_address_arm (1, FALSE, TRUE, 0);
}
static void
-do_vfp_dp_ldst (char * str)
+do_vfp_dp_ldst (void)
{
- if (parse_operands (str, OPERANDS2(RVD,ADDR)))
- return;
-
inst.instruction |= inst.operands[0].reg << VFP_REG_Dd;
encode_cp_address_arm (1, FALSE, TRUE, 0);
}
static void
-vfp_sp_ldstm (char * str, enum vfp_ldstm_type ldstm_type)
+vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
{
- if (parse_operands (str, OPERANDS2(RRw,VRSLST)))
- return;
if (inst.operands[0].writeback)
inst.instruction |= WRITE_BACK;
else if (ldstm_type != VFP_LDSTMIA)
@@ -6084,12 +5777,10 @@
}
static void
-vfp_dp_ldstm (char * str, enum vfp_ldstm_type ldstm_type)
+vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
{
int count;
- if (parse_operands (str, OPERANDS2(RRw,VRDLST)))
- return;
if (inst.operands[0].writeback)
inst.instruction |= WRITE_BACK;
else if (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX)
@@ -6109,39 +5800,39 @@
}
static void
-do_vfp_sp_ldstmia (char * str)
+do_vfp_sp_ldstmia (void)
{
- vfp_sp_ldstm (str, VFP_LDSTMIA);
+ vfp_sp_ldstm (VFP_LDSTMIA);
}
static void
-do_vfp_sp_ldstmdb (char * str)
+do_vfp_sp_ldstmdb (void)
{
- vfp_sp_ldstm (str, VFP_LDSTMDB);
+ vfp_sp_ldstm (VFP_LDSTMDB);
}
static void
-do_vfp_dp_ldstmia (char * str)
+do_vfp_dp_ldstmia (void)
{
- vfp_dp_ldstm (str, VFP_LDSTMIA);
+ vfp_dp_ldstm (VFP_LDSTMIA);
}
static void
-do_vfp_dp_ldstmdb (char * str)
+do_vfp_dp_ldstmdb (void)
{
- vfp_dp_ldstm (str, VFP_LDSTMDB);
+ vfp_dp_ldstm (VFP_LDSTMDB);
}
static void
-do_vfp_xp_ldstmia (char *str)
+do_vfp_xp_ldstmia (void)
{
- vfp_dp_ldstm (str, VFP_LDSTMIAX);
+ vfp_dp_ldstm (VFP_LDSTMIAX);
}
static void
-do_vfp_xp_ldstmdb (char * str)
+do_vfp_xp_ldstmdb (void)
{
- vfp_dp_ldstm (str, VFP_LDSTMDBX);
+ vfp_dp_ldstm (VFP_LDSTMDBX);
}
@@ -6151,80 +5842,57 @@
Format: <WFS|RFS|WFC|RFC>{cond} Rn */
static void
-do_fpa_ctrl (char * str)
+do_fpa_ctrl (void)
{
- if (parse_operands (str, OPERANDS1(RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
}
static void
-do_fpa_cmp (char * str)
+do_fpa_cmp (void)
{
- if (parse_operands (str, OPERANDS2(RF,RF_IF)))
- return;
-
inst.instruction |= inst.operands[0].reg << 16;
inst.instruction |= inst.operands[1].reg;
}
static void
-do_fpa_monadic (char * str)
+do_fpa_monadic (void)
{
- if (parse_operands (str, OPERANDS2(RF,RF_IF)))
- return;
-
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg;
}
static void
-do_fpa_dyadic (char * str)
+do_fpa_dyadic (void)
{
- if (parse_operands (str, OPERANDS3(RF,RF,RF_IF)))
- return;
-
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg << 16;
inst.instruction |= inst.operands[2].reg;
}
static void
-do_fpa_from_reg (char * str)
+do_fpa_from_reg (void)
{
- if (parse_operands (str, OPERANDS2(RF,RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 16);
inst.instruction |= (inst.operands[1].reg << 12);
}
static void
-do_fpa_to_reg (char * str)
+do_fpa_to_reg (void)
{
- if (parse_operands (str, OPERANDS2(RR,RF)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 0);
}
static void
-do_fpa_ldst (char * str)
+do_fpa_ldst (void)
{
- if (parse_operands (str, OPERANDS2(RF,ADDR)))
- return;
inst.instruction |= (inst.operands[0].reg << 12);
encode_cp_address_arm (1, TRUE, TRUE, 0);
}
static void
-do_fpa_ldmstm (char * str)
+do_fpa_ldmstm (void)
{
- if (parse_operands (str, OPERANDS3(RF,bI4,ADDR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
switch (inst.operands[1].imm)
{
@@ -6267,131 +5935,90 @@
/* iWMMXt instructions: strictly in alphabetical order. */
static void
-do_iwmmxt_tandorc (char * str)
+do_iwmmxt_tandorc (void)
{
- if (parse_operands (str, OPERANDS1(RR)))
- return;
if (inst.operands[0].reg != REG_PC)
- {
- inst.error = _("only r15 allowed here");
- return;
- }
-
- inst.instruction |= (inst.operands[0].reg << 12);
+ inst.error = _("only r15 allowed here");
}
static void
-do_iwmmxt_tbcst (char * str)
+do_iwmmxt_tbcst (void)
{
- if (parse_operands (str, OPERANDS2(RR,RIWR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
}
static void
-do_iwmmxt_textrc (char * str)
+do_iwmmxt_textrc (void)
{
- if (parse_operands (str, OPERANDS2(RR,I7)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= inst.operands[1].imm;
}
static void
-do_iwmmxt_textrm (char * str)
+do_iwmmxt_textrm (void)
{
- if (parse_operands (str, OPERANDS3(RR,RIWR,I7)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= inst.operands[2].imm;
}
static void
-do_iwmmxt_tinsr (char * str)
+do_iwmmxt_tinsr (void)
{
- if (parse_operands (str, OPERANDS3(RIWR,RR,I7)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 16);
inst.instruction |= (inst.operands[1].reg << 12);
inst.instruction |= inst.operands[2].imm;
}
static void
-do_iwmmxt_tmcr (char * str)
+do_iwmmxt_tmcr (void)
{
- if (parse_operands (str, OPERANDS2(RIWC,RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 16);
inst.instruction |= (inst.operands[1].reg << 12);
}
static void
-do_iwmmxt_tmcrr (char * str)
+do_iwmmxt_tmcrr (void)
{
- if (parse_operands (str, OPERANDS3(RIWR,RR,RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 0);
inst.instruction |= (inst.operands[1].reg << 12);
inst.instruction |= (inst.operands[2].reg << 16);
}
static void
-do_iwmmxt_tmia (char * str)
+do_iwmmxt_tmia (void)
{
- if (parse_operands (str, OPERANDS3(RIWR,RR,RR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 5);
inst.instruction |= (inst.operands[1].reg << 0);
inst.instruction |= (inst.operands[2].reg << 12);
}
static void
-do_iwmmxt_tmovmsk (char * str)
+do_iwmmxt_tmovmsk (void)
{
- if (parse_operands (str, OPERANDS2(RR,RIWR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
-
}
static void
-do_iwmmxt_tmrc (char * str)
+do_iwmmxt_tmrc (void)
{
- if (parse_operands (str, OPERANDS2(RR,RIWC)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
}
static void
-do_iwmmxt_tmrrc (char * str)
+do_iwmmxt_tmrrc (void)
{
- if (parse_operands (str, OPERANDS3(RR,RR,RIWR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= (inst.operands[2].reg << 0);
}
static void
-do_iwmmxt_waligni (char * str)
+do_iwmmxt_waligni (void)
{
- if (parse_operands (str, OPERANDS4(RIWR,RIWR,RIWR,I7)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= (inst.operands[2].reg << 0);
@@ -6399,11 +6026,8 @@
}
static void
-do_iwmmxt_wmov (char * str)
+do_iwmmxt_wmov (void)
{
- if (parse_operands (str, OPERANDS2(RIWR,RIWR)))
- return;
-
/* WMOV rD, rN is an alias for WOR rD, rN, rN. */
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
@@ -6411,21 +6035,15 @@
}
static void
-do_iwmmxt_wldst (char * str)
+do_iwmmxt_wldst (void)
{
- if (parse_operands (str, OPERANDS2(RIWR,ADDR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
encode_cp_address_arm (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
}
static void
-do_iwmmxt_wldstw (char * str)
+do_iwmmxt_wldstw (void)
{
- if (parse_operands (str, OPERANDS2(RIWR_RIWC,ADDR)))
- return;
-
/* RIWR_RIWC clears .isreg for a control register. */
if (!inst.operands[0].isreg)
{
@@ -6443,43 +6061,31 @@
}
static void
-do_iwmmxt_wrwr (char * str)
+do_iwmmxt_wrwr (void)
{
- if (parse_operands (str, OPERANDS2(RIWR,RIWR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
}
static void
-do_iwmmxt_wrwrwcg (char * str)
+do_iwmmxt_wrwrwcg (void)
{
- if (parse_operands (str, OPERANDS3(RIWR,RIWR,RIWG)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= (inst.operands[2].reg << 0);
}
static void
-do_iwmmxt_wrwrwr (char * str)
+do_iwmmxt_wrwrwr (void)
{
- if (parse_operands (str, OPERANDS3(RIWR,RIWR,RIWR)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= (inst.operands[2].reg << 0);
}
static void
-do_iwmmxt_wshufh (char * str)
+do_iwmmxt_wshufh (void)
{
- if (parse_operands (str, OPERANDS3(RIWR,RIWR,I255)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
inst.instruction |= (inst.operands[1].reg << 16);
inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
@@ -6487,11 +6093,8 @@
}
static void
-do_iwmmxt_wzero (char * str)
+do_iwmmxt_wzero (void)
{
- if (parse_operands (str, OPERANDS1(RIWR)))
- return;
-
/* WZERO reg is an alias for WANDN reg, reg, reg. */
inst.instruction |= (inst.operands[0].reg << 0);
inst.instruction |= (inst.operands[0].reg << 12);
@@ -6504,278 +6107,60 @@
/* Insn like "foo X,Y". */
static void
-do_mav_binops (char *str, int mode, const char *pattern)
+do_mav_binops_1 (void)
{
- int shift0 = (mode >> 0) & 0xff;
- int shift1 = (mode >> 8) & 0xff;
-
- if (parse_operands (str, pattern))
- return;
-
- inst.instruction |= (inst.operands[0].reg << shift0);
- inst.instruction |= (inst.operands[1].reg << shift1);
+ inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= (inst.operands[1].reg << 16);
}
-/* Isnsn like "foo X,Y,Z". */
-
static void
-do_mav_triple (char *str, int mode, const char *pattern)
+do_mav_binops_2 (void)
{
- int shift0 = (mode >> 0) & 0xff;
- int shift1 = (mode >> 8) & 0xff;
- int shift2 = (mode >> 16) & 0xff;
-
- if (parse_operands (str, pattern))
- return;
-
- inst.instruction |= (inst.operands[0].reg << shift0);
- inst.instruction |= (inst.operands[1].reg << shift1);
- inst.instruction |= (inst.operands[2].reg << shift2);
+ inst.instruction |= (inst.operands[0].reg << 16);
+ inst.instruction |= (inst.operands[1].reg << 12);
}
-/* Insn like "foo W,X,Y,Z".
- where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
+/* Insns like "foo X,Y,Z". */
static void
-do_mav_quad (char *str, int mode, const char *pattern)
+do_mav_triple_1 (void)
{
- int shift0 = (mode >> 0) & 0xff;
- int shift1 = (mode >> 8) & 0xff;
- int shift2 = (mode >> 16) & 0xff;
- int shift3 = (mode >> 24) & 0xff;
-
- if (parse_operands (str, pattern))
- return;
-
- inst.instruction |= (inst.operands[0].reg << shift0);
- inst.instruction |= (inst.operands[1].reg << shift1);
- inst.instruction |= (inst.operands[2].reg << shift2);
- inst.instruction |= (inst.operands[3].reg << shift3);
+ inst.instruction |= (inst.operands[0].reg << 16);
+ inst.instruction |= (inst.operands[1].reg << 0);
+ inst.instruction |= (inst.operands[2].reg << 12);
}
-/* Wrapper functions. */
-
static void
-do_mav_binops_1a (char * str)
+do_mav_triple_2 (void)
{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RR,RMF));
+ inst.instruction |= (inst.operands[0].reg << 12);
+ inst.instruction |= (inst.operands[1].reg << 16);
+ inst.instruction |= (inst.operands[2].reg << 0);
}
-static void
-do_mav_binops_1b (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RR,RMD));
-}
+/* Insns like "foo W,X,Y,Z".
+ where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
static void
-do_mav_binops_1c (char * str)
+do_mav_quad (void)
{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RR,RMDX));
+ inst.instruction |= (inst.operands[0].reg << 5);
+ inst.instruction |= (inst.operands[1].reg << 12);
+ inst.instruction |= (inst.operands[2].reg << 16);
+ inst.instruction |= (inst.operands[3].reg << 0);
}
-static void
-do_mav_binops_1d (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMF,RMF));
-}
-
-static void
-do_mav_binops_1e (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMD,RMD));
-}
-
-static void
-do_mav_binops_1f (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMD,RMF));
-}
-
-static void
-do_mav_binops_1g (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMF,RMD));
-}
-
-static void
-do_mav_binops_1h (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMF,RMFX));
-}
-
-static void
-do_mav_binops_1i (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMD,RMFX));
-}
-
-static void
-do_mav_binops_1j (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMF,RMDX));
-}
-
-static void
-do_mav_binops_1k (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMD,RMDX));
-}
-
-static void
-do_mav_binops_1l (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMFX,RMF));
-}
-
-static void
-do_mav_binops_1m (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMFX,RMD));
-}
-
-static void
-do_mav_binops_1n (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMFX,RMFX));
-}
-
-static void
-do_mav_binops_1o (char * str)
-{
- do_mav_binops (str, MAV_MODE1, OPERANDS2(RMDX,RMDX));
-}
-
-static void
-do_mav_binops_2a (char * str)
-{
- do_mav_binops (str, MAV_MODE2, OPERANDS2(RMF,RR));
-}
-
-static void
-do_mav_binops_2b (char * str)
-{
- do_mav_binops (str, MAV_MODE2, OPERANDS2(RMD,RR));
-}
-
-static void
-do_mav_binops_2c (char * str)
-{
- do_mav_binops (str, MAV_MODE2, OPERANDS2(RMDX,RR));
-}
-
-static void
-do_mav_binops_3a (char * str)
-{
- do_mav_binops (str, MAV_MODE3, OPERANDS2(RMAX,RMFX));
-}
-
-static void
-do_mav_binops_3b (char * str)
-{
- do_mav_binops (str, MAV_MODE3, OPERANDS2(RMFX,RMAX));
-}
-
-static void
-do_mav_binops_3c (char * str)
-{
- do_mav_binops (str, MAV_MODE3, OPERANDS2(RMAX,RMDX));
-}
-
-static void
-do_mav_binops_3d (char * str)
-{
- do_mav_binops (str, MAV_MODE3, OPERANDS2(RMDX,RMAX));
-}
-
-static void
-do_mav_triple_4a (char * str)
-{
- do_mav_triple (str, MAV_MODE4, OPERANDS3(RMFX,RMFX,RR));
-}
-
-static void
-do_mav_triple_4b (char * str)
-{
- do_mav_triple (str, MAV_MODE4, OPERANDS3(RMDX,RMDX,RR));
-}
-
-static void
-do_mav_triple_5a (char * str)
-{
- do_mav_triple (str, MAV_MODE5, OPERANDS3(RR,RMF,RMF));
-}
-
-static void
-do_mav_triple_5b (char * str)
-{
- do_mav_triple (str, MAV_MODE5, OPERANDS3(RR,RMD,RMD));
-}
-
-static void
-do_mav_triple_5c (char * str)
-{
- do_mav_triple (str, MAV_MODE5, OPERANDS3(RR,RMFX,RMFX));
-}
-
-static void
-do_mav_triple_5d (char * str)
-{
- do_mav_triple (str, MAV_MODE5, OPERANDS3(RR,RMDX,RMDX));
-}
-
-static void
-do_mav_triple_5e (char * str)
-{
- do_mav_triple (str, MAV_MODE5, OPERANDS3(RMF,RMF,RMF));
-}
-
-static void
-do_mav_triple_5f (char * str)
-{
- do_mav_triple (str, MAV_MODE5, OPERANDS3(RMD,RMD,RMD));
-}
-
-static void
-do_mav_triple_5g (char * str)
-{
- do_mav_triple (str, MAV_MODE5, OPERANDS3(RMFX,RMFX,RMFX));
-}
-
-static void
-do_mav_triple_5h (char * str)
-{
- do_mav_triple (str, MAV_MODE5, OPERANDS3(RMDX,RMDX,RMDX));
-}
-
-static void
-do_mav_quad_6a (char * str)
-{
- do_mav_quad (str, MAV_MODE6, OPERANDS4(RMAX,RMFX,RMFX,RMFX));
-}
-
-static void
-do_mav_quad_6b (char * str)
-{
- do_mav_quad (str, MAV_MODE6, OPERANDS4(RMAX,RMAX,RMFX,RMFX));
-}
-
/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
static void
-do_mav_dspsc_1 (char * str)
+do_mav_dspsc_1 (void)
{
- if (parse_operands (str, OPERANDS2(RMDS,RMDX)))
- return;
-
inst.instruction |= (inst.operands[1].reg << 12);
}
/* cfmv32sc<cond> MVDX[15:0],DSPSC. */
static void
-do_mav_dspsc_2 (char * str)
+do_mav_dspsc_0 (void)
{
- if (parse_operands (str, OPERANDS2(RMDX,RMDS)))
- return;
-
inst.instruction |= (inst.operands[0].reg << 12);
}
@@ -6784,7 +6169,7 @@
cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
static void
-encode_mav_shift (void)
+do_mav_shift (void)
{
int imm = inst.operands[2].imm;
@@ -6799,59 +6184,16 @@
inst.instruction |= imm;
}
-static void
-do_mav_shift_1 (char *str)
-{
- if (parse_operands (str, OPERANDS3(RMFX,RMFX,Is63)))
- return;
- encode_mav_shift ();
-}
-
-static void
-do_mav_shift_2 (char * str)
-{
- if (parse_operands (str, OPERANDS3(RMDX,RMDX,Is63)))
- return;
- encode_mav_shift ();
-}
-
/* Maverick load/store instructions.
<insn><cond> CRd,[Rn,<offset>]{!}.
<insn><cond> CRd,[Rn],<offset>. */
static void
-do_mav_ldst (char *str, const char *operands)
+do_mav_ldst (void)
{
- if (parse_operands (str, operands))
- return;
-
inst.instruction |= inst.operands[0].reg << 12;
encode_cp_address_arm (1, TRUE, TRUE, 0);
}
-
-static void
-do_mav_ldst_1 (char * str)
-{
- do_mav_ldst (str, OPERANDS2(RMF,ADDR));
-}
-
-static void
-do_mav_ldst_2 (char * str)
-{
- do_mav_ldst (str, OPERANDS2(RMD,ADDR));
-}
-
-static void
-do_mav_ldst_3 (char * str)
-{
- do_mav_ldst (str, OPERANDS2(RMFX,ADDR));
-}
-
-static void
-do_mav_ldst_4 (char * str)
-{
- do_mav_ldst (str, OPERANDS2(RMDX,ADDR));
-}
/* XScale instructions. Also sorted arithmetic before move. */
@@ -6861,11 +6203,8 @@
MIAxycc acc0,Rm,Rs. */
static void
-do_xsc_mia (char * str)
+do_xsc_mia (void)
{
- if (parse_operands (str, OPERANDS3(RXA,RRnpc,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[1].reg << 0);
inst.instruction |= (inst.operands[2].reg << 12);
}
@@ -6875,11 +6214,8 @@
MARcc acc0,RdLo,RdHi. */
static void
-do_xsc_mar (char * str)
+do_xsc_mar (void)
{
- if (parse_operands (str, OPERANDS3(RXA,RRnpc,RRnpc)))
- return;
-
inst.instruction |= (inst.operands[1].reg << 12);
inst.instruction |= (inst.operands[2].reg << 16);
}
@@ -6889,10 +6225,8 @@
MRAcc RdLo,RdHi,acc0. */
static void
-do_xsc_mra (char * str)
+do_xsc_mra (void)
{
- if (parse_operands (str, OPERANDS3(RRnpc,RRnpc,RXA)))
- return;
if (reject_overlap (1, 0,1))
return;
@@ -7022,8 +6356,8 @@
mapping_state (MAP_THUMB);
inst.instruction = opcode->value;
inst.size = (opcode->value > 0xffff ? 4 : 2);
- skip_whitespace (p);
- opcode->parms (p);
+ if (!parse_operands (p, opcode->operands))
+ opcode->encode ();
output_inst (str);
return;
}
@@ -7044,8 +6378,8 @@
mapping_state (MAP_ARM);
inst.instruction = opcode->value;
inst.size = INSN_SIZE;
- skip_whitespace (p);
- opcode->parms (p);
+ if (!parse_operands (p, opcode->operands))
+ opcode->encode ();
output_inst (str);
return;
}
@@ -7378,1197 +6712,1198 @@
/* Table of ARM-format instructions. These macros assemble the conditional
variants of each instruction from its bare form. */
-#define CE(mnem, opcode, aenc) \
- { #mnem, 0xe ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "eq", 0x0 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "ne", 0x1 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "cs", 0x2 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "hs", 0x2 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "cc", 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "ul", 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "lo", 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "mi", 0x4 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "pl", 0x5 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "vs", 0x6 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "vc", 0x7 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "hi", 0x8 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "ls", 0x9 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "ge", 0xa ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "lt", 0xb ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "gt", 0xc ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "le", 0xd ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #mnem "al", 0xe ## opcode, ARM_VARIANT, do_ ## aenc }
+#define CE(mnem, opc, nops, ops, aenc) \
+ { #mnem, 0xe ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "eq", 0x0 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "ne", 0x1 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "cs", 0x2 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "hs", 0x2 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "cc", 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "ul", 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "lo", 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "mi", 0x4 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "pl", 0x5 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "vs", 0x6 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "vc", 0x7 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "hi", 0x8 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "ls", 0x9 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "ge", 0xa ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "lt", 0xb ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "gt", 0xc ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "le", 0xd ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #mnem "al", 0xe ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }
-#define CM(m1, m2, opcode, aenc) \
- { #m1 #m2, 0xe ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "eq" #m2, 0x0 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "ne" #m2, 0x1 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "cs" #m2, 0x2 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "hs" #m2, 0x2 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "cc" #m2, 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "ul" #m2, 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "lo" #m2, 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "mi" #m2, 0x4 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "pl" #m2, 0x5 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "vs" #m2, 0x6 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "vc" #m2, 0x7 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "hi" #m2, 0x8 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "ls" #m2, 0x9 ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "ge" #m2, 0xa ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "lt" #m2, 0xb ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "gt" #m2, 0xc ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "le" #m2, 0xd ## opcode, ARM_VARIANT, do_ ## aenc }, \
- { #m1 "al" #m2, 0xe ## opcode, ARM_VARIANT, do_ ## aenc }
+#define CM(m1, m2, opc, nops, ops, aenc) \
+ { #m1 #m2, 0xe ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "eq" #m2, 0x0 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "ne" #m2, 0x1 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "cs" #m2, 0x2 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "hs" #m2, 0x2 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "cc" #m2, 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "ul" #m2, 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "lo" #m2, 0x3 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "mi" #m2, 0x4 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "pl" #m2, 0x5 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "vs" #m2, 0x6 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "vc" #m2, 0x7 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "hi" #m2, 0x8 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "ls" #m2, 0x9 ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "ge" #m2, 0xa ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "lt" #m2, 0xb ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "gt" #m2, 0xc ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "le" #m2, 0xd ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }, \
+ { #m1 "al" #m2, 0xe ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }
-#define UE(mnem, opcode, aenc) \
- { #mnem, 0xe ## opcode, ARM_VARIANT, do_ ## aenc }
+#define UE(mnem, opc, nops, ops, aenc) \
+ { #mnem, 0xe ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }
-#define UF(mnem, opcode, aenc) \
- { #mnem, 0xf ## opcode, ARM_VARIANT, do_ ## aenc }
+#define UF(mnem, opc, nops, ops, aenc) \
+ { #mnem, 0xf ## opc, ARM_VARIANT, OPERANDS##nops ops, do_ ## aenc }
static const struct asm_opcode insns[] =
{
#define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
- CE(and, 0000000, arit),
- CM(and,s, 0100000, arit),
- CE(eor, 0200000, arit),
- CM(eor,s, 0300000, arit),
- CE(sub, 0400000, arit),
- CM(sub,s, 0500000, arit),
- CE(rsb, 0600000, arit),
- CM(rsb,s, 0700000, arit),
- CE(add, 0800000, arit),
- CM(add,s, 0900000, arit),
- CE(adc, 0a00000, arit),
- CM(adc,s, 0b00000, arit),
- CE(sbc, 0c00000, arit),
- CM(sbc,s, 0d00000, arit),
- CE(rsc, 0e00000, arit),
- CM(rsc,s, 0f00000, arit),
- CE(orr, 1800000, arit),
- CM(orr,s, 1900000, arit),
- CE(bic, 1c00000, arit),
- CM(bic,s, 1d00000, arit),
+ CE(and, 0000000, 3, (RR, RR, SHOP), arit),
+ CM(and,s, 0100000, 3, (RR, RR, SHOP), arit),
+ CE(eor, 0200000, 3, (RR, RR, SHOP), arit),
+ CM(eor,s, 0300000, 3, (RR, RR, SHOP), arit),
+ CE(sub, 0400000, 3, (RR, RR, SHOP), arit),
+ CM(sub,s, 0500000, 3, (RR, RR, SHOP), arit),
+ CE(rsb, 0600000, 3, (RR, RR, SHOP), arit),
+ CM(rsb,s, 0700000, 3, (RR, RR, SHOP), arit),
+ CE(add, 0800000, 3, (RR, RR, SHOP), arit),
+ CM(add,s, 0900000, 3, (RR, RR, SHOP), arit),
+ CE(adc, 0a00000, 3, (RR, RR, SHOP), arit),
+ CM(adc,s, 0b00000, 3, (RR, RR, SHOP), arit),
+ CE(sbc, 0c00000, 3, (RR, RR, SHOP), arit),
+ CM(sbc,s, 0d00000, 3, (RR, RR, SHOP), arit),
+ CE(rsc, 0e00000, 3, (RR, RR, SHOP), arit),
+ CM(rsc,s, 0f00000, 3, (RR, RR, SHOP), arit),
+ CE(orr, 1800000, 3, (RR, RR, SHOP), arit),
+ CM(orr,s, 1900000, 3, (RR, RR, SHOP), arit),
+ CE(bic, 1c00000, 3, (RR, RR, SHOP), arit),
+ CM(bic,s, 1d00000, 3, (RR, RR, SHOP), arit),
- CE(tst, 1100000, cmp),
- CM(tst,s, 1100000, cmp),
- CM(tst,p, 110f000, cmp),
- CE(teq, 1300000, cmp),
- CM(teq,s, 1300000, cmp),
- CM(teq,p, 130f000, cmp),
- CE(cmp, 1500000, cmp),
- CM(cmp,s, 1500000, cmp),
- CM(cmp,p, 150f000, cmp),
- CE(cmn, 1700000, cmp),
- CM(cmn,s, 1700000, cmp),
- CM(cmn,p, 170f000, cmp),
+ CE(tst, 1100000, 2, (RR, SHOP), cmp),
+ CM(tst,s, 1100000, 2, (RR, SHOP), cmp),
+ CM(tst,p, 110f000, 2, (RR, SHOP), cmp),
+ CE(teq, 1300000, 2, (RR, SHOP), cmp),
+ CM(teq,s, 1300000, 2, (RR, SHOP), cmp),
+ CM(teq,p, 130f000, 2, (RR, SHOP), cmp),
+ CE(cmp, 1500000, 2, (RR, SHOP), cmp),
+ CM(cmp,s, 1500000, 2, (RR, SHOP), cmp),
+ CM(cmp,p, 150f000, 2, (RR, SHOP), cmp),
+ CE(cmn, 1700000, 2, (RR, SHOP), cmp),
+ CM(cmn,s, 1700000, 2, (RR, SHOP), cmp),
+ CM(cmn,p, 170f000, 2, (RR, SHOP), cmp),
- CE(mov, 1a00000, mov),
- CM(mov,s, 1b00000, mov),
- CE(mvn, 1e00000, mov),
- CM(mvn,s, 1f00000, mov),
+ CE(mov, 1a00000, 2, (RR, SHOP), mov),
+ CM(mov,s, 1b00000, 2, (RR, SHOP), mov),
+ CE(mvn, 1e00000, 2, (RR, SHOP), mov),
+ CM(mvn,s, 1f00000, 2, (RR, SHOP), mov),
- CE(ldr, 4100000, ldst),
- CM(ldr,b, 4500000, ldst),
- CM(ldr,t, 4300000, ldstt),
- CM(ldr,bt, 4700000, ldstt),
- CE(str, 4000000, ldst),
- CM(str,b, 4400000, ldst),
- CM(str,t, 4200000, ldstt),
- CM(str,bt, 4600000, ldstt),
+ CE(ldr, 4100000, 2, (RR, ADDR), ldst),
+ CM(ldr,b, 4500000, 2, (RR, ADDR), ldst),
+ CM(ldr,t, 4300000, 2, (RR, ADDR), ldstt),
+ CM(ldr,bt, 4700000, 2, (RR, ADDR), ldstt),
+ CE(str, 4000000, 2, (RR, ADDR), ldst),
+ CM(str,b, 4400000, 2, (RR, ADDR), ldst),
+ CM(str,t, 4200000, 2, (RR, ADDR), ldstt),
+ CM(str,bt, 4600000, 2, (RR, ADDR), ldstt),
- CM(stm,ia, 8800000, ldmstm),
- CM(stm,ib, 9800000, ldmstm),
- CM(stm,da, 8000000, ldmstm),
- CM(stm,db, 9000000, ldmstm),
- CM(stm,fd, 9000000, ldmstm),
- CM(stm,fa, 9800000, ldmstm),
- CM(stm,ea, 8800000, ldmstm),
- CM(stm,ed, 8000000, ldmstm),
+ CM(stm,ia, 8800000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,ib, 9800000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,da, 8000000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,db, 9000000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,fd, 9000000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,fa, 9800000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,ea, 8800000, 2, (RRw, REGLST), ldmstm),
+ CM(stm,ed, 8000000, 2, (RRw, REGLST), ldmstm),
- CM(ldm,ia, 8900000, ldmstm),
- CM(ldm,ib, 9900000, ldmstm),
- CM(ldm,da, 8100000, ldmstm),
- CM(ldm,db, 9100000, ldmstm),
- CM(ldm,fd, 8900000, ldmstm),
- CM(ldm,fa, 8100000, ldmstm),
- CM(ldm,ea, 9100000, ldmstm),
- CM(ldm,ed, 9900000, ldmstm),
+ CM(ldm,ia, 8900000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,ib, 9900000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,da, 8100000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,db, 9100000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,fd, 8900000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,fa, 8100000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,ea, 9100000, 2, (RRw, REGLST), ldmstm),
+ CM(ldm,ed, 9900000, 2, (RRw, REGLST), ldmstm),
- CE(swi, f000000, swi),
+ CE(swi, f000000, 1, (iEXP), swi),
#ifdef TE_WINCE
/* XXX This is the wrong place to do this. Think multi-arch. */
- CE(b, a000000, branch),
- CE(bl, b000000, branch),
+ CE(b, a000000, 1, (EXPr), branch),
+ CE(bl, b000000, 1, (EXPr), branch),
#else
- CE(b, afffffe, branch),
- CE(bl, bfffffe, branch),
+ CE(b, afffffe, 1, (EXPr), branch),
+ CE(bl, bfffffe, 1, (EXPr), branch),
#endif
/* Pseudo ops. */
- CE(adr, 28f0000, adr),
- CM(adr,l, 28f0000, adrl),
- CE(nop, 1a00000, nop),
+ CE(adr, 28f0000, 2, (RR, EXP), adr),
+ CM(adr,l, 28f0000, 2, (RR, EXP), adrl),
+ CE(nop, 1a00000, 1, (ocI255), nop),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
- CE(mul, 0000090, mul),
- CM(mul,s, 0100090, mul),
- CE(mla, 0200090, mla),
- CM(mla,s, 0300090, mla),
+ CE(mul, 0000090, 3, (RRnpc, RRnpc, RR), mul),
+ CM(mul,s, 0100090, 3, (RRnpc, RRnpc, RR), mul),
+ CE(mla, 0200090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
+ CM(mla,s, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
/* Generic coprocessor instructions. */
- CE(cdp, e000000, cdp),
- CE(ldc, c100000, lstc),
- CM(ldc,l, c500000, lstc),
- CE(stc, c000000, lstc),
- CM(stc,l, c400000, lstc),
- CE(mcr, e000010, co_reg),
- CE(mrc, e100010, co_reg),
+ CE(cdp, e000000, 6, (RCP, bI15, RCN, RCN, RCN, obI7), cdp),
+ CE(ldc, c100000, 3, (RCP, RCN, ADDR), lstc),
+ CM(ldc,l, c500000, 3, (RCP, RCN, ADDR), lstc),
+ CE(stc, c000000, 3, (RCP, RCN, ADDR), lstc),
+ CM(stc,l, c400000, 3, (RCP, RCN, ADDR), lstc),
+ CE(mcr, e000010, 6, (RCP, bI7, RR, RCN, RCN, obI7), co_reg),
+ CE(mrc, e100010, 6, (RCP, bI7, RR, RCN, RCN, obI7), co_reg),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
- CE(swp, 1000090, swap),
- CM(swp,b, 1400090, swap),
+ CE(swp, 1000090, 3, (RRnpc, RRnpc, bRRnpc), swap),
+ CM(swp,b, 1400090, 3, (RRnpc, RRnpc, bRRnpc), swap),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
- CE(mrs, 10f0000, mrs),
- CE(msr, 120f000, msr),
+ CE(mrs, 10f0000, 2, (RR, PSR), mrs),
+ CE(msr, 120f000, 2, (PSR, RR_iEX), msr),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
- CE(smull, 0c00090, mull),
- CM(smull,s, 0d00090, mull),
- CE(umull, 0800090, mull),
- CM(umull,s, 0900090, mull),
- CE(smlal, 0e00090, mull),
- CM(smlal,s, 0f00090, mull),
- CE(umlal, 0a00090, mull),
- CM(umlal,s, 0b00090, mull),
+ CE(smull, 0c00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CE(umull, 0800090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CE(smlal, 0e00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CE(umlal, 0a00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
- CM(ldr,h, 01000b0, ldstv4),
- CM(ldr,sh, 01000f0, ldstv4),
- CM(ldr,sb, 01000d0, ldstv4),
- CM(str,h, 00000b0, ldstv4),
+ CM(ldr,h, 01000b0, 2, (RR, ADDR), ldstv4),
+ CM(ldr,sh, 01000f0, 2, (RR, ADDR), ldstv4),
+ CM(ldr,sb, 01000d0, 2, (RR, ADDR), ldstv4),
+ CM(str,h, 00000b0, 2, (RR, ADDR), ldstv4),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
/* ARM Architecture 4T. */
/* Note: bx (and blx) are required on V5, even if the processor does
not support Thumb. */
- CE(bx, 12fff10, bx),
+ CE(bx, 12fff10, 1, (RR), bx),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
/* Note: blx has 2 variants; the .value coded here is for
BLX(2). Only this variant has conditional execution. */
- CE(blx, 12fff30, blx),
- CE(clz, 16f0f10, clz),
- UE(bkpt, 1200070, bkpt),
- UF(ldc2, c100000, lstc),
- UF(ldc2l, c500000, lstc),
- UF(stc2, c000000, lstc),
- UF(stc2l, c400000, lstc),
- UF(cdp2, e000000, cdp),
- UF(mcr2, e000010, co_reg),
- UF(mrc2, e100010, co_reg),
+ CE(blx, 12fff30, 1, (RR_EXr), blx),
+ CE(clz, 16f0f10, 2, (RRnpc, RRnpc), clz),
+ UE(bkpt, 1200070, 1, (obIffff), bkpt),
+ UF(ldc2, c100000, 3, (RCP, RCN, ADDR), lstc),
+ UF(ldc2l, c500000, 3, (RCP, RCN, ADDR), lstc),
+ UF(stc2, c000000, 3, (RCP, RCN, ADDR), lstc),
+ UF(stc2l, c400000, 3, (RCP, RCN, ADDR), lstc),
+ UF(cdp2, e000000, 6, (RCP, bI15, RCN, RCN, RCN, obI7), cdp),
+ UF(mcr2, e000010, 6, (RCP, bI7, RR, RCN, RCN, obI7), co_reg),
+ UF(mrc2, e100010, 6, (RCP, bI7, RR, RCN, RCN, obI7), co_reg),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
- CE(smlabb, 1000080, smla),
- CE(smlatb, 10000a0, smla),
- CE(smlabt, 10000c0, smla),
- CE(smlatt, 10000e0, smla),
+ CE(smlabb, 1000080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlatb, 10000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlabt, 10000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlatt, 10000e0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlawb, 1200080, smla),
- CE(smlawt, 12000c0, smla),
+ CE(smlawb, 1200080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlawt, 12000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
- CE(smlalbb, 1400080, smlal),
- CE(smlaltb, 14000a0, smlal),
- CE(smlalbt, 14000c0, smlal),
- CE(smlaltt, 14000e0, smlal),
+ CE(smlalbb, 1400080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlaltb, 14000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlalbt, 14000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlaltt, 14000e0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
- CE(smulbb, 1600080, smul),
- CE(smultb, 16000a0, smul),
- CE(smulbt, 16000c0, smul),
- CE(smultt, 16000e0, smul),
+ CE(smulbb, 1600080, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smultb, 16000a0, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smulbt, 16000c0, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smultt, 16000e0, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(smulwb, 12000a0, smul),
- CE(smulwt, 12000e0, smul),
+ CE(smulwb, 12000a0, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smulwt, 12000e0, 3, (RRnpc, RRnpc, RRnpc), smul),
- CE(qadd, 1000050, qadd),
- CE(qdadd, 1400050, qadd),
- CE(qsub, 1200050, qadd),
- CE(qdsub, 1600050, qadd),
+ CE(qadd, 1000050, 3, (RRnpc, RRnpc, RRnpc), qadd),
+ CE(qdadd, 1400050, 3, (RRnpc, RRnpc, RRnpc), qadd),
+ CE(qsub, 1200050, 3, (RRnpc, RRnpc, RRnpc), qadd),
+ CE(qdsub, 1600050, 3, (RRnpc, RRnpc, RRnpc), qadd),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
- UF(pld, 450f000, pld),
- CM(ldr,d, 00000d0, ldrd),
- CM(str,d, 00000f0, ldrd),
+ UF(pld, 450f000, 1, (ADDR), pld),
+ CM(ldr,d, 00000d0, 2, (RR, ADDR), ldrd),
+ CM(str,d, 00000f0, 2, (RR, ADDR), ldrd),
- CE(mcrr, c400000, co_reg2c),
- CE(mrrc, c500000, co_reg2c),
+ CE(mcrr, c400000, 5, (RCP, bI15, RRnpc, RRnpc, RCN), co_reg2c),
+ CE(mrrc, c500000, 5, (RCP, bI15, RRnpc, RRnpc, RCN), co_reg2c),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
- CE(bxj, 12fff20, bxj),
+ CE(bxj, 12fff20, 1, (RR), bxj),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
- UF(cps, 1020000, cps),
- UF(cpsie, 1080000, cpsi),
- UF(cpsid, 10c0000, cpsi),
- CE(ldrex, 1900f9f, ldrex),
- UF(mcrr2, c400000, co_reg2c),
- UF(mrrc2, c500000, co_reg2c),
- CE(pkhbt, 6800010, pkhbt),
- CE(pkhtb, 6800050, pkhtb),
- CE(qadd16, 6200f10, qadd16),
- CE(qadd8, 6200f90, qadd16),
- CE(qaddsubx, 6200f30, qadd16),
- CE(qsub16, 6200f70, qadd16),
- CE(qsub8, 6200ff0, qadd16),
- CE(qsubaddx, 6200f50, qadd16),
- CE(sadd16, 6100f10, qadd16),
- CE(sadd8, 6100f90, qadd16),
- CE(saddsubx, 6100f30, qadd16),
- CE(shadd16, 6300f10, qadd16),
- CE(shadd8, 6300f90, qadd16),
- CE(shaddsubx, 6300f30, qadd16),
- CE(shsub16, 6300f70, qadd16),
- CE(shsub8, 6300ff0, qadd16),
- CE(shsubaddx, 6300f50, qadd16),
- CE(ssub16, 6100f70, qadd16),
- CE(ssub8, 6100ff0, qadd16),
- CE(ssubaddx, 6100f50, qadd16),
- CE(uadd16, 6500f10, qadd16),
- CE(uadd8, 6500f90, qadd16),
- CE(uaddsubx, 6500f30, qadd16),
- CE(uhadd16, 6700f10, qadd16),
- CE(uhadd8, 6700f90, qadd16),
- CE(uhaddsubx, 6700f30, qadd16),
- CE(uhsub16, 6700f70, qadd16),
- CE(uhsub8, 6700ff0, qadd16),
- CE(uhsubaddx, 6700f50, qadd16),
- CE(uqadd16, 6600f10, qadd16),
- CE(uqadd8, 6600f90, qadd16),
- CE(uqaddsubx, 6600f30, qadd16),
- CE(uqsub16, 6600f70, qadd16),
- CE(uqsub8, 6600ff0, qadd16),
- CE(uqsubaddx, 6600f50, qadd16),
- CE(usub16, 6500f70, qadd16),
- CE(usub8, 6500ff0, qadd16),
- CE(usubaddx, 6500f50, qadd16),
- CE(rev, 6bf0f30, rev),
- CE(rev16, 6bf0fb0, rev),
- CE(revsh, 6ff0fb0, rev),
- UF(rfeia, 8900a00, rfe),
- UF(rfeib, 9900a00, rfe),
- UF(rfeda, 8100a00, rfe),
- UF(rfedb, 9100a00, rfe),
- UF(rfefd, 8900a00, rfe),
- UF(rfefa, 9900a00, rfe),
- UF(rfeea, 8100a00, rfe),
- UF(rfeed, 9100a00, rfe),
- CE(sxtah, 6b00070, sxtah),
- CE(sxtab16, 6800070, sxtah),
- CE(sxtab, 6a00070, sxtah),
- CE(sxth, 6bf0070, sxth),
- CE(sxtb16, 68f0070, sxth),
- CE(sxtb, 6af0070, sxth),
- CE(uxtah, 6f00070, sxtah),
- CE(uxtab16, 6c00070, sxtah),
- CE(uxtab, 6e00070, sxtah),
- CE(uxth, 6ff0070, sxth),
- CE(uxtb16, 6cf0070, sxth),
- CE(uxtb, 6ef0070, sxth),
- CE(sel, 68000b0, qadd16),
- UF(setend, 1010000, setend),
- CE(smlad, 7000010, smla),
- CE(smladx, 7000030, smla),
- CE(smlald, 7400010, smlal),
- CE(smlaldx, 7400030, smlal),
- CE(smlsd, 7000050, smla),
- CE(smlsdx, 7000070, smla),
- CE(smlsld, 7400050, smlal),
- CE(smlsldx, 7400070, smlal),
- CE(smmla, 7500010, smla),
- CE(smmlar, 7500030, smla),
- CE(smmls, 75000d0, smla),
- CE(smmlsr, 75000f0, smla),
- CE(smmul, 750f010, smul),
- CE(smmulr, 750f030, smul),
- CE(smuad, 700f010, smul),
- CE(smuadx, 700f030, smul),
- CE(smusd, 700f050, smul),
- CE(smusdx, 700f070, smul),
- UF(srsia, 8cd0500, srs),
- UF(srsib, 9cd0500, srs),
- UF(srsda, 84d0500, srs),
- UF(srsdb, 94d0500, srs),
- CE(ssat, 6a00010, ssat),
- CE(ssat16, 6a00f30, ssat16),
- CE(strex, 1800f90, strex),
- CE(umaal, 0400090, smlal),
- CE(usad8, 780f010, smul),
- CE(usada8, 7800010, smla),
- CE(usat, 6e00010, usat),
- CE(usat16, 6e00f30, usat16),
+ UF(cps, 1020000, 1, (bI31), cps),
+ UF(cpsie, 1080000, 2, (CPSF, obI31), cpsi),
+ UF(cpsid, 10c0000, 2, (CPSF, obI31), cpsi),
+ CE(ldrex, 1900f9f, 2, (RRnpc, bRRnpc), ldrex),
+ UF(mcrr2, c400000, 5, (RCP, bI15, RRnpc, RRnpc, RCN), co_reg2c),
+ UF(mrrc2, c500000, 5, (RCP, bI15, RRnpc, RRnpc, RCN), co_reg2c),
+ CE(pkhbt, 6800010, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt),
+ CE(pkhtb, 6800050, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb),
+ CE(qadd16, 6200f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(qadd8, 6200f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(qaddsubx, 6200f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(qsub16, 6200f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(qsub8, 6200ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(qsubaddx, 6200f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(sadd16, 6100f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(sadd8, 6100f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(saddsubx, 6100f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shadd16, 6300f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shadd8, 6300f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shaddsubx, 6300f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shsub16, 6300f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shsub8, 6300ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(shsubaddx, 6300f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(ssub16, 6100f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(ssub8, 6100ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(ssubaddx, 6100f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uadd16, 6500f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uadd8, 6500f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uaddsubx, 6500f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhadd16, 6700f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhadd8, 6700f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhaddsubx, 6700f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhsub16, 6700f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhsub8, 6700ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uhsubaddx, 6700f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqadd16, 6600f10, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqadd8, 6600f90, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqaddsubx, 6600f30, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqsub16, 6600f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqsub8, 6600ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(uqsubaddx, 6600f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(usub16, 6500f70, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(usub8, 6500ff0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(usubaddx, 6500f50, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ CE(rev, 6bf0f30, 2, (RRnpc, RRnpc), rev),
+ CE(rev16, 6bf0fb0, 2, (RRnpc, RRnpc), rev),
+ CE(revsh, 6ff0fb0, 2, (RRnpc, RRnpc), rev),
+ UF(rfeia, 8900a00, 1, (RRw), rfe),
+ UF(rfeib, 9900a00, 1, (RRw), rfe),
+ UF(rfeda, 8100a00, 1, (RRw), rfe),
+ UF(rfedb, 9100a00, 1, (RRw), rfe),
+ UF(rfefd, 8900a00, 1, (RRw), rfe),
+ UF(rfefa, 9900a00, 1, (RRw), rfe),
+ UF(rfeea, 8100a00, 1, (RRw), rfe),
+ UF(rfeed, 9100a00, 1, (RRw), rfe),
+ CE(sxtah, 6b00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(sxtab16, 6800070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(sxtab, 6a00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(sxth, 6bf0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(sxtb16, 68f0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(sxtb, 6af0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(uxtah, 6f00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(uxtab16, 6c00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(uxtab, 6e00070, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah),
+ CE(uxth, 6ff0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(uxtb16, 6cf0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(uxtb, 6ef0070, 3, (RRnpc, RRnpc, oROR), sxth),
+ CE(sel, 68000b0, 3, (RRnpc, RRnpc, RRnpc), qadd16),
+ UF(setend, 1010000, 1, (ENDI), setend),
+ CE(smlad, 7000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smladx, 7000030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlald, 7400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlaldx, 7400030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlsd, 7000050, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlsdx, 7000070, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smlsld, 7400050, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smlsldx, 7400070, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(smmla, 7500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smmlar, 7500030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smmls, 75000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smmlsr, 75000f0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(smmul, 750f010, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smmulr, 750f030, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smuad, 700f010, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smuadx, 700f030, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smusd, 700f050, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(smusdx, 700f070, 3, (RRnpc, RRnpc, RRnpc), smul),
+ UF(srsia, 8cd0500, 1, (I31w), srs),
+ UF(srsib, 9cd0500, 1, (I31w), srs),
+ UF(srsda, 84d0500, 1, (I31w), srs),
+ UF(srsdb, 94d0500, 1, (I31w), srs),
+ CE(ssat, 6a00010, 4, (RRnpc, I32, RRnpc, oSHllar), ssat),
+ CE(ssat16, 6a00f30, 3, (RRnpc, I16, RRnpc), ssat16),
+ CE(strex, 1800f90, 3, (RRnpc, RRnpc, bRRnpc), strex),
+ CE(umaal, 0400090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal),
+ CE(usad8, 780f010, 3, (RRnpc, RRnpc, RRnpc), smul),
+ CE(usada8, 7800010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla),
+ CE(usat, 6e00010, 4, (RRnpc, I31, RRnpc, oSHllar), usat),
+ CE(usat16, 6e00f30, 3, (RRnpc, I15, RRnpc), usat16),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6K
- UF(clrex, 57ff01f, empty),
- CE(ldrexb, 1d00f9f, ldrex),
- CE(ldrexd, 1b00f9f, ldrex),
- CE(ldrexh, 1f00f9f, ldrex),
- CE(sev, 320f004, empty),
- CE(strexb, 1c00f90, strex),
- CE(strexd, 1a00f90, strex),
- CE(strexh, 1e00f90, strex),
- CE(wfe, 320f002, empty),
- CE(wfi, 320f003, empty),
- CE(yield, 320f001, empty),
+ CE(ldrexb, 1d00f9f, 2, (RRnpc, bRRnpc), ldrex),
+ CE(ldrexd, 1b00f9f, 2, (RRnpc, bRRnpc), ldrex),
+ CE(ldrexh, 1f00f9f, 2, (RRnpc, bRRnpc), ldrex),
+ CE(strexb, 1c00f90, 3, (RRnpc, RRnpc, bRRnpc), strex),
+ CE(strexd, 1a00f90, 3, (RRnpc, RRnpc, bRRnpc), strex),
+ CE(strexh, 1e00f90, 3, (RRnpc, RRnpc, bRRnpc), strex),
+ UF(clrex, 57ff01f, 0, (), empty),
+ CE(wfe, 320f002, 0, (), empty),
+ CE(wfi, 320f003, 0, (), empty),
+ CE(yield, 320f001, 0, (), empty),
+ CE(sev, 320f004, 0, (), empty),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6Z
- CE(smi, 1600070, smi),
+ CE(smi, 1600070, 1, (iEXP), smi),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_EXT_V6T2
- CE(bfc, 7c0001f, bfc),
- CE(bfi, 7c00010, bfi),
- CE(mls, 0600090, mls),
- CE(movw, 3000000, mov16),
- CE(movt, 3400000, mov16),
- CE(rbit, 3ff0f30, rbit),
- CE(sbfx, 7a00050, bfx),
- CE(ubfx, 7e00050, bfx),
+ CE(bfc, 7c0001f, 3, (RRnpc, I31, I32), bfc),
+ CE(bfi, 7c00010, 4, (RRnpc, RRnpc_I0, I31, I32), bfi),
+ CE(sbfx, 7a00050, 4, (RR, RR, I31, I32), bfx),
+ CE(ubfx, 7e00050, 4, (RR, RR, I31, I32), bfx),
- CM(ldr,ht, 03000b0, ldsttv4),
- CM(ldr,sht, 03000f0, ldsttv4),
- CM(ldr,sbt, 03000d0, ldsttv4),
- CM(str,ht, 02000b0, ldsttv4),
+ CE(mls, 0600090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
+ CE(movw, 3000000, 2, (RRnpc, Iffff), mov16),
+ CE(movt, 3400000, 2, (RRnpc, Iffff), mov16),
+ CE(rbit, 3ff0f30, 2, (RR, RR), rbit),
+ CM(ldr,ht, 03000b0, 2, (RR, ADDR), ldsttv4),
+ CM(ldr,sht, 03000f0, 2, (RR, ADDR), ldsttv4),
+ CM(ldr,sbt, 03000d0, 2, (RR, ADDR), ldsttv4),
+ CM(str,ht, 02000b0, 2, (RR, ADDR), ldsttv4),
+
#undef ARM_VARIANT
#define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
- CE(wfs, e200110, fpa_ctrl),
- CE(rfs, e300110, fpa_ctrl),
- CE(wfc, e400110, fpa_ctrl),
- CE(rfc, e500110, fpa_ctrl),
+ CE(wfs, e200110, 1, (RR), fpa_ctrl),
+ CE(rfs, e300110, 1, (RR), fpa_ctrl),
+ CE(wfc, e400110, 1, (RR), fpa_ctrl),
+ CE(rfc, e500110, 1, (RR), fpa_ctrl),
- CM(ldf,s, c100100, fpa_ldst),
- CM(ldf,d, c108100, fpa_ldst),
- CM(ldf,e, c500100, fpa_ldst),
- CM(ldf,p, c508100, fpa_ldst),
+ CM(ldf,s, c100100, 2, (RF, ADDR), fpa_ldst),
+ CM(ldf,d, c108100, 2, (RF, ADDR), fpa_ldst),
+ CM(ldf,e, c500100, 2, (RF, ADDR), fpa_ldst),
+ CM(ldf,p, c508100, 2, (RF, ADDR), fpa_ldst),
- CM(stf,s, c000100, fpa_ldst),
- CM(stf,d, c008100, fpa_ldst),
- CM(stf,e, c400100, fpa_ldst),
- CM(stf,p, c408100, fpa_ldst),
+ CM(stf,s, c000100, 2, (RF, ADDR), fpa_ldst),
+ CM(stf,d, c008100, 2, (RF, ADDR), fpa_ldst),
+ CM(stf,e, c400100, 2, (RF, ADDR), fpa_ldst),
+ CM(stf,p, c408100, 2, (RF, ADDR), fpa_ldst),
- CM(mvf,s, e008100, fpa_monadic),
- CM(mvf,sp, e008120, fpa_monadic),
- CM(mvf,sm, e008140, fpa_monadic),
- CM(mvf,sz, e008160, fpa_monadic),
- CM(mvf,d, e008180, fpa_monadic),
- CM(mvf,dp, e0081a0, fpa_monadic),
- CM(mvf,dm, e0081c0, fpa_monadic),
- CM(mvf,dz, e0081e0, fpa_monadic),
- CM(mvf,e, e088100, fpa_monadic),
- CM(mvf,ep, e088120, fpa_monadic),
- CM(mvf,em, e088140, fpa_monadic),
- CM(mvf,ez, e088160, fpa_monadic),
+ CM(mvf,s, e008100, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,sp, e008120, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,sm, e008140, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,sz, e008160, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,d, e008180, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,dp, e0081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,dm, e0081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,dz, e0081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,e, e088100, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,ep, e088120, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,em, e088140, 2, (RF, RF_IF), fpa_monadic),
+ CM(mvf,ez, e088160, 2, (RF, RF_IF), fpa_monadic),
- CM(mnf,s, e108100, fpa_monadic),
- CM(mnf,sp, e108120, fpa_monadic),
- CM(mnf,sm, e108140, fpa_monadic),
- CM(mnf,sz, e108160, fpa_monadic),
- CM(mnf,d, e108180, fpa_monadic),
- CM(mnf,dp, e1081a0, fpa_monadic),
- CM(mnf,dm, e1081c0, fpa_monadic),
- CM(mnf,dz, e1081e0, fpa_monadic),
- CM(mnf,e, e188100, fpa_monadic),
- CM(mnf,ep, e188120, fpa_monadic),
- CM(mnf,em, e188140, fpa_monadic),
- CM(mnf,ez, e188160, fpa_monadic),
+ CM(mnf,s, e108100, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,sp, e108120, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,sm, e108140, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,sz, e108160, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,d, e108180, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,dp, e1081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,dm, e1081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,dz, e1081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,e, e188100, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,ep, e188120, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,em, e188140, 2, (RF, RF_IF), fpa_monadic),
+ CM(mnf,ez, e188160, 2, (RF, RF_IF), fpa_monadic),
- CM(abs,s, e208100, fpa_monadic),
- CM(abs,sp, e208120, fpa_monadic),
- CM(abs,sm, e208140, fpa_monadic),
- CM(abs,sz, e208160, fpa_monadic),
- CM(abs,d, e208180, fpa_monadic),
- CM(abs,dp, e2081a0, fpa_monadic),
- CM(abs,dm, e2081c0, fpa_monadic),
- CM(abs,dz, e2081e0, fpa_monadic),
- CM(abs,e, e288100, fpa_monadic),
- CM(abs,ep, e288120, fpa_monadic),
- CM(abs,em, e288140, fpa_monadic),
- CM(abs,ez, e288160, fpa_monadic),
+ CM(abs,s, e208100, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,sp, e208120, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,sm, e208140, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,sz, e208160, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,d, e208180, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,dp, e2081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,dm, e2081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,dz, e2081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,e, e288100, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,ep, e288120, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,em, e288140, 2, (RF, RF_IF), fpa_monadic),
+ CM(abs,ez, e288160, 2, (RF, RF_IF), fpa_monadic),
- CM(rnd,s, e308100, fpa_monadic),
- CM(rnd,sp, e308120, fpa_monadic),
- CM(rnd,sm, e308140, fpa_monadic),
- CM(rnd,sz, e308160, fpa_monadic),
- CM(rnd,d, e308180, fpa_monadic),
- CM(rnd,dp, e3081a0, fpa_monadic),
- CM(rnd,dm, e3081c0, fpa_monadic),
- CM(rnd,dz, e3081e0, fpa_monadic),
- CM(rnd,e, e388100, fpa_monadic),
- CM(rnd,ep, e388120, fpa_monadic),
- CM(rnd,em, e388140, fpa_monadic),
- CM(rnd,ez, e388160, fpa_monadic),
+ CM(rnd,s, e308100, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,sp, e308120, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,sm, e308140, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,sz, e308160, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,d, e308180, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,dp, e3081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,dm, e3081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,dz, e3081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,e, e388100, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,ep, e388120, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,em, e388140, 2, (RF, RF_IF), fpa_monadic),
+ CM(rnd,ez, e388160, 2, (RF, RF_IF), fpa_monadic),
- CM(sqt,s, e408100, fpa_monadic),
- CM(sqt,sp, e408120, fpa_monadic),
- CM(sqt,sm, e408140, fpa_monadic),
- CM(sqt,sz, e408160, fpa_monadic),
- CM(sqt,d, e408180, fpa_monadic),
- CM(sqt,dp, e4081a0, fpa_monadic),
- CM(sqt,dm, e4081c0, fpa_monadic),
- CM(sqt,dz, e4081e0, fpa_monadic),
- CM(sqt,e, e488100, fpa_monadic),
- CM(sqt,ep, e488120, fpa_monadic),
- CM(sqt,em, e488140, fpa_monadic),
- CM(sqt,ez, e488160, fpa_monadic),
+ CM(sqt,s, e408100, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,sp, e408120, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,sm, e408140, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,sz, e408160, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,d, e408180, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,dp, e4081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,dm, e4081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,dz, e4081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,e, e488100, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,ep, e488120, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,em, e488140, 2, (RF, RF_IF), fpa_monadic),
+ CM(sqt,ez, e488160, 2, (RF, RF_IF), fpa_monadic),
- CM(log,s, e508100, fpa_monadic),
- CM(log,sp, e508120, fpa_monadic),
- CM(log,sm, e508140, fpa_monadic),
- CM(log,sz, e508160, fpa_monadic),
- CM(log,d, e508180, fpa_monadic),
- CM(log,dp, e5081a0, fpa_monadic),
- CM(log,dm, e5081c0, fpa_monadic),
- CM(log,dz, e5081e0, fpa_monadic),
- CM(log,e, e588100, fpa_monadic),
- CM(log,ep, e588120, fpa_monadic),
- CM(log,em, e588140, fpa_monadic),
- CM(log,ez, e588160, fpa_monadic),
+ CM(log,s, e508100, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,sp, e508120, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,sm, e508140, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,sz, e508160, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,d, e508180, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,dp, e5081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,dm, e5081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,dz, e5081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,e, e588100, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,ep, e588120, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,em, e588140, 2, (RF, RF_IF), fpa_monadic),
+ CM(log,ez, e588160, 2, (RF, RF_IF), fpa_monadic),
- CM(lgn,s, e608100, fpa_monadic),
- CM(lgn,sp, e608120, fpa_monadic),
- CM(lgn,sm, e608140, fpa_monadic),
- CM(lgn,sz, e608160, fpa_monadic),
- CM(lgn,d, e608180, fpa_monadic),
- CM(lgn,dp, e6081a0, fpa_monadic),
- CM(lgn,dm, e6081c0, fpa_monadic),
- CM(lgn,dz, e6081e0, fpa_monadic),
- CM(lgn,e, e688100, fpa_monadic),
- CM(lgn,ep, e688120, fpa_monadic),
- CM(lgn,em, e688140, fpa_monadic),
- CM(lgn,ez, e688160, fpa_monadic),
+ CM(lgn,s, e608100, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,sp, e608120, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,sm, e608140, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,sz, e608160, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,d, e608180, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,dp, e6081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,dm, e6081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,dz, e6081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,e, e688100, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,ep, e688120, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,em, e688140, 2, (RF, RF_IF), fpa_monadic),
+ CM(lgn,ez, e688160, 2, (RF, RF_IF), fpa_monadic),
- CM(exp,s, e708100, fpa_monadic),
- CM(exp,sp, e708120, fpa_monadic),
- CM(exp,sm, e708140, fpa_monadic),
- CM(exp,sz, e708160, fpa_monadic),
- CM(exp,d, e708180, fpa_monadic),
- CM(exp,dp, e7081a0, fpa_monadic),
- CM(exp,dm, e7081c0, fpa_monadic),
- CM(exp,dz, e7081e0, fpa_monadic),
- CM(exp,e, e788100, fpa_monadic),
- CM(exp,ep, e788120, fpa_monadic),
- CM(exp,em, e788140, fpa_monadic),
- CM(exp,dz, e788160, fpa_monadic),
+ CM(exp,s, e708100, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,sp, e708120, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,sm, e708140, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,sz, e708160, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,d, e708180, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,dp, e7081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,dm, e7081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,dz, e7081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,e, e788100, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,ep, e788120, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,em, e788140, 2, (RF, RF_IF), fpa_monadic),
+ CM(exp,dz, e788160, 2, (RF, RF_IF), fpa_monadic),
- CM(sin,s, e808100, fpa_monadic),
- CM(sin,sp, e808120, fpa_monadic),
- CM(sin,sm, e808140, fpa_monadic),
- CM(sin,sz, e808160, fpa_monadic),
- CM(sin,d, e808180, fpa_monadic),
- CM(sin,dp, e8081a0, fpa_monadic),
- CM(sin,dm, e8081c0, fpa_monadic),
- CM(sin,dz, e8081e0, fpa_monadic),
- CM(sin,e, e888100, fpa_monadic),
- CM(sin,ep, e888120, fpa_monadic),
- CM(sin,em, e888140, fpa_monadic),
- CM(sin,ez, e888160, fpa_monadic),
+ CM(sin,s, e808100, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,sp, e808120, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,sm, e808140, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,sz, e808160, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,d, e808180, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,dp, e8081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,dm, e8081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,dz, e8081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,e, e888100, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,ep, e888120, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,em, e888140, 2, (RF, RF_IF), fpa_monadic),
+ CM(sin,ez, e888160, 2, (RF, RF_IF), fpa_monadic),
- CM(cos,s, e908100, fpa_monadic),
- CM(cos,sp, e908120, fpa_monadic),
- CM(cos,sm, e908140, fpa_monadic),
- CM(cos,sz, e908160, fpa_monadic),
- CM(cos,d, e908180, fpa_monadic),
- CM(cos,dp, e9081a0, fpa_monadic),
- CM(cos,dm, e9081c0, fpa_monadic),
- CM(cos,dz, e9081e0, fpa_monadic),
- CM(cos,e, e988100, fpa_monadic),
- CM(cos,ep, e988120, fpa_monadic),
- CM(cos,em, e988140, fpa_monadic),
- CM(cos,ez, e988160, fpa_monadic),
+ CM(cos,s, e908100, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,sp, e908120, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,sm, e908140, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,sz, e908160, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,d, e908180, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,dp, e9081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,dm, e9081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,dz, e9081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,e, e988100, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,ep, e988120, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,em, e988140, 2, (RF, RF_IF), fpa_monadic),
+ CM(cos,ez, e988160, 2, (RF, RF_IF), fpa_monadic),
- CM(tan,s, ea08100, fpa_monadic),
- CM(tan,sp, ea08120, fpa_monadic),
- CM(tan,sm, ea08140, fpa_monadic),
- CM(tan,sz, ea08160, fpa_monadic),
- CM(tan,d, ea08180, fpa_monadic),
- CM(tan,dp, ea081a0, fpa_monadic),
- CM(tan,dm, ea081c0, fpa_monadic),
- CM(tan,dz, ea081e0, fpa_monadic),
- CM(tan,e, ea88100, fpa_monadic),
- CM(tan,ep, ea88120, fpa_monadic),
- CM(tan,em, ea88140, fpa_monadic),
- CM(tan,ez, ea88160, fpa_monadic),
+ CM(tan,s, ea08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,sp, ea08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,sm, ea08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,sz, ea08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,d, ea08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,dp, ea081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,dm, ea081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,dz, ea081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,e, ea88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,ep, ea88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,em, ea88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(tan,ez, ea88160, 2, (RF, RF_IF), fpa_monadic),
- CM(asn,s, eb08100, fpa_monadic),
- CM(asn,sp, eb08120, fpa_monadic),
- CM(asn,sm, eb08140, fpa_monadic),
- CM(asn,sz, eb08160, fpa_monadic),
- CM(asn,d, eb08180, fpa_monadic),
- CM(asn,dp, eb081a0, fpa_monadic),
- CM(asn,dm, eb081c0, fpa_monadic),
- CM(asn,dz, eb081e0, fpa_monadic),
- CM(asn,e, eb88100, fpa_monadic),
- CM(asn,ep, eb88120, fpa_monadic),
- CM(asn,em, eb88140, fpa_monadic),
- CM(asn,ez, eb88160, fpa_monadic),
+ CM(asn,s, eb08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,sp, eb08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,sm, eb08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,sz, eb08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,d, eb08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,dp, eb081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,dm, eb081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,dz, eb081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,e, eb88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,ep, eb88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,em, eb88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(asn,ez, eb88160, 2, (RF, RF_IF), fpa_monadic),
- CM(acs,s, ec08100, fpa_monadic),
- CM(acs,sp, ec08120, fpa_monadic),
- CM(acs,sm, ec08140, fpa_monadic),
- CM(acs,sz, ec08160, fpa_monadic),
- CM(acs,d, ec08180, fpa_monadic),
- CM(acs,dp, ec081a0, fpa_monadic),
- CM(acs,dm, ec081c0, fpa_monadic),
- CM(acs,dz, ec081e0, fpa_monadic),
- CM(acs,e, ec88100, fpa_monadic),
- CM(acs,ep, ec88120, fpa_monadic),
- CM(acs,em, ec88140, fpa_monadic),
- CM(acs,ez, ec88160, fpa_monadic),
+ CM(acs,s, ec08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,sp, ec08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,sm, ec08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,sz, ec08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,d, ec08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,dp, ec081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,dm, ec081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,dz, ec081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,e, ec88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,ep, ec88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,em, ec88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(acs,ez, ec88160, 2, (RF, RF_IF), fpa_monadic),
- CM(atn,s, ed08100, fpa_monadic),
- CM(atn,sp, ed08120, fpa_monadic),
- CM(atn,sm, ed08140, fpa_monadic),
- CM(atn,sz, ed08160, fpa_monadic),
- CM(atn,d, ed08180, fpa_monadic),
- CM(atn,dp, ed081a0, fpa_monadic),
- CM(atn,dm, ed081c0, fpa_monadic),
- CM(atn,dz, ed081e0, fpa_monadic),
- CM(atn,e, ed88100, fpa_monadic),
- CM(atn,ep, ed88120, fpa_monadic),
- CM(atn,em, ed88140, fpa_monadic),
- CM(atn,ez, ed88160, fpa_monadic),
+ CM(atn,s, ed08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,sp, ed08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,sm, ed08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,sz, ed08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,d, ed08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,dp, ed081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,dm, ed081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,dz, ed081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,e, ed88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,ep, ed88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,em, ed88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(atn,ez, ed88160, 2, (RF, RF_IF), fpa_monadic),
- CM(urd,s, ee08100, fpa_monadic),
- CM(urd,sp, ee08120, fpa_monadic),
- CM(urd,sm, ee08140, fpa_monadic),
- CM(urd,sz, ee08160, fpa_monadic),
- CM(urd,d, ee08180, fpa_monadic),
- CM(urd,dp, ee081a0, fpa_monadic),
- CM(urd,dm, ee081c0, fpa_monadic),
- CM(urd,dz, ee081e0, fpa_monadic),
- CM(urd,e, ee88100, fpa_monadic),
- CM(urd,ep, ee88120, fpa_monadic),
- CM(urd,em, ee88140, fpa_monadic),
- CM(urd,ez, ee88160, fpa_monadic),
+ CM(urd,s, ee08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,sp, ee08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,sm, ee08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,sz, ee08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,d, ee08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,dp, ee081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,dm, ee081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,dz, ee081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,e, ee88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,ep, ee88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,em, ee88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(urd,ez, ee88160, 2, (RF, RF_IF), fpa_monadic),
- CM(nrm,s, ef08100, fpa_monadic),
- CM(nrm,sp, ef08120, fpa_monadic),
- CM(nrm,sm, ef08140, fpa_monadic),
- CM(nrm,sz, ef08160, fpa_monadic),
- CM(nrm,d, ef08180, fpa_monadic),
- CM(nrm,dp, ef081a0, fpa_monadic),
- CM(nrm,dm, ef081c0, fpa_monadic),
- CM(nrm,dz, ef081e0, fpa_monadic),
- CM(nrm,e, ef88100, fpa_monadic),
- CM(nrm,ep, ef88120, fpa_monadic),
- CM(nrm,em, ef88140, fpa_monadic),
- CM(nrm,ez, ef88160, fpa_monadic),
+ CM(nrm,s, ef08100, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,sp, ef08120, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,sm, ef08140, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,sz, ef08160, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,d, ef08180, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,dp, ef081a0, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,dm, ef081c0, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,dz, ef081e0, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,e, ef88100, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,ep, ef88120, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,em, ef88140, 2, (RF, RF_IF), fpa_monadic),
+ CM(nrm,ez, ef88160, 2, (RF, RF_IF), fpa_monadic),
- CM(adf,s, e000100, fpa_dyadic),
- CM(adf,sp, e000120, fpa_dyadic),
- CM(adf,sm, e000140, fpa_dyadic),
- CM(adf,sz, e000160, fpa_dyadic),
- CM(adf,d, e000180, fpa_dyadic),
- CM(adf,dp, e0001a0, fpa_dyadic),
- CM(adf,dm, e0001c0, fpa_dyadic),
- CM(adf,dz, e0001e0, fpa_dyadic),
- CM(adf,e, e080100, fpa_dyadic),
- CM(adf,ep, e080120, fpa_dyadic),
- CM(adf,em, e080140, fpa_dyadic),
- CM(adf,ez, e080160, fpa_dyadic),
+ CM(adf,s, e000100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,sp, e000120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,sm, e000140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,sz, e000160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,d, e000180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,dp, e0001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,dm, e0001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,dz, e0001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,e, e080100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,ep, e080120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,em, e080140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(adf,ez, e080160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(suf,s, e200100, fpa_dyadic),
- CM(suf,sp, e200120, fpa_dyadic),
- CM(suf,sm, e200140, fpa_dyadic),
- CM(suf,sz, e200160, fpa_dyadic),
- CM(suf,d, e200180, fpa_dyadic),
- CM(suf,dp, e2001a0, fpa_dyadic),
- CM(suf,dm, e2001c0, fpa_dyadic),
- CM(suf,dz, e2001e0, fpa_dyadic),
- CM(suf,e, e280100, fpa_dyadic),
- CM(suf,ep, e280120, fpa_dyadic),
- CM(suf,em, e280140, fpa_dyadic),
- CM(suf,ez, e280160, fpa_dyadic),
+ CM(suf,s, e200100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,sp, e200120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,sm, e200140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,sz, e200160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,d, e200180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,dp, e2001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,dm, e2001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,dz, e2001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,e, e280100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,ep, e280120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,em, e280140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(suf,ez, e280160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rsf,s, e300100, fpa_dyadic),
- CM(rsf,sp, e300120, fpa_dyadic),
- CM(rsf,sm, e300140, fpa_dyadic),
- CM(rsf,sz, e300160, fpa_dyadic),
- CM(rsf,d, e300180, fpa_dyadic),
- CM(rsf,dp, e3001a0, fpa_dyadic),
- CM(rsf,dm, e3001c0, fpa_dyadic),
- CM(rsf,dz, e3001e0, fpa_dyadic),
- CM(rsf,e, e380100, fpa_dyadic),
- CM(rsf,ep, e380120, fpa_dyadic),
- CM(rsf,em, e380140, fpa_dyadic),
- CM(rsf,ez, e380160, fpa_dyadic),
+ CM(rsf,s, e300100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,sp, e300120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,sm, e300140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,sz, e300160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,d, e300180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,dp, e3001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,dm, e3001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,dz, e3001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,e, e380100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,ep, e380120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,em, e380140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rsf,ez, e380160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(muf,s, e100100, fpa_dyadic),
- CM(muf,sp, e100120, fpa_dyadic),
- CM(muf,sm, e100140, fpa_dyadic),
- CM(muf,sz, e100160, fpa_dyadic),
- CM(muf,d, e100180, fpa_dyadic),
- CM(muf,dp, e1001a0, fpa_dyadic),
- CM(muf,dm, e1001c0, fpa_dyadic),
- CM(muf,dz, e1001e0, fpa_dyadic),
- CM(muf,e, e180100, fpa_dyadic),
- CM(muf,ep, e180120, fpa_dyadic),
- CM(muf,em, e180140, fpa_dyadic),
- CM(muf,ez, e180160, fpa_dyadic),
+ CM(muf,s, e100100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,sp, e100120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,sm, e100140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,sz, e100160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,d, e100180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,dp, e1001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,dm, e1001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,dz, e1001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,e, e180100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,ep, e180120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,em, e180140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(muf,ez, e180160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(dvf,s, e400100, fpa_dyadic),
- CM(dvf,sp, e400120, fpa_dyadic),
- CM(dvf,sm, e400140, fpa_dyadic),
- CM(dvf,sz, e400160, fpa_dyadic),
- CM(dvf,d, e400180, fpa_dyadic),
- CM(dvf,dp, e4001a0, fpa_dyadic),
- CM(dvf,dm, e4001c0, fpa_dyadic),
- CM(dvf,dz, e4001e0, fpa_dyadic),
- CM(dvf,e, e480100, fpa_dyadic),
- CM(dvf,ep, e480120, fpa_dyadic),
- CM(dvf,em, e480140, fpa_dyadic),
- CM(dvf,ez, e480160, fpa_dyadic),
+ CM(dvf,s, e400100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,sp, e400120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,sm, e400140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,sz, e400160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,d, e400180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,dp, e4001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,dm, e4001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,dz, e4001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,e, e480100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,ep, e480120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,em, e480140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(dvf,ez, e480160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rdf,s, e500100, fpa_dyadic),
- CM(rdf,sp, e500120, fpa_dyadic),
- CM(rdf,sm, e500140, fpa_dyadic),
- CM(rdf,sz, e500160, fpa_dyadic),
- CM(rdf,d, e500180, fpa_dyadic),
- CM(rdf,dp, e5001a0, fpa_dyadic),
- CM(rdf,dm, e5001c0, fpa_dyadic),
- CM(rdf,dz, e5001e0, fpa_dyadic),
- CM(rdf,e, e580100, fpa_dyadic),
- CM(rdf,ep, e580120, fpa_dyadic),
- CM(rdf,em, e580140, fpa_dyadic),
- CM(rdf,ez, e580160, fpa_dyadic),
+ CM(rdf,s, e500100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,sp, e500120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,sm, e500140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,sz, e500160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,d, e500180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,dp, e5001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,dm, e5001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,dz, e5001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,e, e580100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,ep, e580120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,em, e580140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rdf,ez, e580160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pow,s, e600100, fpa_dyadic),
- CM(pow,sp, e600120, fpa_dyadic),
- CM(pow,sm, e600140, fpa_dyadic),
- CM(pow,sz, e600160, fpa_dyadic),
- CM(pow,d, e600180, fpa_dyadic),
- CM(pow,dp, e6001a0, fpa_dyadic),
- CM(pow,dm, e6001c0, fpa_dyadic),
- CM(pow,dz, e6001e0, fpa_dyadic),
- CM(pow,e, e680100, fpa_dyadic),
- CM(pow,ep, e680120, fpa_dyadic),
- CM(pow,em, e680140, fpa_dyadic),
- CM(pow,ez, e680160, fpa_dyadic),
+ CM(pow,s, e600100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,sp, e600120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,sm, e600140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,sz, e600160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,d, e600180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,dp, e6001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,dm, e6001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,dz, e6001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,e, e680100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,ep, e680120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,em, e680140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pow,ez, e680160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rpw,s, e700100, fpa_dyadic),
- CM(rpw,sp, e700120, fpa_dyadic),
- CM(rpw,sm, e700140, fpa_dyadic),
- CM(rpw,sz, e700160, fpa_dyadic),
- CM(rpw,d, e700180, fpa_dyadic),
- CM(rpw,dp, e7001a0, fpa_dyadic),
- CM(rpw,dm, e7001c0, fpa_dyadic),
- CM(rpw,dz, e7001e0, fpa_dyadic),
- CM(rpw,e, e780100, fpa_dyadic),
- CM(rpw,ep, e780120, fpa_dyadic),
- CM(rpw,em, e780140, fpa_dyadic),
- CM(rpw,ez, e780160, fpa_dyadic),
+ CM(rpw,s, e700100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,sp, e700120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,sm, e700140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,sz, e700160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,d, e700180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,dp, e7001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,dm, e7001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,dz, e7001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,e, e780100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,ep, e780120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,em, e780140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rpw,ez, e780160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(rmf,s, e800100, fpa_dyadic),
- CM(rmf,sp, e800120, fpa_dyadic),
- CM(rmf,sm, e800140, fpa_dyadic),
- CM(rmf,sz, e800160, fpa_dyadic),
- CM(rmf,d, e800180, fpa_dyadic),
- CM(rmf,dp, e8001a0, fpa_dyadic),
- CM(rmf,dm, e8001c0, fpa_dyadic),
- CM(rmf,dz, e8001e0, fpa_dyadic),
- CM(rmf,e, e880100, fpa_dyadic),
- CM(rmf,ep, e880120, fpa_dyadic),
- CM(rmf,em, e880140, fpa_dyadic),
- CM(rmf,ez, e880160, fpa_dyadic),
+ CM(rmf,s, e800100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,sp, e800120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,sm, e800140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,sz, e800160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,d, e800180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,dp, e8001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,dm, e8001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,dz, e8001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,e, e880100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,ep, e880120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,em, e880140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(rmf,ez, e880160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fml,s, e900100, fpa_dyadic),
- CM(fml,sp, e900120, fpa_dyadic),
- CM(fml,sm, e900140, fpa_dyadic),
- CM(fml,sz, e900160, fpa_dyadic),
- CM(fml,d, e900180, fpa_dyadic),
- CM(fml,dp, e9001a0, fpa_dyadic),
- CM(fml,dm, e9001c0, fpa_dyadic),
- CM(fml,dz, e9001e0, fpa_dyadic),
- CM(fml,e, e980100, fpa_dyadic),
- CM(fml,ep, e980120, fpa_dyadic),
- CM(fml,em, e980140, fpa_dyadic),
- CM(fml,ez, e980160, fpa_dyadic),
+ CM(fml,s, e900100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,sp, e900120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,sm, e900140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,sz, e900160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,d, e900180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,dp, e9001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,dm, e9001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,dz, e9001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,e, e980100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,ep, e980120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,em, e980140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fml,ez, e980160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(fdv,s, ea00100, fpa_dyadic),
- CM(fdv,sp, ea00120, fpa_dyadic),
- CM(fdv,sm, ea00140, fpa_dyadic),
- CM(fdv,sz, ea00160, fpa_dyadic),
- CM(fdv,d, ea00180, fpa_dyadic),
- CM(fdv,dp, ea001a0, fpa_dyadic),
- CM(fdv,dm, ea001c0, fpa_dyadic),
- CM(fdv,dz, ea001e0, fpa_dyadic),
- CM(fdv,e, ea80100, fpa_dyadic),
- CM(fdv,ep, ea80120, fpa_dyadic),
- CM(fdv,em, ea80140, fpa_dyadic),
- CM(fdv,ez, ea80160, fpa_dyadic),
+ CM(fdv,s, ea00100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,sp, ea00120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,sm, ea00140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,sz, ea00160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,d, ea00180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,dp, ea001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,dm, ea001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,dz, ea001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,e, ea80100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,ep, ea80120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,em, ea80140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(fdv,ez, ea80160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(frd,s, eb00100, fpa_dyadic),
- CM(frd,sp, eb00120, fpa_dyadic),
- CM(frd,sm, eb00140, fpa_dyadic),
- CM(frd,sz, eb00160, fpa_dyadic),
- CM(frd,d, eb00180, fpa_dyadic),
- CM(frd,dp, eb001a0, fpa_dyadic),
- CM(frd,dm, eb001c0, fpa_dyadic),
- CM(frd,dz, eb001e0, fpa_dyadic),
- CM(frd,e, eb80100, fpa_dyadic),
- CM(frd,ep, eb80120, fpa_dyadic),
- CM(frd,em, eb80140, fpa_dyadic),
- CM(frd,ez, eb80160, fpa_dyadic),
+ CM(frd,s, eb00100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,sp, eb00120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,sm, eb00140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,sz, eb00160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,d, eb00180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,dp, eb001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,dm, eb001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,dz, eb001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,e, eb80100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,ep, eb80120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,em, eb80140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(frd,ez, eb80160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CM(pol,s, ec00100, fpa_dyadic),
- CM(pol,sp, ec00120, fpa_dyadic),
- CM(pol,sm, ec00140, fpa_dyadic),
- CM(pol,sz, ec00160, fpa_dyadic),
- CM(pol,d, ec00180, fpa_dyadic),
- CM(pol,dp, ec001a0, fpa_dyadic),
- CM(pol,dm, ec001c0, fpa_dyadic),
- CM(pol,dz, ec001e0, fpa_dyadic),
- CM(pol,e, ec80100, fpa_dyadic),
- CM(pol,ep, ec80120, fpa_dyadic),
- CM(pol,em, ec80140, fpa_dyadic),
- CM(pol,ez, ec80160, fpa_dyadic),
+ CM(pol,s, ec00100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,sp, ec00120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,sm, ec00140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,sz, ec00160, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,d, ec00180, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,dp, ec001a0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,dm, ec001c0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,dz, ec001e0, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,e, ec80100, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,ep, ec80120, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,em, ec80140, 3, (RF, RF, RF_IF), fpa_dyadic),
+ CM(pol,ez, ec80160, 3, (RF, RF, RF_IF), fpa_dyadic),
- CE(cmf, e90f110, fpa_cmp),
- CM(cmf,e, ed0f110, fpa_cmp),
- CE(cnf, eb0f110, fpa_cmp),
- CM(cnf,e, ef0f110, fpa_cmp),
+ CE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
+ CM(cmf,e, ed0f110, 2, (RF, RF_IF), fpa_cmp),
+ CE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
+ CM(cnf,e, ef0f110, 2, (RF, RF_IF), fpa_cmp),
/* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should
not be an optional suffix, but part of the instruction. To be
compatible, we accept either. */
- CE(cmfe, ed0f110, fpa_cmp),
- CE(cnfe, ef0f110, fpa_cmp),
+ CE(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
+ CE(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
- CM(flt,s, e000110, fpa_from_reg),
- CM(flt,sp, e000130, fpa_from_reg),
- CM(flt,sm, e000150, fpa_from_reg),
- CM(flt,sz, e000170, fpa_from_reg),
- CM(flt,d, e000190, fpa_from_reg),
- CM(flt,dp, e0001b0, fpa_from_reg),
- CM(flt,dm, e0001d0, fpa_from_reg),
- CM(flt,dz, e0001f0, fpa_from_reg),
- CM(flt,e, e080110, fpa_from_reg),
- CM(flt,ep, e080130, fpa_from_reg),
- CM(flt,em, e080150, fpa_from_reg),
- CM(flt,ez, e080170, fpa_from_reg),
+ CM(flt,s, e000110, 2, (RF, RR), fpa_from_reg),
+ CM(flt,sp, e000130, 2, (RF, RR), fpa_from_reg),
+ CM(flt,sm, e000150, 2, (RF, RR), fpa_from_reg),
+ CM(flt,sz, e000170, 2, (RF, RR), fpa_from_reg),
+ CM(flt,d, e000190, 2, (RF, RR), fpa_from_reg),
+ CM(flt,dp, e0001b0, 2, (RF, RR), fpa_from_reg),
+ CM(flt,dm, e0001d0, 2, (RF, RR), fpa_from_reg),
+ CM(flt,dz, e0001f0, 2, (RF, RR), fpa_from_reg),
+ CM(flt,e, e080110, 2, (RF, RR), fpa_from_reg),
+ CM(flt,ep, e080130, 2, (RF, RR), fpa_from_reg),
+ CM(flt,em, e080150, 2, (RF, RR), fpa_from_reg),
+ CM(flt,ez, e080170, 2, (RF, RR), fpa_from_reg),
/* The implementation of the FIX instruction is broken on some
assemblers, in that it accepts a precision specifier as well as a
rounding specifier, despite the fact that this is meaningless.
To be more compatible, we accept it as well, though of course it
does not set any bits. */
- CE(fix, e100110, fpa_to_reg),
- CM(fix,p, e100130, fpa_to_reg),
- CM(fix,m, e100150, fpa_to_reg),
- CM(fix,z, e100170, fpa_to_reg),
- CM(fix,sp, e100130, fpa_to_reg),
- CM(fix,sm, e100150, fpa_to_reg),
- CM(fix,sz, e100170, fpa_to_reg),
- CM(fix,dp, e100130, fpa_to_reg),
- CM(fix,dm, e100150, fpa_to_reg),
- CM(fix,dz, e100170, fpa_to_reg),
- CM(fix,ep, e100130, fpa_to_reg),
- CM(fix,em, e100150, fpa_to_reg),
- CM(fix,ez, e100170, fpa_to_reg),
+ CE(fix, e100110, 2, (RR, RF), fpa_to_reg),
+ CM(fix,p, e100130, 2, (RR, RF), fpa_to_reg),
+ CM(fix,m, e100150, 2, (RR, RF), fpa_to_reg),
+ CM(fix,z, e100170, 2, (RR, RF), fpa_to_reg),
+ CM(fix,sp, e100130, 2, (RR, RF), fpa_to_reg),
+ CM(fix,sm, e100150, 2, (RR, RF), fpa_to_reg),
+ CM(fix,sz, e100170, 2, (RR, RF), fpa_to_reg),
+ CM(fix,dp, e100130, 2, (RR, RF), fpa_to_reg),
+ CM(fix,dm, e100150, 2, (RR, RF), fpa_to_reg),
+ CM(fix,dz, e100170, 2, (RR, RF), fpa_to_reg),
+ CM(fix,ep, e100130, 2, (RR, RF), fpa_to_reg),
+ CM(fix,em, e100150, 2, (RR, RF), fpa_to_reg),
+ CM(fix,ez, e100170, 2, (RR, RF), fpa_to_reg),
/* Instructions that were new with the real FPA, call them V2. */
#undef ARM_VARIANT
#define ARM_VARIANT FPU_FPA_EXT_V2
- CE(lfm, c100200, fpa_ldmstm),
- CM(lfm,fd, c900200, fpa_ldmstm),
- CM(lfm,ea, d100200, fpa_ldmstm),
- CE(sfm, c000200, fpa_ldmstm),
- CM(sfm,fd, d000200, fpa_ldmstm),
- CM(sfm,ea, c800200, fpa_ldmstm),
+ CE(lfm, c100200, 3, (RF, bI4, ADDR), fpa_ldmstm),
+ CM(lfm,fd, c900200, 3, (RF, bI4, ADDR), fpa_ldmstm),
+ CM(lfm,ea, d100200, 3, (RF, bI4, ADDR), fpa_ldmstm),
+ CE(sfm, c000200, 3, (RF, bI4, ADDR), fpa_ldmstm),
+ CM(sfm,fd, d000200, 3, (RF, bI4, ADDR), fpa_ldmstm),
+ CM(sfm,ea, c800200, 3, (RF, bI4, ADDR), fpa_ldmstm),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
/* Moves and type conversions. */
- CE(fcpys, eb00a40, vfp_sp_monadic),
- CE(fmrs, e100a10, vfp_reg_from_sp),
- CE(fmsr, e000a10, vfp_sp_from_reg),
- CE(fmstat, ef1fa10, empty),
- CE(fsitos, eb80ac0, vfp_sp_monadic),
- CE(fuitos, eb80a40, vfp_sp_monadic),
- CE(ftosis, ebd0a40, vfp_sp_monadic),
- CE(ftosizs, ebd0ac0, vfp_sp_monadic),
- CE(ftouis, ebc0a40, vfp_sp_monadic),
- CE(ftouizs, ebc0ac0, vfp_sp_monadic),
- CE(fmrx, ef00a10, vfp_reg_from_ctrl),
- CE(fmxr, ee00a10, vfp_ctrl_from_reg),
+ CE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
+ CE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
+ CE(fmstat, ef1fa10, 0, (), empty),
+ CE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fmrx, ef00a10, 2, (RR, RVC), vfp_reg_from_ctrl),
+ CE(fmxr, ee00a10, 2, (RVC, RR), vfp_ctrl_from_reg),
/* Memory operations. */
- CE(flds, d100a00, vfp_sp_ldst),
- CE(fsts, d000a00, vfp_sp_ldst),
- CE(fldmias, c900a00, vfp_sp_ldstmia),
- CE(fldmfds, c900a00, vfp_sp_ldstmia),
- CE(fldmdbs, d300a00, vfp_sp_ldstmdb),
- CE(fldmeas, d300a00, vfp_sp_ldstmdb),
- CE(fldmiax, c900b00, vfp_xp_ldstmia),
- CE(fldmfdx, c900b00, vfp_xp_ldstmia),
- CE(fldmdbx, d300b00, vfp_xp_ldstmdb),
- CE(fldmeax, d300b00, vfp_xp_ldstmdb),
- CE(fstmias, c800a00, vfp_sp_ldstmia),
- CE(fstmeas, c800a00, vfp_sp_ldstmia),
- CE(fstmdbs, d200a00, vfp_sp_ldstmdb),
- CE(fstmfds, d200a00, vfp_sp_ldstmdb),
- CE(fstmiax, c800b00, vfp_xp_ldstmia),
- CE(fstmeax, c800b00, vfp_xp_ldstmia),
- CE(fstmdbx, d200b00, vfp_xp_ldstmdb),
- CE(fstmfdx, d200b00, vfp_xp_ldstmdb),
+ CE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
+ CE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
+ CE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ CE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ CE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ CE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ CE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ CE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ CE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ CE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ CE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ CE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ CE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ CE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ CE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ CE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ CE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ CE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
/* Monadic operations. */
- CE(fabss, eb00ac0, vfp_sp_monadic),
- CE(fnegs, eb10a40, vfp_sp_monadic),
- CE(fsqrts, eb10ac0, vfp_sp_monadic),
+ CE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
/* Dyadic operations. */
- CE(fadds, e300a00, vfp_sp_dyadic),
- CE(fsubs, e300a40, vfp_sp_dyadic),
- CE(fmuls, e200a00, vfp_sp_dyadic),
- CE(fdivs, e800a00, vfp_sp_dyadic),
- CE(fmacs, e000a00, vfp_sp_dyadic),
- CE(fmscs, e100a00, vfp_sp_dyadic),
- CE(fnmuls, e200a40, vfp_sp_dyadic),
- CE(fnmacs, e000a40, vfp_sp_dyadic),
- CE(fnmscs, e100a40, vfp_sp_dyadic),
+ CE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ CE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
/* Comparisons. */
- CE(fcmps, eb40a40, vfp_sp_monadic),
- CE(fcmpzs, eb50a40, vfp_sp_compare_z),
- CE(fcmpes, eb40ac0, vfp_sp_monadic),
- CE(fcmpezs, eb50ac0, vfp_sp_compare_z),
+ CE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
+ CE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ CE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
/* Moves and type conversions. */
- CE(fcpyd, eb00b40, vfp_dp_monadic),
- CE(fcvtds, eb70ac0, vfp_dp_sp_cvt),
- CE(fcvtsd, eb70bc0, vfp_sp_dp_cvt),
- CE(fmdhr, e200b10, vfp_dp_from_reg),
- CE(fmdlr, e000b10, vfp_dp_from_reg),
- CE(fmrdh, e300b10, vfp_reg_from_dp),
- CE(fmrdl, e100b10, vfp_reg_from_dp),
- CE(fsitod, eb80bc0, vfp_dp_sp_cvt),
- CE(fuitod, eb80b40, vfp_dp_sp_cvt),
- CE(ftosid, ebd0b40, vfp_sp_dp_cvt),
- CE(ftosizd, ebd0bc0, vfp_sp_dp_cvt),
- CE(ftouid, ebc0b40, vfp_sp_dp_cvt),
- CE(ftouizd, ebc0bc0, vfp_sp_dp_cvt),
+ CE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
+ CE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ CE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_from_reg),
+ CE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_from_reg),
+ CE(fmrdh, e300b10, 2, (RR, RVD), vfp_reg_from_dp),
+ CE(fmrdl, e100b10, 2, (RR, RVD), vfp_reg_from_dp),
+ CE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
+ CE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
+ CE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ CE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ CE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ CE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
/* Memory operations. */
- CE(fldd, d100b00, vfp_dp_ldst),
- CE(fstd, d000b00, vfp_dp_ldst),
- CE(fldmiad, c900b00, vfp_dp_ldstmia),
- CE(fldmfdd, c900b00, vfp_dp_ldstmia),
- CE(fldmdbd, d300b00, vfp_dp_ldstmdb),
- CE(fldmead, d300b00, vfp_dp_ldstmdb),
- CE(fstmiad, c800b00, vfp_dp_ldstmia),
- CE(fstmead, c800b00, vfp_dp_ldstmia),
- CE(fstmdbd, d200b00, vfp_dp_ldstmdb),
- CE(fstmfdd, d200b00, vfp_dp_ldstmdb),
+ CE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
+ CE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
+ CE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ CE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ CE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ CE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ CE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ CE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ CE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ CE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
/* Monadic operations. */
- CE(fabsd, eb00bc0, vfp_dp_monadic),
- CE(fnegd, eb10b40, vfp_dp_monadic),
- CE(fsqrtd, eb10bc0, vfp_dp_monadic),
+ CE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_monadic),
/* Dyadic operations. */
- CE(faddd, e300b00, vfp_dp_dyadic),
- CE(fsubd, e300b40, vfp_dp_dyadic),
- CE(fmuld, e200b00, vfp_dp_dyadic),
- CE(fdivd, e800b00, vfp_dp_dyadic),
- CE(fmacd, e000b00, vfp_dp_dyadic),
- CE(fmscd, e100b00, vfp_dp_dyadic),
- CE(fnmuld, e200b40, vfp_dp_dyadic),
- CE(fnmacd, e000b40, vfp_dp_dyadic),
- CE(fnmscd, e100b40, vfp_dp_dyadic),
+ CE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
+ CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_dyadic),
/* Comparisons. */
- CE(fcmpd, eb40b40, vfp_dp_monadic),
- CE(fcmpzd, eb50b40, vfp_dp_compare_z),
- CE(fcmped, eb40bc0, vfp_dp_monadic),
- CE(fcmpezd, eb50bc0, vfp_dp_compare_z),
+ CE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_compare_z),
+ CE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_monadic),
+ CE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_compare_z),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V2
- CE(fmsrr, c400a10, vfp_sp2_from_reg2),
- CE(fmrrs, c500a10, vfp_reg2_from_sp2),
- CE(fmdrr, c400b10, vfp_dp_from_reg2),
- CE(fmrrd, c500b10, vfp_reg2_from_dp),
+ CE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
+ CE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
+ CE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_from_reg2),
+ CE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_reg2_from_dp),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
- CE(mia, e200010, xsc_mia),
- CE(miaph, e280010, xsc_mia),
- CE(miabb, e2c0010, xsc_mia),
- CE(miabt, e2d0010, xsc_mia),
- CE(miatb, e2e0010, xsc_mia),
- CE(miatt, e2f0010, xsc_mia),
- CE(mar, c400000, xsc_mar),
- CE(mra, c500000, xsc_mra),
+ CE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ CE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
+ CE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
- CE(tandcb, e130130, iwmmxt_tandorc),
- CE(tandch, e530130, iwmmxt_tandorc),
- CE(tandcw, e930130, iwmmxt_tandorc),
- CE(tbcstb, e400010, iwmmxt_tbcst),
- CE(tbcsth, e400050, iwmmxt_tbcst),
- CE(tbcstw, e400090, iwmmxt_tbcst),
- CE(textrcb, e130170, iwmmxt_textrc),
- CE(textrch, e530170, iwmmxt_textrc),
- CE(textrcw, e930170, iwmmxt_textrc),
- CE(textrmub, e100070, iwmmxt_textrm),
- CE(textrmuh, e500070, iwmmxt_textrm),
- CE(textrmuw, e900070, iwmmxt_textrm),
- CE(textrmsb, e100078, iwmmxt_textrm),
- CE(textrmsh, e500078, iwmmxt_textrm),
- CE(textrmsw, e900078, iwmmxt_textrm),
- CE(tinsrb, e600010, iwmmxt_tinsr),
- CE(tinsrh, e600050, iwmmxt_tinsr),
- CE(tinsrw, e600090, iwmmxt_tinsr),
- CE(tmcr, e000110, iwmmxt_tmcr),
- CE(tmcrr, c400000, iwmmxt_tmcrr),
- CE(tmia, e200010, iwmmxt_tmia),
- CE(tmiaph, e280010, iwmmxt_tmia),
- CE(tmiabb, e2c0010, iwmmxt_tmia),
- CE(tmiabt, e2d0010, iwmmxt_tmia),
- CE(tmiatb, e2e0010, iwmmxt_tmia),
- CE(tmiatt, e2f0010, iwmmxt_tmia),
- CE(tmovmskb, e100030, iwmmxt_tmovmsk),
- CE(tmovmskh, e500030, iwmmxt_tmovmsk),
- CE(tmovmskw, e900030, iwmmxt_tmovmsk),
- CE(tmrc, e100110, iwmmxt_tmrc),
- CE(tmrrc, c500000, iwmmxt_tmrrc),
- CE(torcb, e130150, iwmmxt_tandorc),
- CE(torch, e530150, iwmmxt_tandorc),
- CE(torcw, e930150, iwmmxt_tandorc),
- CE(waccb, e0001c0, iwmmxt_wrwr),
- CE(wacch, e4001c0, iwmmxt_wrwr),
- CE(waccw, e8001c0, iwmmxt_wrwr),
- CE(waddbss, e300180, iwmmxt_wrwrwr),
- CE(waddb, e000180, iwmmxt_wrwrwr),
- CE(waddbus, e100180, iwmmxt_wrwrwr),
- CE(waddhss, e700180, iwmmxt_wrwrwr),
- CE(waddh, e400180, iwmmxt_wrwrwr),
- CE(waddhus, e500180, iwmmxt_wrwrwr),
- CE(waddwss, eb00180, iwmmxt_wrwrwr),
- CE(waddw, e800180, iwmmxt_wrwrwr),
- CE(waddwus, e900180, iwmmxt_wrwrwr),
- CE(waligni, e000020, iwmmxt_waligni),
- CE(walignr0, e800020, iwmmxt_wrwrwr),
- CE(walignr1, e900020, iwmmxt_wrwrwr),
- CE(walignr2, ea00020, iwmmxt_wrwrwr),
- CE(walignr3, eb00020, iwmmxt_wrwrwr),
- CE(wand, e200000, iwmmxt_wrwrwr),
- CE(wandn, e300000, iwmmxt_wrwrwr),
- CE(wavg2b, e800000, iwmmxt_wrwrwr),
- CE(wavg2br, e900000, iwmmxt_wrwrwr),
- CE(wavg2h, ec00000, iwmmxt_wrwrwr),
- CE(wavg2hr, ed00000, iwmmxt_wrwrwr),
- CE(wcmpeqb, e000060, iwmmxt_wrwrwr),
- CE(wcmpeqh, e400060, iwmmxt_wrwrwr),
- CE(wcmpeqw, e800060, iwmmxt_wrwrwr),
- CE(wcmpgtub, e100060, iwmmxt_wrwrwr),
- CE(wcmpgtuh, e500060, iwmmxt_wrwrwr),
- CE(wcmpgtuw, e900060, iwmmxt_wrwrwr),
- CE(wcmpgtsb, e300060, iwmmxt_wrwrwr),
- CE(wcmpgtsh, e700060, iwmmxt_wrwrwr),
- CE(wcmpgtsw, eb00060, iwmmxt_wrwrwr),
- CE(wldrb, c100000, iwmmxt_wldst),
- CE(wldrh, c500000, iwmmxt_wldst),
- CE(wldrw, c100100, iwmmxt_wldstw),
- CE(wldrd, c500100, iwmmxt_wldst),
- CE(wmacs, e600100, iwmmxt_wrwrwr),
- CE(wmacsz, e700100, iwmmxt_wrwrwr),
- CE(wmacu, e400100, iwmmxt_wrwrwr),
- CE(wmacuz, e500100, iwmmxt_wrwrwr),
- CE(wmadds, ea00100, iwmmxt_wrwrwr),
- CE(wmaddu, e800100, iwmmxt_wrwrwr),
- CE(wmaxsb, e200160, iwmmxt_wrwrwr),
- CE(wmaxsh, e600160, iwmmxt_wrwrwr),
- CE(wmaxsw, ea00160, iwmmxt_wrwrwr),
- CE(wmaxub, e000160, iwmmxt_wrwrwr),
- CE(wmaxuh, e400160, iwmmxt_wrwrwr),
- CE(wmaxuw, e800160, iwmmxt_wrwrwr),
- CE(wminsb, e300160, iwmmxt_wrwrwr),
- CE(wminsh, e700160, iwmmxt_wrwrwr),
- CE(wminsw, eb00160, iwmmxt_wrwrwr),
- CE(wminub, e100160, iwmmxt_wrwrwr),
- CE(wminuh, e500160, iwmmxt_wrwrwr),
- CE(wminuw, e900160, iwmmxt_wrwrwr),
- CE(wmov, e000000, iwmmxt_wmov),
- CE(wmulsm, e300100, iwmmxt_wrwrwr),
- CE(wmulsl, e200100, iwmmxt_wrwrwr),
- CE(wmulum, e100100, iwmmxt_wrwrwr),
- CE(wmulul, e000100, iwmmxt_wrwrwr),
- CE(wor, e000000, iwmmxt_wrwrwr),
- CE(wpackhss, e700080, iwmmxt_wrwrwr),
- CE(wpackhus, e500080, iwmmxt_wrwrwr),
- CE(wpackwss, eb00080, iwmmxt_wrwrwr),
- CE(wpackwus, e900080, iwmmxt_wrwrwr),
- CE(wpackdss, ef00080, iwmmxt_wrwrwr),
- CE(wpackdus, ed00080, iwmmxt_wrwrwr),
- CE(wrorh, e700040, iwmmxt_wrwrwr),
- CE(wrorhg, e700148, iwmmxt_wrwrwcg),
- CE(wrorw, eb00040, iwmmxt_wrwrwr),
- CE(wrorwg, eb00148, iwmmxt_wrwrwcg),
- CE(wrord, ef00040, iwmmxt_wrwrwr),
- CE(wrordg, ef00148, iwmmxt_wrwrwcg),
- CE(wsadb, e000120, iwmmxt_wrwrwr),
- CE(wsadbz, e100120, iwmmxt_wrwrwr),
- CE(wsadh, e400120, iwmmxt_wrwrwr),
- CE(wsadhz, e500120, iwmmxt_wrwrwr),
- CE(wshufh, e0001e0, iwmmxt_wshufh),
- CE(wsllh, e500040, iwmmxt_wrwrwr),
- CE(wsllhg, e500148, iwmmxt_wrwrwcg),
- CE(wsllw, e900040, iwmmxt_wrwrwr),
- CE(wsllwg, e900148, iwmmxt_wrwrwcg),
- CE(wslld, ed00040, iwmmxt_wrwrwr),
- CE(wslldg, ed00148, iwmmxt_wrwrwcg),
- CE(wsrah, e400040, iwmmxt_wrwrwr),
- CE(wsrahg, e400148, iwmmxt_wrwrwcg),
- CE(wsraw, e800040, iwmmxt_wrwrwr),
- CE(wsrawg, e800148, iwmmxt_wrwrwcg),
- CE(wsrad, ec00040, iwmmxt_wrwrwr),
- CE(wsradg, ec00148, iwmmxt_wrwrwcg),
- CE(wsrlh, e600040, iwmmxt_wrwrwr),
- CE(wsrlhg, e600148, iwmmxt_wrwrwcg),
- CE(wsrlw, ea00040, iwmmxt_wrwrwr),
- CE(wsrlwg, ea00148, iwmmxt_wrwrwcg),
- CE(wsrld, ee00040, iwmmxt_wrwrwr),
- CE(wsrldg, ee00148, iwmmxt_wrwrwcg),
- CE(wstrb, c000000, iwmmxt_wldst),
- CE(wstrh, c400000, iwmmxt_wldst),
- CE(wstrw, c000100, iwmmxt_wldstw),
- CE(wstrd, c400100, iwmmxt_wldst),
- CE(wsubbss, e3001a0, iwmmxt_wrwrwr),
- CE(wsubb, e0001a0, iwmmxt_wrwrwr),
- CE(wsubbus, e1001a0, iwmmxt_wrwrwr),
- CE(wsubhss, e7001a0, iwmmxt_wrwrwr),
- CE(wsubh, e4001a0, iwmmxt_wrwrwr),
- CE(wsubhus, e5001a0, iwmmxt_wrwrwr),
- CE(wsubwss, eb001a0, iwmmxt_wrwrwr),
- CE(wsubw, e8001a0, iwmmxt_wrwrwr),
- CE(wsubwus, e9001a0, iwmmxt_wrwrwr),
- CE(wunpckehub,e0000c0, iwmmxt_wrwr),
- CE(wunpckehuh,e4000c0, iwmmxt_wrwr),
- CE(wunpckehuw,e8000c0, iwmmxt_wrwr),
- CE(wunpckehsb,e2000c0, iwmmxt_wrwr),
- CE(wunpckehsh,e6000c0, iwmmxt_wrwr),
- CE(wunpckehsw,ea000c0, iwmmxt_wrwr),
- CE(wunpckihb, e1000c0, iwmmxt_wrwrwr),
- CE(wunpckihh, e5000c0, iwmmxt_wrwrwr),
- CE(wunpckihw, e9000c0, iwmmxt_wrwrwr),
- CE(wunpckelub,e0000e0, iwmmxt_wrwr),
- CE(wunpckeluh,e4000e0, iwmmxt_wrwr),
- CE(wunpckeluw,e8000e0, iwmmxt_wrwr),
- CE(wunpckelsb,e2000e0, iwmmxt_wrwr),
- CE(wunpckelsh,e6000e0, iwmmxt_wrwr),
- CE(wunpckelsw,ea000e0, iwmmxt_wrwr),
- CE(wunpckilb, e1000e0, iwmmxt_wrwrwr),
- CE(wunpckilh, e5000e0, iwmmxt_wrwrwr),
- CE(wunpckilw, e9000e0, iwmmxt_wrwrwr),
- CE(wxor, e100000, iwmmxt_wrwrwr),
- CE(wzero, e300000, iwmmxt_wzero),
+ CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
+ CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
+ CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
+ CE(tbcstb, e400010, 2, (RR, RIWR), iwmmxt_tbcst),
+ CE(tbcsth, e400050, 2, (RR, RIWR), iwmmxt_tbcst),
+ CE(tbcstw, e400090, 2, (RR, RIWR), iwmmxt_tbcst),
+ CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
+ CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
+ CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
+ CE(textrmub, e100070, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmuh, e500070, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmuw, e900070, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmsb, e100078, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmsh, e500078, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmsw, e900078, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
+ CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
+ CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
+ CE(tmcr, e000110, 2, (RIWC, RR), iwmmxt_tmcr),
+ CE(tmcrr, c400000, 3, (RIWR, RR, RR), iwmmxt_tmcrr),
+ CE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ CE(tmovmskb, e100030, 2, (RR, RIWR), iwmmxt_tmovmsk),
+ CE(tmovmskh, e500030, 2, (RR, RIWR), iwmmxt_tmovmsk),
+ CE(tmovmskw, e900030, 2, (RR, RIWR), iwmmxt_tmovmsk),
+ CE(tmrc, e100110, 2, (RR, RIWC), iwmmxt_tmrc),
+ CE(tmrrc, c500000, 3, (RR, RR, RIWR), iwmmxt_tmrrc),
+ CE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
+ CE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
+ CE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
+ CE(waccb, e0001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wacch, e4001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(waccw, e8001c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
+ CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wand, e200000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
+ CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
+ CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wor, e000000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
+ CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), iwmmxt_wrwrwcg),
+ CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
+ CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), iwmmxt_wrwr),
+ CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), iwmmxt_wrwrwr),
+ CE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
- CE(cfldrs, c100400, mav_ldst_1),
- CE(cfldrd, c500400, mav_ldst_2),
- CE(cfldr32, c100500, mav_ldst_3),
- CE(cfldr64, c500500, mav_ldst_4),
- CE(cfstrs, c000400, mav_ldst_1),
- CE(cfstrd, c400400, mav_ldst_2),
- CE(cfstr32, c000500, mav_ldst_3),
- CE(cfstr64, c400500, mav_ldst_4),
- CE(cfmvsr, e000450, mav_binops_2a),
- CE(cfmvrs, e100450, mav_binops_1a),
- CE(cfmvdlr, e000410, mav_binops_2b),
- CE(cfmvrdl, e100410, mav_binops_1b),
- CE(cfmvdhr, e000430, mav_binops_2b),
- CE(cfmvrdh, e100430, mav_binops_1b),
- CE(cfmv64lr, e000510, mav_binops_2c),
- CE(cfmvr64l, e100510, mav_binops_1c),
- CE(cfmv64hr, e000530, mav_binops_2c),
- CE(cfmvr64h, e100530, mav_binops_1c),
- CE(cfmval32, e200440, mav_binops_3a),
- CE(cfmv32al, e100440, mav_binops_3b),
- CE(cfmvam32, e200460, mav_binops_3a),
- CE(cfmv32am, e100460, mav_binops_3b),
- CE(cfmvah32, e200480, mav_binops_3a),
- CE(cfmv32ah, e100480, mav_binops_3b),
- CE(cfmva32, e2004a0, mav_binops_3a),
- CE(cfmv32a, e1004a0, mav_binops_3b),
- CE(cfmva64, e2004c0, mav_binops_3c),
- CE(cfmv64a, e1004c0, mav_binops_3d),
- CE(cfmvsc32, e2004e0, mav_dspsc_1),
- CE(cfmv32sc, e1004e0, mav_dspsc_2),
- CE(cfcpys, e000400, mav_binops_1d),
- CE(cfcpyd, e000420, mav_binops_1e),
- CE(cfcvtsd, e000460, mav_binops_1f),
- CE(cfcvtds, e000440, mav_binops_1g),
- CE(cfcvt32s, e000480, mav_binops_1h),
- CE(cfcvt32d, e0004a0, mav_binops_1i),
- CE(cfcvt64s, e0004c0, mav_binops_1j),
- CE(cfcvt64d, e0004e0, mav_binops_1k),
- CE(cfcvts32, e100580, mav_binops_1l),
- CE(cfcvtd32, e1005a0, mav_binops_1m),
- CE(cftruncs32,e1005c0, mav_binops_1l),
- CE(cftruncd32,e1005e0, mav_binops_1m),
- CE(cfrshl32, e000550, mav_triple_4a),
- CE(cfrshl64, e000570, mav_triple_4b),
- CE(cfsh32, e000500, mav_shift_1),
- CE(cfsh64, e200500, mav_shift_2),
- CE(cfcmps, e100490, mav_triple_5a),
- CE(cfcmpd, e1004b0, mav_triple_5b),
- CE(cfcmp32, e100590, mav_triple_5c),
- CE(cfcmp64, e1005b0, mav_triple_5d),
- CE(cfabss, e300400, mav_binops_1d),
- CE(cfabsd, e300420, mav_binops_1e),
- CE(cfnegs, e300440, mav_binops_1d),
- CE(cfnegd, e300460, mav_binops_1e),
- CE(cfadds, e300480, mav_triple_5e),
- CE(cfaddd, e3004a0, mav_triple_5f),
- CE(cfsubs, e3004c0, mav_triple_5e),
- CE(cfsubd, e3004e0, mav_triple_5f),
- CE(cfmuls, e100400, mav_triple_5e),
- CE(cfmuld, e100420, mav_triple_5f),
- CE(cfabs32, e300500, mav_binops_1n),
- CE(cfabs64, e300520, mav_binops_1o),
- CE(cfneg32, e300540, mav_binops_1n),
- CE(cfneg64, e300560, mav_binops_1o),
- CE(cfadd32, e300580, mav_triple_5g),
- CE(cfadd64, e3005a0, mav_triple_5h),
- CE(cfsub32, e3005c0, mav_triple_5g),
- CE(cfsub64, e3005e0, mav_triple_5h),
- CE(cfmul32, e100500, mav_triple_5g),
- CE(cfmul64, e100520, mav_triple_5h),
- CE(cfmac32, e100540, mav_triple_5g),
- CE(cfmsc32, e100560, mav_triple_5g),
- CE(cfmadd32, e000600, mav_quad_6a),
- CE(cfmsub32, e100600, mav_quad_6a),
- CE(cfmadda32, e200600, mav_quad_6b),
- CE(cfmsuba32, e300600, mav_quad_6b),
+ CE(cfldrs, c100400, 2, (RMF, ADDR), mav_ldst),
+ CE(cfldrd, c500400, 2, (RMD, ADDR), mav_ldst),
+ CE(cfldr32, c100500, 2, (RMFX, ADDR), mav_ldst),
+ CE(cfldr64, c500500, 2, (RMDX, ADDR), mav_ldst),
+ CE(cfstrs, c000400, 2, (RMF, ADDR), mav_ldst),
+ CE(cfstrd, c400400, 2, (RMD, ADDR), mav_ldst),
+ CE(cfstr32, c000500, 2, (RMFX, ADDR), mav_ldst),
+ CE(cfstr64, c400500, 2, (RMDX, ADDR), mav_ldst),
+ CE(cfmvsr, e000450, 2, (RMF, RR), mav_binops_2),
+ CE(cfmvrs, e100450, 2, (RR, RMF), mav_binops_1),
+ CE(cfmvdlr, e000410, 2, (RMD, RR), mav_binops_2),
+ CE(cfmvrdl, e100410, 2, (RR, RMD), mav_binops_1),
+ CE(cfmvdhr, e000430, 2, (RMD, RR), mav_binops_2),
+ CE(cfmvrdh, e100430, 2, (RR, RMD), mav_binops_1),
+ CE(cfmv64lr, e000510, 2, (RMDX, RR), mav_binops_2),
+ CE(cfmvr64l, e100510, 2, (RR, RMDX), mav_binops_1),
+ CE(cfmv64hr, e000530, 2, (RMDX, RR), mav_binops_2),
+ CE(cfmvr64h, e100530, 2, (RR, RMDX), mav_binops_1),
+ CE(cfmval32, e200440, 2, (RMAX, RMFX), mav_binops_1),
+ CE(cfmv32al, e100440, 2, (RMFX, RMAX), mav_binops_1),
+ CE(cfmvam32, e200460, 2, (RMAX, RMFX), mav_binops_1),
+ CE(cfmv32am, e100460, 2, (RMFX, RMAX), mav_binops_1),
+ CE(cfmvah32, e200480, 2, (RMAX, RMFX), mav_binops_1),
+ CE(cfmv32ah, e100480, 2, (RMFX, RMAX), mav_binops_1),
+ CE(cfmva32, e2004a0, 2, (RMAX, RMFX), mav_binops_1),
+ CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), mav_binops_1),
+ CE(cfmva64, e2004c0, 2, (RMAX, RMDX), mav_binops_1),
+ CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), mav_binops_1),
+ CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc_1),
+ CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), mav_dspsc_0),
+ CE(cfcpys, e000400, 2, (RMF, RMF), mav_binops_1),
+ CE(cfcpyd, e000420, 2, (RMD, RMD), mav_binops_1),
+ CE(cfcvtsd, e000460, 2, (RMD, RMF), mav_binops_1),
+ CE(cfcvtds, e000440, 2, (RMF, RMD), mav_binops_1),
+ CE(cfcvt32s, e000480, 2, (RMF, RMFX), mav_binops_1),
+ CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), mav_binops_1),
+ CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), mav_binops_1),
+ CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), mav_binops_1),
+ CE(cfcvts32, e100580, 2, (RMFX, RMF), mav_binops_1),
+ CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), mav_binops_1),
+ CE(cftruncs32,e1005c0, 2, (RMFX, RMF), mav_binops_1),
+ CE(cftruncd32,e1005e0, 2, (RMFX, RMD), mav_binops_1),
+ CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple_1),
+ CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple_1),
+ CE(cfsh32, e000500, 3, (RMFX, RMFX, Is63), mav_shift),
+ CE(cfsh64, e200500, 3, (RMDX, RMDX, Is63), mav_shift),
+ CE(cfcmps, e100490, 3, (RR, RMF, RMF), mav_triple_2),
+ CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), mav_triple_2),
+ CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), mav_triple_2),
+ CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), mav_triple_2),
+ CE(cfabss, e300400, 2, (RMF, RMF), mav_binops_1),
+ CE(cfabsd, e300420, 2, (RMD, RMD), mav_binops_1),
+ CE(cfnegs, e300440, 2, (RMF, RMF), mav_binops_1),
+ CE(cfnegd, e300460, 2, (RMD, RMD), mav_binops_1),
+ CE(cfadds, e300480, 3, (RMF, RMF, RMF), mav_triple_2),
+ CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), mav_triple_2),
+ CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), mav_triple_2),
+ CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), mav_triple_2),
+ CE(cfmuls, e100400, 3, (RMF, RMF, RMF), mav_triple_2),
+ CE(cfmuld, e100420, 3, (RMD, RMD, RMD), mav_triple_2),
+ CE(cfabs32, e300500, 2, (RMFX, RMFX), mav_binops_1),
+ CE(cfabs64, e300520, 2, (RMDX, RMDX), mav_binops_1),
+ CE(cfneg32, e300540, 2, (RMFX, RMFX), mav_binops_1),
+ CE(cfneg64, e300560, 2, (RMDX, RMDX), mav_binops_1),
+ CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), mav_triple_2),
+ CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), mav_triple_2),
+ CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), mav_triple_2),
+ CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), mav_triple_2),
+ CE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
+ CE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
+ CE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
+ CE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
};
#undef ARM_VARIANT
#undef CE
@@ -8578,96 +7913,96 @@
/* Thumb instructions are substantially simpler, there being no conditional
suffix or infix. */
-#define TI(mnem, opcode, tenc) \
- { #mnem, 0x ## opcode, THUMB_VARIANT, do_ ## tenc }
+#define TI(mnem, opc, nops, ops, tenc) \
+ { #mnem, 0x ## opc, THUMB_VARIANT, OPERANDS##nops ops, do_ ## tenc }
static const struct asm_opcode tinsns[] =
{
#define THUMB_VARIANT ARM_EXT_V4T /* Thumb v1 (ARMv4T). */
- TI(adc, 4140, t_arit),
- TI(add, 0000, t_add_sub),
- TI(and, 4000, t_arit),
- TI(asr, 4100, t_shift),
- TI(b, e7fe, t_branch12),
- TI(beq, d0fe, t_branch9),
- TI(bne, d1fe, t_branch9),
- TI(bcs, d2fe, t_branch9),
- TI(bhs, d2fe, t_branch9),
- TI(bcc, d3fe, t_branch9),
- TI(bul, d3fe, t_branch9),
- TI(blo, d3fe, t_branch9),
- TI(bmi, d4fe, t_branch9),
- TI(bpl, d5fe, t_branch9),
- TI(bvs, d6fe, t_branch9),
- TI(bvc, d7fe, t_branch9),
- TI(bhi, d8fe, t_branch9),
- TI(bls, d9fe, t_branch9),
- TI(bge, dafe, t_branch9),
- TI(blt, dbfe, t_branch9),
- TI(bgt, dcfe, t_branch9),
- TI(ble, ddfe, t_branch9),
- TI(bal, defe, t_branch9),
- TI(bic, 4380, t_arit),
- TI(bl, f7fffffe, t_branch23),
- TI(bx, 4700, t_bx),
- TI(cmn, 42c0, t_arit),
- TI(cmp, 4280, t_mov_cmp),
- TI(eor, 4040, t_arit),
- TI(ldmia, c800, t_ldmstm),
- TI(ldr, 5800, t_ldst),
- TI(ldrb, 5c00, t_ldst),
- TI(ldrh, 5a00, t_ldst),
- TI(ldrsb, 5600, t_lds),
- TI(ldrsh, 5e00, t_lds),
- TI(ldsb, 5600, t_lds),
- TI(ldsh, 5e00, t_lds),
- TI(lsl, 4080, t_shift),
- TI(lsr, 40c0, t_shift),
- TI(mov, 4600, t_mov_cmp),
- TI(mul, 4340, t_arit),
- TI(mvn, 43c0, t_arit),
- TI(neg, 4240, t_arit),
- TI(orr, 4300, t_arit),
- TI(pop, bc00, t_push_pop),
- TI(push, b400, t_push_pop),
- TI(ror, 41c0, t_arit),
- TI(sbc, 4180, t_arit),
- TI(stmia, c000, t_ldmstm),
- TI(str, 5000, t_ldst),
- TI(strb, 5400, t_ldst),
- TI(strh, 5200, t_ldst),
- TI(swi, df00, t_swi),
- TI(sub, 8000, t_add_sub),
- TI(tst, 4200, t_arit),
+ TI(adc, 4140, 3, (RL, RL, oRL), t_arit),
+ TI(add, 0000, 3, (RR, RR_iEX, oRR_iEX), t_add_sub),
+ TI(and, 4000, 3, (RL, RL, oRL), t_arit),
+ TI(asr, 4100, 3, (RL, RL_iEX, oRL_iEX), t_shift),
+ TI(b, e7fe, 1, (EXP), t_branch12),
+ TI(beq, d0fe, 1, (EXP), t_branch9),
+ TI(bne, d1fe, 1, (EXP), t_branch9),
+ TI(bcs, d2fe, 1, (EXP), t_branch9),
+ TI(bhs, d2fe, 1, (EXP), t_branch9),
+ TI(bcc, d3fe, 1, (EXP), t_branch9),
+ TI(bul, d3fe, 1, (EXP), t_branch9),
+ TI(blo, d3fe, 1, (EXP), t_branch9),
+ TI(bmi, d4fe, 1, (EXP), t_branch9),
+ TI(bpl, d5fe, 1, (EXP), t_branch9),
+ TI(bvs, d6fe, 1, (EXP), t_branch9),
+ TI(bvc, d7fe, 1, (EXP), t_branch9),
+ TI(bhi, d8fe, 1, (EXP), t_branch9),
+ TI(bls, d9fe, 1, (EXP), t_branch9),
+ TI(bge, dafe, 1, (EXP), t_branch9),
+ TI(blt, dbfe, 1, (EXP), t_branch9),
+ TI(bgt, dcfe, 1, (EXP), t_branch9),
+ TI(ble, ddfe, 1, (EXP), t_branch9),
+ TI(bal, defe, 1, (EXP), t_branch9),
+ TI(bic, 4380, 3, (RL, RL, oRL), t_arit),
+ TI(bl, f7fffffe, 1, (EXP), t_branch23),
+ TI(bx, 4700, 1, (RR), t_bx),
+ TI(cmn, 42c0, 3, (RL, RL, oRL), t_arit),
+ TI(cmp, 4280, 2, (RR, RR_iEX), t_mov_cmp),
+ TI(eor, 4040, 3, (RL, RL, oRL), t_arit),
+ TI(ldmia, c800, 2, (RLw, REGLST), t_ldmstm),
+ TI(ldr, 5800, 2, (RL, ADDR), t_ldst),
+ TI(ldrb, 5c00, 2, (RL, ADDR), t_ldst),
+ TI(ldrh, 5a00, 2, (RL, ADDR), t_ldst),
+ TI(ldrsb, 5600, 2, (RL, ADDR), t_lds),
+ TI(ldrsh, 5e00, 2, (RL, ADDR), t_lds),
+ TI(ldsb, 5600, 2, (RL, ADDR), t_lds),
+ TI(ldsh, 5e00, 2, (RL, ADDR), t_lds),
+ TI(lsl, 4080, 3, (RL, RL_iEX, oRL_iEX), t_shift),
+ TI(lsr, 40c0, 3, (RL, RL_iEX, oRL_iEX), t_shift),
+ TI(mov, 4600, 2, (RR, RR_iEX), t_mov_cmp),
+ TI(mul, 4340, 3, (RL, RL, oRL), t_arit),
+ TI(mvn, 43c0, 3, (RL, RL, oRL), t_arit),
+ TI(neg, 4240, 3, (RL, RL, oRL), t_arit),
+ TI(orr, 4300, 3, (RL, RL, oRL), t_arit),
+ TI(pop, bc00, 1, (REGLST), t_push_pop),
+ TI(push, b400, 1, (REGLST), t_push_pop),
+ TI(ror, 41c0, 3, (RL, RL, oRL), t_arit),
+ TI(sbc, 4180, 3, (RL, RL, oRL), t_arit),
+ TI(stmia, c000, 2, (RLw, REGLST), t_ldmstm),
+ TI(str, 5000, 2, (RL, ADDR), t_ldst),
+ TI(strb, 5400, 2, (RL, ADDR), t_ldst),
+ TI(strh, 5200, 2, (RL, ADDR), t_ldst),
+ TI(swi, df00, 1, (EXP), t_swi),
+ TI(sub, 8000, 3, (RR, RR_iEX, oRR_iEX), t_add_sub),
+ TI(tst, 4200, 3, (RL, RL, oRL), t_arit),
/* Pseudo ops: */
- TI(adr, 000f, t_adr),
- TI(nop, 46c0, empty), /* mov r8,r8 */
+ TI(adr, 000f, 2, (RL, EXP), t_adr),
+ TI(nop, 46c0, 0, (), empty), /* mov r8,r8 */
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V5T /* Thumb v2 (ARMv5T). */
- TI(blx, 4780, t_blx),
- TI(bkpt, be00, t_bkpt),
+ TI(blx, 4780, 1, (RR_EX), t_blx),
+ TI(bkpt, be00, 1, (obI255), t_bkpt),
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V6
- TI(cpsie, b660, t_cps),
- TI(cpsid, b670, t_cps),
- TI(cpy, 4600, t_cpy),
- TI(rev, ba00, t_arit),
- TI(rev16, ba40, t_arit),
- TI(revsh, bac0, t_arit),
- TI(setend, b650, t_setend),
- TI(sxth, b200, t_arit),
- TI(sxtb, b240, t_arit),
- TI(uxth, b280, t_arit),
- TI(uxtb, b2c0, t_arit),
+ TI(cpsie, b660, 1, (CPSF), t_cps),
+ TI(cpsid, b670, 1, (CPSF), t_cps),
+ TI(cpy, 4600, 2, (RR, RR), t_cpy),
+ TI(rev, ba00, 3, (RL, RL, oRL), t_arit),
+ TI(rev16, ba40, 3, (RL, RL, oRL), t_arit),
+ TI(revsh, bac0, 3, (RL, RL, oRL), t_arit),
+ TI(setend, b650, 1, (ENDI), t_setend),
+ TI(sxth, b200, 3, (RL, RL, oRL), t_arit),
+ TI(sxtb, b240, 3, (RL, RL, oRL), t_arit),
+ TI(uxth, b280, 3, (RL, RL, oRL), t_arit),
+ TI(uxtb, b2c0, 3, (RL, RL, oRL), t_arit),
#undef THUMB_VARIANT
#define THUMB_VARIANT ARM_EXT_V6K
- TI(sev, bf40, empty),
- TI(wfe, bf20, empty),
- TI(wfi, bf30, empty),
- TI(yield, bf10, empty),
+ TI(sev, bf40, 0, (), empty),
+ TI(wfe, bf20, 0, (), empty),
+ TI(wfi, bf30, 0, (), empty),
+ TI(yield, bf10, 0, (), empty),
};
#undef THUMB_VARIANT
#undef TI