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[PATCH] ARM: Get architecture definitions from opcode/arm.h

From: Richard Earnshaw <rearnsha at buzzard dot freeserve dot co dot uk>
To: binutils at sources dot redhat dot com
Cc: Richard dot Earnshaw at buzzard dot freeserve dot co dot uk
Date: Fri, 16 Jul 2004 23:14:18 +0100
Subject: [PATCH] ARM: Get architecture definitions from opcode/arm.h
Reply-to: Richard dot Earnshaw at buzzard dot freeserve dot co dot uk

As alluded in my previous mail, here are the patches to make gas for ARM 
get its architecture flags from include/opcode/arm.h.

R.

2004-07-16  Richard Earnshaw  <rearnsha@arm.com>

	* config/tc-arm.c: Include include/opcode/arm.h.
	(ARM_EXT_*, ARM_ARCH_*, ARM_ANY, ARM_ALL, COPROC_ANY): Delete.
	(FPU_FPA_EXT_* FPU_VFP_EXT_*, FPU_ANY, FPU_NONE, FPU_MAVERICK): Delete.
	(FPU_ARCH_*): Delete.
	* Makefile.am: Update dependencies.
	* Makefile.in: Regenerate.

? autom4te.cache
Index: Makefile.am
===================================================================
RCS file: /cvs/src/src/gas/Makefile.am,v
retrieving revision 1.91
diff -p -p -r1.91 Makefile.am
*** Makefile.am	7 Jul 2004 17:28:48 -0000	1.91
--- Makefile.am	16 Jul 2004 22:06:07 -0000
*************** DEPTC_arc_elf = $(INCDIR)/symcat.h $(src
*** 1023,1039 ****
    $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
  DEPTC_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
    $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
!   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h
  DEPTC_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
    $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
    $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
    $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
!   $(INCDIR)/obstack.h
  DEPTC_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
    $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
    $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
    $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
!   $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
  DEPTC_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
    $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
    $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
--- 1023,1040 ----
    $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
  DEPTC_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
    $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
!   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h
  DEPTC_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
    $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
    $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
    $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
!   $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h
  DEPTC_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
    $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
    $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
    $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
!   $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
!   $(INCDIR)/opcode/arm.h
  DEPTC_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
    $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
    $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
Index: config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.169
diff -p -p -r1.169 tc-arm.c
*** config/tc-arm.c	2 Jul 2004 11:12:29 -0000	1.169
--- config/tc-arm.c	16 Jul 2004 22:06:35 -0000
***************
*** 36,41 ****
--- 36,43 ----
  #include "symbols.h"
  #include "listing.h"
  
+ #include "opcode/arm.h"
+ 
  #ifdef OBJ_ELF
  #include "elf/arm.h"
  #include "dwarf2dbg.h"
***************
*** 44,122 ****
  /* XXX Set this to 1 after the next binutils release */
  #define WARN_DEPRECATED 0
  
- /* The following bitmasks control CPU extensions:  */
- #define ARM_EXT_V1	 0x00000001	/* All processors (core set).  */
- #define ARM_EXT_V2	 0x00000002	/* Multiply instructions.  */
- #define ARM_EXT_V2S	 0x00000004	/* SWP instructions.       */
- #define ARM_EXT_V3	 0x00000008	/* MSR MRS.                */
- #define ARM_EXT_V3M	 0x00000010	/* Allow long multiplies.  */
- #define ARM_EXT_V4	 0x00000020	/* Allow half word loads.  */
- #define ARM_EXT_V4T	 0x00000040	/* Thumb v1.               */
- #define ARM_EXT_V5	 0x00000080	/* Allow CLZ, etc.         */
- #define ARM_EXT_V5T	 0x00000100	/* Thumb v2.               */
- #define ARM_EXT_V5ExP	 0x00000200	/* DSP core set.           */
- #define ARM_EXT_V5E	 0x00000400	/* DSP Double transfers.   */
- #define ARM_EXT_V5J	 0x00000800	/* Jazelle extension.	   */
- #define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
- 
- /* Co-processor space extensions.  */
- #define ARM_CEXT_XSCALE   0x00800000	/* Allow MIA etc.          */
- #define ARM_CEXT_MAVERICK 0x00400000	/* Use Cirrus/DSP coprocessor.  */
- #define ARM_CEXT_IWMMXT   0x00200000    /* Intel Wireless MMX technology coprocessor.   */
- 
- /* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
-    defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
-    ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE.  To these we add
-    three more to cover cores prior to ARM6.  Finally, there are cores which
-    implement further extensions in the co-processor space.  */
- #define ARM_ARCH_V1			  ARM_EXT_V1
- #define ARM_ARCH_V2	(ARM_ARCH_V1	| ARM_EXT_V2)
- #define ARM_ARCH_V2S	(ARM_ARCH_V2	| ARM_EXT_V2S)
- #define ARM_ARCH_V3	(ARM_ARCH_V2S	| ARM_EXT_V3)
- #define ARM_ARCH_V3M	(ARM_ARCH_V3	| ARM_EXT_V3M)
- #define ARM_ARCH_V4xM	(ARM_ARCH_V3	| ARM_EXT_V4)
- #define ARM_ARCH_V4	(ARM_ARCH_V3M	| ARM_EXT_V4)
- #define ARM_ARCH_V4TxM	(ARM_ARCH_V4xM	| ARM_EXT_V4T)
- #define ARM_ARCH_V4T	(ARM_ARCH_V4	| ARM_EXT_V4T)
- #define ARM_ARCH_V5xM	(ARM_ARCH_V4xM	| ARM_EXT_V5)
- #define ARM_ARCH_V5	(ARM_ARCH_V4	| ARM_EXT_V5)
- #define ARM_ARCH_V5TxM	(ARM_ARCH_V5xM	| ARM_EXT_V4T | ARM_EXT_V5T)
- #define ARM_ARCH_V5T	(ARM_ARCH_V5	| ARM_EXT_V4T | ARM_EXT_V5T)
- #define ARM_ARCH_V5TExP	(ARM_ARCH_V5T	| ARM_EXT_V5ExP)
- #define ARM_ARCH_V5TE	(ARM_ARCH_V5TExP | ARM_EXT_V5E)
- #define ARM_ARCH_V5TEJ	(ARM_ARCH_V5TE	| ARM_EXT_V5J)
- #define ARM_ARCH_V6     (ARM_ARCH_V5TEJ | ARM_EXT_V6)
- 
- /* Processors with specific extensions in the co-processor space.  */
- #define ARM_ARCH_XSCALE	(ARM_ARCH_V5TE	| ARM_CEXT_XSCALE)
- #define ARM_ARCH_IWMMXT	(ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT)
- 
- /* Some useful combinations:  */
- #define ARM_ANY		0x0000ffff	/* Any basic core.  */
- #define ARM_ALL		0x00ffffff	/* Any core + co-processor */
- #define CPROC_ANY	0x00ff0000	/* Any co-processor */
- #define FPU_ANY		0xff000000	/* Note this is ~ARM_ALL.  */
- 
- 
- #define FPU_FPA_EXT_V1	 0x80000000	/* Base FPA instruction set.  */
- #define FPU_FPA_EXT_V2	 0x40000000	/* LFM/SFM.		      */
- #define FPU_VFP_EXT_NONE 0x20000000	/* Use VFP word-ordering.     */
- #define FPU_VFP_EXT_V1xD 0x10000000	/* Base VFP instruction set.  */
- #define FPU_VFP_EXT_V1	 0x08000000	/* Double-precision insns.    */
- #define FPU_VFP_EXT_V2	 0x04000000	/* ARM10E VFPr1.	      */
- #define FPU_MAVERICK	 0x02000000	/* Cirrus Maverick.	      */
- #define FPU_NONE	 0
- 
- #define FPU_ARCH_FPE	 FPU_FPA_EXT_V1
- #define FPU_ARCH_FPA	(FPU_ARCH_FPE | FPU_FPA_EXT_V2)
- 
- #define FPU_ARCH_VFP       FPU_VFP_EXT_NONE
- #define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE)
- #define FPU_ARCH_VFP_V1   (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1)
- #define FPU_ARCH_VFP_V2	  (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2)
- 
- #define FPU_ARCH_MAVERICK  FPU_MAVERICK
- 
  enum arm_float_abi
  {
    ARM_FLOAT_ABI_HARD,
--- 46,51 ----

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