PowerPC 440 mbar and tlbwe instructions

["Zack Weinberg" <zack at codesourcery dot com>]

One of CodeSourcery's clients is complaining that GAS in PPC440 mode
doesn't accept the mbar and tlbwe instructions with the syntax
documented in IBM's 440 chip reference manual.  I have found that GAS
is adhering instead to the specification in Motorola's E500 reference
manual.  The difference in a nutshell:

Mot:     mbar I  # where I = 5-bit immediate constant
IBM:     mbar    # no arguments - same encoding as Motorola's mbar 0

Mot:     tlbwe        # no arguments - encoded as tlbwe
IBM:     tlbwe X,Y,Z  # same as 403/405 - tlbwe 0,0,0 == Motorola tlbwe

(Annoyingly, IBM "mbar" has different semantics from Motorola 
"mbar 0", despite using the same encoding.  I have not been
able to comprehend the documentation for the tlbwe instruction,
so I don't know if it has the same problem.)

(Book E itself implies that both syntaxes are acceptable, but it's
deliberately vague here.)

I cannot simply add new opcode table entries for these instructions
marked PPC440, because -m440 enables both PPC_OPCODE_440 and
PPC_OPCODE_BOOKE so we get a collision and an internal error.
For mbar, the sanest thing to do is mark the MO operand (which is only
used by mbar) PPC_OPERAND_OPTIONAL.  But this will not work for tlbwe,
which has three arguments, all of whose operand tags are used by other
instructions whose syntax should not change.  The only thing I can
think of is to add RAO, RSO, and SHO operand tags.

Comments?

zw

opcodes:
        * ppc-opc.c (MO): Make optional.
        (RAO, RSO, SHO): New optional forms of RA, RS, SH operands.
        (tlbwe): Accept for both PPC403 and BOOKE.  Make all operands optional.
gas/testsuite:
        * gas/ppc/booke.d: Update decoding of mbar instruction.

===================================================================
Index: opcodes/ppc-opc.c
--- opcodes/ppc-opc.c	3 Dec 2003 03:15:14 -0000	1.58
+++ opcodes/ppc-opc.c	10 Dec 2003 02:58:37 -0000
@@ -344,7 +344,7 @@ const struct powerpc_operand powerpc_ope
 
   /* The MO field in an mbar instruction.  */
 #define MO MB6 + 1
-  { 5, 21, 0, 0, 0 },
+  { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 
   /* The NB field in an X form instruction.  The value 32 is stored as
      0.  */
@@ -384,8 +384,12 @@ const struct powerpc_operand powerpc_ope
 #define RAS RAM + 1
   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 
+  /* The RA field of the tlbwe instruction, which is optional.  */
+#define RAO RAS + 1
+  { 5, 16, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
+
   /* The RB field in an X, XO, M, or MDS form instruction.  */
-#define RB RAS + 1
+#define RB RAO + 1
 #define RB_MASK (0x1f << 11)
   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 
@@ -413,8 +417,12 @@ const struct powerpc_operand powerpc_ope
 #define RTQ RSQ + 1
   { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
 
+  /* The RS field of the tlbwe instruction, which is optional.  */
+#define RSO RTQ + 1
+  { 5, 21, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
+
   /* The SH field in an X or M form instruction.  */
-#define SH RTQ + 1
+#define SH RSO + 1
 #define SH_MASK (0x1f << 11)
   { 5, 11, 0, 0, 0 },
 
@@ -423,8 +431,12 @@ const struct powerpc_operand powerpc_ope
 #define SH6_MASK ((0x1f << 11) | (1 << 1))
   { 6, 1, insert_sh6, extract_sh6, 0 },
 
+  /* The SH field of the tlbwe instruction, which is optional.  */
+#define SHO SH6 + 1
+  { 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
+
   /* The SI field in a D form instruction.  */
-#define SI SH6 + 1
+#define SI SHO + 1
   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 
   /* The SI field in a D form instruction when we accept a wide range
@@ -4256,8 +4268,7 @@ const struct powerpc_opcode powerpc_opco
 
 { "tlbwehi", XTLB(31,978,0), XTLB_MASK,	PPC403,		{ RT, RA } },
 { "tlbwelo", XTLB(31,978,1), XTLB_MASK,	PPC403,		{ RT, RA } },
-{ "tlbwe",   X(31,978),	X_MASK,		BOOKE,		{ 0 } },
-{ "tlbwe",   X(31,978),	X_MASK,		PPC403,		{ RS, RA, SH } },
+{ "tlbwe",   X(31,978),	X_MASK,		PPC403|BOOKE,	{ RSO, RAO, SHO } },
 { "tlbld",   X(31,978),	XRTRA_MASK,	PPC,		{ RB } },
 
 { "icbi",    X(31,982),	XRT_MASK,	PPC,		{ RA, RB } },
===================================================================
Index: gas/testsuite/gas/ppc/booke.d
--- gas/testsuite/gas/ppc/booke.d	26 Jul 2003 10:22:01 -0000	1.6
+++ gas/testsuite/gas/ppc/booke.d	10 Dec 2003 02:55:17 -0000
@@ -136,4 +136,4 @@ Disassembly of section \.text:
  1a8:	7d 10 6b 86 	mtdcr	432,r8
  1ac:	7c 00 04 ac 	msync
  1b0:	7c 09 55 ec 	dcba	r9,r10
- 1b4:	7c 00 06 ac 	mbar	0
+ 1b4:	7c 00 06 ac 	mbar