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[patch] ARM gas Floating Point options
- From: Paul Brook <paul at codesourcery dot com>
- To: binutils at sources dot redhat dot com
- Cc: "Mark Mitchell" <mark at codesourcery dot com>,Richard Earnshaw <rearnsha at arm dot com>
- Date: Fri, 5 Dec 2003 13:08:31 +0000
- Subject: [patch] ARM gas Floating Point options
(this time to the right list, and including the patch)
The attached patch adds floating point switches to the gas ARM taget in line
with similar changes to GCC.
Basically it adds -msoft-float and -mhard-float which can work independently
of -mfpu=. The existing -mfpu=soft* have been kept for compatability.
If ok could you also apply, I don't have write access to src.
Paul
2003-12-05 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (FPU_MAVERICK): Define.
(FPU_ARCH_MAVERICK): Define.
(target_soft_float): Define.
(md_begin): Use them.
(arm_opts): Add msoft-float and mhard-float.
(arm_cpus): Use FPU_ARCH_MAVERICK.
(arm_fpus): Add maverick.
* doc/as.texinfo: Document -mhard-float and -msoft-float.
* doc/c-arm.text: Ditto. Menution -fpu=maverick.
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.151
diff -u -p -r1.151 tc-arm.c
--- gas/config/tc-arm.c 22 Nov 2003 02:35:29 -0000 1.151
+++ gas/config/tc-arm.c 5 Dec 2003 12:41:37 -0000
@@ -100,6 +100,7 @@
#define FPU_VFP_EXT_V1xD 0x10000000 /* Base VFP instruction set. */
#define FPU_VFP_EXT_V1 0x08000000 /* Double-precision insns. */
#define FPU_VFP_EXT_V2 0x04000000 /* ARM10E VFPr1. */
+#define FPU_MAVERICK 0x02000000 /* Cirrus Maverick. */
#define FPU_NONE 0
#define FPU_ARCH_FPE FPU_FPA_EXT_V1
@@ -110,6 +111,8 @@
#define FPU_ARCH_VFP_V1 (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1)
#define FPU_ARCH_VFP_V2 (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2)
+#define FPU_ARCH_MAVERICK FPU_MAVERICK
+
/* Types of processor to assemble for. */
#define ARM_1 ARM_ARCH_V1
#define ARM_2 ARM_ARCH_V2
@@ -157,6 +160,8 @@
static unsigned long cpu_variant;
static int target_oabi = 0;
+/* Values are 0=unset (default), 1=soft-float, 2=hard-float. */
+static int target_soft_float = 0;
/* Flags stored in private area of BFD structure. */
static int uses_apcs_26 = FALSE;
@@ -10569,24 +10574,26 @@ md_begin ()
#if defined OBJ_COFF || defined OBJ_ELF
{
unsigned int flags = 0;
-
+
/* Set the flags in the private structure. */
if (uses_apcs_26) flags |= F_APCS26;
if (support_interwork) flags |= F_INTERWORK;
if (uses_apcs_float) flags |= F_APCS_FLOAT;
if (pic_code) flags |= F_PIC;
if ((cpu_variant & FPU_ANY) == FPU_NONE
- || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
- flags |= F_SOFT_FLOAT;
+ || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP /* VFP layout only. */
+ || target_soft_float)
+ {
+ if (target_soft_float == 2)
+ as_bad (_("-mhard-float conflicts with specified fpu"));
+ flags |= F_SOFT_FLOAT;
+ }
/* Using VFP conventions (even if soft-float). */
if (cpu_variant & FPU_VFP_EXT_NONE) flags |= F_VFP_FLOAT;
#if defined OBJ_ELF
- if (cpu_variant & ARM_CEXT_MAVERICK)
- {
- flags &= ~ F_SOFT_FLOAT;
+ if (cpu_variant & FPU_ARCH_MAVERICK)
flags |= EF_ARM_MAVERICK_FLOAT;
- }
#endif
bfd_set_private_flags (stdoutput, flags);
@@ -12011,6 +12018,10 @@ struct arm_option_table arm_opts[] =
{"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
{"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 1,
NULL},
+ {"msoft-float", N_("Disable hardware floating point instructions"),
+ &target_soft_float, 1, NULL},
+ {"mhard-float", N_("Enable hardware floating point instructions"),
+ &target_soft_float, 2, NULL},
/* These are recognized by the assembler, but have no affect on code. */
{"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
@@ -12203,7 +12214,7 @@ static struct arm_cpu_option_table arm_c
{"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2},
{"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
/* Maverick */
- {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_NONE},
+ {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK},
{NULL, 0, 0}
};
@@ -12282,6 +12293,7 @@ static struct arm_fpu_option_table arm_f
{"vfpxd", FPU_ARCH_VFP_V1xD},
{"arm1020t", FPU_ARCH_VFP_V1},
{"arm1020e", FPU_ARCH_VFP_V2},
+ {"maverick", FPU_ARCH_MAVERICK},
{NULL, 0}
};
Index: gas/doc/as.texinfo
===================================================================
RCS file: /cvs/src/src/gas/doc/as.texinfo,v
retrieving revision 1.93
diff -u -p -r1.93 as.texinfo
--- gas/doc/as.texinfo 15 Oct 2003 14:16:29 -0000 1.93
+++ gas/doc/as.texinfo 5 Dec 2003 12:41:39 -0000
@@ -298,6 +298,7 @@ gcc(1), ld(1), and the Info entries for
[@b{-mcpu}=@var{processor}[+@var{extension}@dots{}]]
[@b{-march}=@var{architecture}[+@var{extension}@dots{}]]
[@b{-mfpu}=@var{floating-point-fromat}]
+ [@b{-msoft-float} @b{-mhard-float}]
[@b{-mthumb}]
[@b{-EB}|@b{-EL}]
[@b{-mapcs-32}|@b{-mapcs-26}|@b{-mapcs-float}|
Index: gas/doc/c-arm.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-arm.texi,v
retrieving revision 1.21
diff -u -p -r1.21 c-arm.texi
--- gas/doc/c-arm.texi 13 Nov 2003 14:19:01 -0000 1.21
+++ gas/doc/c-arm.texi 5 Dec 2003 12:41:39 -0000
@@ -161,9 +161,10 @@ The following format options are recogni
@code{vfp10-r0},
@code{vfp9},
@code{vfpxd},
-@code{arm1020t}
+@code{arm1020t},
+@code{arm1020e},
and
-@code{arm1020e}.
+@code{maverick}.
In addition to determining which instructions are assembled, this option
also affects the way in which the @code{.double} assembler directive behaves
@@ -208,6 +209,16 @@ registers rather than integer registers.
@item -mapcs-reentrant
This indicates that the reentrant variant of the APCS should be used.
This variant supports position independent code.
+
+@cindex @code{-msoft-float} command line option, ARM
+@item -msoft-float
+This option specifies that the output generated by the assembler should be
+marked as not using hardware floating point instructions/registers.
+
+@cindex @code{-mhard-float} command line option, ARM
+@item -mhard-float
+This option specifies that the output generated by the assembler should be
+marked as using hardware floating point instructions/registers.
@cindex @code{-EB} command line option, ARM
@item -EB