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arm-gas: support unindexed form of Addressing Mode 5


Hi Guys,

  Intel recently pointed out to me that the ARM port of GAS was not
  supporting the unindexed form of Addressing Mode 5.  So here is a
  patch to add that support.  Plus a patch to support disassembling
  the mode and a patch to adds tests for this to the gas testsuite.

Cheers
        Nick

opcodes/ChangeLog        
2003-08-19  Nick Clifton  <nickc@redhat.com>

	* arm-dis.c (print_insn_arm: case 'A'): Add code to
	disassemble unindexed form of Addressing Mode 5.

gas/ChangeLog
2003-08-19  Nick Clifton  <nickc@redhat.com>

	* config/tc-arm.c (cp_address_required_here): Add code to handle
	unindexed addressing mode.

gas/testsuite/ChangeLog
2003-08-19  Nick Clifton  <nickc@redhat.com>

	* gas/arm/copro.s: Add tests of Addressing Mode 5 (Unindexed).
	* gas/arm/arm.exp: Run copro.s as a dump test.
	* gas/arm/copro.d: New file: expected disassembly of copro.s

Index: opcodes/arm-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/arm-dis.c,v
retrieving revision 1.33
diff -c -3 -p -r1.33 arm-dis.c
*** opcodes/arm-dis.c	18 Jul 2003 11:34:41 -0000	1.33
--- opcodes/arm-dis.c	19 Aug 2003 12:55:56 -0000
*************** print_insn_arm (pc, info, given)
*** 445,453 ****
  
  		    case 'A':
  		      func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
! 		      if ((given & 0x01000000) != 0)
  			{
  			  int offset = given & 0xff;
  			  if (offset)
  			    func (stream, ", %s#%d]%s",
  				  ((given & 0x00800000) == 0 ? "-" : ""),
--- 445,455 ----
  
  		    case 'A':
  		      func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
! 
! 		      if ((given & (1 << 24)) != 0)
  			{
  			  int offset = given & 0xff;
+ 
  			  if (offset)
  			    func (stream, ", %s#%d]%s",
  				  ((given & 0x00800000) == 0 ? "-" : ""),
*************** print_insn_arm (pc, info, given)
*** 459,470 ****
  		      else
  			{
  			  int offset = given & 0xff;
! 			  if (offset)
! 			    func (stream, "], %s#%d",
! 				  ((given & 0x00800000) == 0 ? "-" : ""),
! 				  offset * 4);
  			  else
! 			    func (stream, "]");
  			}
  		      break;
  
--- 461,478 ----
  		      else
  			{
  			  int offset = given & 0xff;
! 
! 			  func (stream, "]");
! 
! 			  if (given & (1 << 21))
! 			    {
! 			      if (offset)
! 				func (stream, ", %s#%d",
! 				      ((given & 0x00800000) == 0 ? "-" : ""),
! 				      offset * 4);
! 			    }
  			  else
! 			    func (stream, ", {%d}", offset);
  			}
  		      break;
  
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.143
diff -c -3 -p -r1.143 tc-arm.c
*** gas/config/tc-arm.c	23 Jul 2003 19:30:39 -0000	1.143
--- gas/config/tc-arm.c	19 Aug 2003 12:56:05 -0000
*************** cp_address_required_here (str, wb_ok)
*** 3329,3350 ****
  	{
  	  p++;
  
! 	  if (wb_ok && skip_past_comma (& p) == SUCCESS)
  	    {
! 	      /* [Rn], #expr  */
! 	      write_back = WRITE_BACK;
  
! 	      if (reg == REG_PC)
  		{
! 		  inst.error = _("pc may not be used in post-increment");
! 		  return FAIL;
  		}
  
! 	      if (cp_address_offset (& p) == FAIL)
  		return FAIL;
  	    }
  	  else
! 	    pre_inc = PRE_INDEX | INDEX_UP;
  	}
        else
  	{
--- 3329,3424 ----
  	{
  	  p++;
  
! 	  skip_whitespace (p);
! 
! 	  if (*p == '\0')
  	    {
! 	      /* As an extension to the official ARM syntax we allow:
! 		 
! 		   [Rn]
! 		   
! 	         as a short hand for:
  
! 		   [Rn,#0]  */
! 	      inst.instruction |= PRE_INDEX | INDEX_UP;
! 	      *str = p;
! 	      return SUCCESS;
! 	    }
! 	  
! 	  if (skip_past_comma (& p) == FAIL)
! 	    {
! 	      inst.error = _("comma expected after closing square bracket");
! 	      return FAIL;
! 	    }
! 
! 	  skip_whitespace (p);
! 
! 	  if (*p == '#')
! 	    {
! 	      if (wb_ok)
  		{
! 		  /* [Rn], #expr  */
! 		  write_back = WRITE_BACK;
! 
! 		  if (reg == REG_PC)
! 		    {
! 		      inst.error = _("pc may not be used in post-increment");
! 		      return FAIL;
! 		    }
! 
! 		  if (cp_address_offset (& p) == FAIL)
! 		    return FAIL;
  		}
+ 	      else
+ 		pre_inc = PRE_INDEX | INDEX_UP;
+ 	    }
+ 	  else if (*p == '{')
+ 	    {
+ 	      int option;
+ 
+ 	      /* [Rn], {<expr>}  */
+ 	      p++;
  
! 	      skip_whitespace (p);
! 
! 	      if (my_get_expression (& inst.reloc.exp, & p))
  		return FAIL;
+ 
+ 	      if (inst.reloc.exp.X_op == O_constant)
+ 		{
+ 		  option = inst.reloc.exp.X_add_number;
+ 
+ 		  if (option > 255 || option < 0)
+ 		    {
+ 		      inst.error = _("'option' field too large");
+ 		      return FAIL;
+ 		    }
+ 
+ 		  skip_whitespace (p);
+ 
+ 		  if (*p != '}')
+ 		    {
+ 		      inst.error = _("'}' expected at end of 'option' field");
+ 		      return FAIL;
+ 		    }
+ 		  else
+ 		    {
+ 		      p++;
+ 		      inst.instruction |= option;
+ 		      inst.instruction |= INDEX_UP;
+ 		    }
+ 		}
+ 	      else
+ 		{
+ 		  inst.error = _("non-constant expressions for 'option' field not supported");
+ 		  return FAIL;
+ 		}
  	    }
  	  else
! 	    {
! 	      inst.error = _("# or { expected after comma");
! 	      return FAIL;	      
! 	    }
  	}
        else
  	{
Index: gas/testsuite/gas/arm/arm.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arm.exp,v
retrieving revision 1.19
diff -c -3 -p -r1.19 arm.exp
*** gas/testsuite/gas/arm/arm.exp	13 Jun 2003 16:45:55 -0000	1.19
--- gas/testsuite/gas/arm/arm.exp	19 Aug 2003 12:56:06 -0000
*************** if {[istarget *arm*-*-*] || [istarget "x
*** 40,46 ****
  
      run_dump_test "arch5tej"
  
!     gas_test "copro.s" "" $stdoptlist "Co processor instructions"
  
      gas_test "immed.s" "" $stdoptlist "immediate expressions"
  
--- 40,46 ----
  
      run_dump_test "arch5tej"
  
!     run_dump_test "copro"
  
      gas_test "immed.s" "" $stdoptlist "immediate expressions"
  
Index: gas/testsuite/gas/arm/copro.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/copro.s,v
retrieving revision 1.1.1.1
diff -c -3 -p -r1.1.1.1 copro.s
*** gas/testsuite/gas/arm/copro.s	3 May 1999 07:28:48 -0000	1.1.1.1
--- gas/testsuite/gas/arm/copro.s	19 Aug 2003 12:56:06 -0000
*************** bar:
*** 22,24 ****
--- 22,41 ----
  
  	mcr	p7, 1, r15, cr1, cr1
  	mcrlt	5, 1, r8, cr2, cr9, 0
+ 
+ 	@ The following patterns test Addressing Mode 5 "Unindexed"
+ 	
+         ldc     3,   c7, [r0], {0}
+         stc     p14, c6, [r1], {1}
+         ldc2    5,   c5, [r2], {2}
+         stc2    p6,  c4, [r3], {3}
+         ldcl    7,   c3, [r4], {4}
+         stcl    p8,  c2, [r5], {5}
+         ldc2l   9,   c1, [r6], {6}
+         stc2l   p10, c0, [r7], {7}
+         ldcl    11,  c8, [r8], {255}
+         stcl    p12, c9, [r9], {254}
+         mrrc    13,   0, r7, r0, cr4
+         mcrr    p14,  0, r7, r0, cr5
+         mrrc    15,  15, r7, r0, cr15
+         mcrr    p14, 15, r7, r0, cr14

*** /dev/null	2003-01-30 10:24:37.000000000 +0000
--- /sources/sourceware/gas/testsuite/gas/arm/copro.d	2003-08-19 13:45:53.000000000 +0100
***************
*** 0 ****
--- 1,39 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: ARM CoProcessor Instructions
+ #as: -march=armv5te -EL
+ 
+ # Test the standard ARM co-processor instructions:
+ 
+ .*: +file format .*arm.*
+ 
+ Disassembly of section .text:
+ 0+000 <[^>]*> ee421103 	dvfs	f1, f2, f3
+ 0+004 <[^>]*> 0e3414a5 	cfadddeq	mvd1, mvd4, mvd5
+ 0+008 <[^>]*> ed939500 	cfldr32	mvfx9, \[r3\]
+ 0+00c <[^>]*> edd1e108 	ldfp	f6, \[r1, #32\]
+ 0+010 <[^>]*> 4db200ff 	ldcmi	0, cr0, \[r2, #1020\]!
+ 0+014 <[^>]*> 5cf31710 	ldcpll	7, cr1, \[r3\], #64
+ 0+018 <[^>]*> ed1f8001 	ldc	0, cr8, \[pc, -#4\]
+ 0+01c <[^>]*> ed830500 	cfstr32	mvfx0, \[r3\]
+ 0+020 <[^>]*> edc0f302 	stcl	3, cr15, \[r0, #8\]
+ 0+024 <[^>]*> 0da2c419 	cfstrseq	mvf12, \[r2, #100\]!
+ 0+028 <[^>]*> 3ca4860c 	stccc	6, cr8, \[r4\], #48
+ 0+02c <[^>]*> ed0f7101 	stfs	f7, \[pc, -#4\]
+ 0+030 <[^>]*> ee715212 	mrc	2, 3, r5, cr1, cr2, \{0\}
+ 0+034 <[^>]*> aeb1f4f2 	mrcge	4, 5, pc, cr1, cr2, \{7\}
+ 0+038 <[^>]*> ee21f711 	mcr	7, 1, pc, cr1, cr1, \{0\}
+ 0+03c <[^>]*> be228519 	cfsh64lt	mvdx8, mvdx2, #9
+ 0+040 <[^>]*> ec907300 	ldc	3, cr7, \[r0\], \{0\}
+ 0+044 <[^>]*> ec816e01 	stc	14, cr6, \[r1\], \{1\}
+ 0+048 <[^>]*> fc925502 	ldc2	5, cr5, \[r2\], \{2\}
+ 0+04c <[^>]*> fc834603 	stc2	6, cr4, \[r3\], \{3\}
+ 0+050 <[^>]*> ecd43704 	ldcl	7, cr3, \[r4\], \{4\}
+ 0+054 <[^>]*> ecc52805 	stcl	8, cr2, \[r5\], \{5\}
+ 0+058 <[^>]*> fcd61906 	ldc2l	9, cr1, \[r6\], \{6\}
+ 0+05c <[^>]*> fcc70a07 	stc2l	10, cr0, \[r7\], \{7\}
+ 0+060 <[^>]*> ecd88bff 	ldcl	11, cr8, \[r8\], \{255\}
+ 0+064 <[^>]*> ecc99cfe 	stcl	12, cr9, \[r9\], \{254\}
+ 0+068 <[^>]*> ec507d04 	mrrc	13, 0, r7, r0, cr4
+ 0+06c <[^>]*> ec407e05 	mcrr	14, 0, r7, r0, cr5
+ 0+070 <[^>]*> ec507fff 	mrrc	15, 15, r7, r0, cr15
+ 0+074 <[^>]*> ec407efe 	mcrr	14, 15, r7, r0, cr14


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