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[Patch] Add XP support to i860 (committed)


This adds support for the XP instructions to gas (enabled with new
option -mxp) and the disassembler, as well as some tests and documentation
covering the new functionality.

2003-05-23  Jason Eckhardt  <jle@rice.edu>
gas:
	* config/tc-i860.c (target_xp): Declare variable.
	(OPTION_XP): Declare macro.
	(md_longopts): Add option -mxp.
	(md_parse_option): Set target_xp.
	(md_show_usage): Add -mxp usage.
	(i860_process_insn): Recognize XP registers bear, ccr, p0-p3.
	(md_assemble): Don't try expansions if XP_ONLY is set.
	* doc/c-i860.texi: Document -mxp option.

gas/testsuite:
	* gas/i860/xp.s: New file.
	* gas/i860/xp.d: New file.

include/opcode:
	* i860.h (expand_type): Add XP_ONLY.
	(scyc.b): New XP instruction.
	(ldio.l): Likewise.
	(ldio.s): Likewise.
	(ldio.b): Likewise.
	(ldint.l): Likewise.
	(ldint.s): Likewise.
	(ldint.b): Likewise.
	(stio.l): Likewise.
	(stio.s): Likewise.
	(stio.b): Likewise.
	(pfld.q): Likewise.

opcodes:
	* i860-dis.c (crnames): Add bear, ccr, p0, p1, p2, p3.
	(print_insn_i860): Grab 4 bits of the control register field
	instead of 3.

Index: gas/config/tc-i860.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-i860.c,v
retrieving revision 1.16
diff -c -3 -p -r1.16 tc-i860.c
*** gas/config/tc-i860.c	18 May 2003 21:24:32 -0000	1.16
--- gas/config/tc-i860.c	24 May 2003 04:12:25 -0000
***************
*** 1,5 ****
  /* tc-i860.c -- Assembler for the Intel i860 architecture.
!    Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002
     Free Software Foundation, Inc.

     Brought back from the dead and completely reworked
--- 1,5 ----
  /* tc-i860.c -- Assembler for the Intel i860 architecture.
!    Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003
     Free Software Foundation, Inc.

     Brought back from the dead and completely reworked
*************** static char last_expand;
*** 88,93 ****
--- 88,96 ----
  /* If true, then warn if any pseudo operations were expanded.  */
  static int target_warn_expand = 0;

+ /* If true, then XP support is enabled.  */
+ static int target_xp = 0;
+
  /* Prototypes.  */
  static void i860_process_insn	PARAMS ((char *));
  static void s_dual		PARAMS ((int));
*************** md_assemble (str)
*** 229,235 ****

    /* Check for expandable flag to produce pseudo-instructions.  This
       is an undesirable feature that should be avoided.  */
!   if (the_insn.expand != 0
        && ! (the_insn.fi[0].fup & (OP_SEL_HA | OP_SEL_H | OP_SEL_L | OP_SEL_GOT
  			    | OP_SEL_GOTOFF | OP_SEL_PLT)))
      {
--- 232,238 ----

    /* Check for expandable flag to produce pseudo-instructions.  This
       is an undesirable feature that should be avoided.  */
!   if (the_insn.expand != 0 && the_insn.expand != XP_ONLY
        && ! (the_insn.fi[0].fup & (OP_SEL_HA | OP_SEL_H | OP_SEL_L | OP_SEL_GOT
  			    | OP_SEL_GOTOFF | OP_SEL_PLT)))
      {
*************** i860_process_insn (str)
*** 687,692 ****
--- 690,732 ----
  		  s += 4;
  		  continue;
  		}
+ 	      /* The remaining control registers are XP only.  */
+ 	      if (target_xp && strncmp (s, "bear", 4) == 0)
+ 		{
+ 		  opcode |= 0x6 << 21;
+ 		  s += 4;
+ 		  continue;
+ 		}
+ 	      if (target_xp && strncmp (s, "ccr", 3) == 0)
+ 		{
+ 		  opcode |= 0x7 << 21;
+ 		  s += 3;
+ 		  continue;
+ 		}
+ 	      if (target_xp && strncmp (s, "p0", 2) == 0)
+ 		{
+ 		  opcode |= 0x8 << 21;
+ 		  s += 2;
+ 		  continue;
+ 		}
+ 	      if (target_xp && strncmp (s, "p1", 2) == 0)
+ 		{
+ 		  opcode |= 0x9 << 21;
+ 		  s += 2;
+ 		  continue;
+ 		}
+ 	      if (target_xp && strncmp (s, "p2", 2) == 0)
+ 		{
+ 		  opcode |= 0xa << 21;
+ 		  s += 2;
+ 		  continue;
+ 		}
+ 	      if (target_xp && strncmp (s, "p3", 2) == 0)
+ 		{
+ 		  opcode |= 0xb << 21;
+ 		  s += 2;
+ 		  continue;
+ 		}
  	      break;

  	    /* 5-bit immediate in src1.  */
*************** i860_process_insn (str)
*** 884,889 ****
--- 924,933 ----
      }

    the_insn.opcode = opcode;
+
+   /* Only recognize XP instructions when the user has requested it.  */
+   if (insn->expand == XP_ONLY && ! target_xp)
+     as_bad (_("Unknown opcode: `%s'"), insn->name);
  }

  static int
*************** const char *md_shortopts = "";
*** 1030,1040 ****
--- 1074,1086 ----
  #define OPTION_EB		(OPTION_MD_BASE + 0)
  #define OPTION_EL		(OPTION_MD_BASE + 1)
  #define OPTION_WARN_EXPAND	(OPTION_MD_BASE + 2)
+ #define OPTION_XP		(OPTION_MD_BASE + 3)

  struct option md_longopts[] = {
    { "EB",	    no_argument, NULL, OPTION_EB },
    { "EL",	    no_argument, NULL, OPTION_EL },
    { "mwarn-expand", no_argument, NULL, OPTION_WARN_EXPAND },
+   { "mxp",	    no_argument, NULL, OPTION_XP },
    { NULL,	    no_argument, NULL, 0 }
  };
  size_t md_longopts_size = sizeof (md_longopts);
*************** md_parse_option (c, arg)
*** 1058,1063 ****
--- 1104,1113 ----
        target_warn_expand = 1;
        break;

+     case OPTION_XP:
+       target_xp = 1;
+       break;
+
  #ifdef OBJ_ELF
      /* SVR4 argument compatibility (-V): print version ID.  */
      case 'V':
*************** md_show_usage (stream)
*** 1084,1090 ****
    fprintf (stream, _("\
    -EL			  generate code for little endian mode (default)\n\
    -EB			  generate code for big endian mode\n\
!   -mwarn-expand		  warn if pseudo operations are expanded\n"));
  #ifdef OBJ_ELF
    /* SVR4 compatibility flags.  */
    fprintf (stream, _("\
--- 1134,1141 ----
    fprintf (stream, _("\
    -EL			  generate code for little endian mode (default)\n\
    -EB			  generate code for big endian mode\n\
!   -mwarn-expand		  warn if pseudo operations are expanded\n\
!   -mxp			  enable i860XP support (disabled by default)\n"));
  #ifdef OBJ_ELF
    /* SVR4 compatibility flags.  */
    fprintf (stream, _("\
Index: gas/doc/c-i860.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-i860.texi,v
retrieving revision 1.4
diff -c -3 -p -r1.4 c-i860.texi
*** gas/doc/c-i860.texi	8 Mar 2001 23:24:26 -0000	1.4
--- gas/doc/c-i860.texi	24 May 2003 04:12:25 -0000
***************
*** 1,4 ****
! @c Copyright 2000 Free Software Foundation, Inc.
  @c This is part of the GAS manual.
  @c For copying conditions, see the file as.texinfo.
  @ifset GENERIC
--- 1,4 ----
! @c Copyright 2000, 2003 Free Software Foundation, Inc.
  @c This is part of the GAS manual.
  @c For copying conditions, see the file as.texinfo.
  @ifset GENERIC
*************** will be expanded into two instructions.
*** 62,67 ****
--- 62,71 ----
  rely on, so this flag can help detect any code where it happens. One
  use of it, for instance, has been to find and eliminate any place
  where @code{gcc} may emit these pseudo-instructions.
+ @item -mxp
+ Enable support for the i860XP instructions and control registers.  By default,
+ this option is disabled so that only the base instruction set (i.e., i860XR)
+ is supported.
  @end table

  @node Directives-i860
*************** default register is @code{r31}.
*** 98,104 ****

  @cindex opcodes, i860
  @cindex i860 opcodes
! All of the Intel i860 machine instructions are supported. Please see
  either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information.
  @subsection Other instruction support (pseudo-instructions)
  For compatibility with some other i860 assemblers, a number of
--- 102,108 ----

  @cindex opcodes, i860
  @cindex i860 opcodes
! All of the Intel i860XR and i860XP machine instructions are supported. Please see
  either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information.
  @subsection Other instruction support (pseudo-instructions)
  For compatibility with some other i860 assemblers, a number of
Index: include/opcode/i860.h
===================================================================
RCS file: /cvs/src/src/include/opcode/i860.h,v
retrieving revision 1.8
diff -c -3 -p -r1.8 i860.h
*** include/opcode/i860.h	21 May 2003 05:06:49 -0000	1.8
--- include/opcode/i860.h	24 May 2003 04:12:53 -0000
*************** struct i860_opcode
*** 40,46 ****

  enum expand_type
  {
!     E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY
  };


--- 40,46 ----

  enum expand_type
  {
!     E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY
  };


*************** static const struct i860_opcode i860_opc
*** 135,140 ****
--- 135,144 ----
  { "pfld.d",	0x64000000, 0x98000007, "L(2),g", E_ADDR },	/* pfld.d #const(isrc2),fdest */
  { "pfld.d",	0x60000001, 0x9c000006, "1(2)++,g", 0 },	/* pfld.d isrc1(isrc2)++,fdest */
  { "pfld.d",	0x64000001, 0x98000006, "L(2)++,g", E_ADDR },	/* pfld.d #const(isrc2)++,fdest */
+ { "pfld.q",	0x60000004, 0x9c000003, "1(2),g", XP_ONLY },	/* pfld.q isrc1(isrc2),fdest */
+ { "pfld.q",	0x64000004, 0x98000003, "L(2),g", XP_ONLY },	/* pfld.q #const(isrc2),fdest */
+ { "pfld.q",	0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY },	/* pfld.q isrc1(isrc2)++,fdest */
+ { "pfld.q",	0x64000005, 0x98000002, "L(2)++,g", XP_ONLY },	/* pfld.q #const(isrc2)++,fdest */

  { "fst.l",	0x28000002, 0xd4000001, "g,1(2)", 0 },	/* fst.l fdest,isrc1(isrc2) */
  { "fst.l",	0x2c000002, 0xd0000001, "g,K(2)", E_ADDR },	/* fst.l fdest,#const(isrc2) */
*************** static const struct i860_opcode i860_opc
*** 204,209 ****
--- 208,223 ----
  { "calli",	0x4c000002, 0xb000001d, "1", E_DELAY },	/* calli isrc1ni */
  { "intovr",	0x4c000004, 0xb000001b, "", 0 },	/* intovr trap on integer overflow */
  { "unlock",	0x4c000007, 0xb0000018, "", 0 },	/* unlock clear BL in dirbase */
+ { "ldio.l",	0x4c000408, 0xb00003f7, "2,d", XP_ONLY },	/* ldio.l isrc2,idest */
+ { "ldio.s",	0x4c000208, 0xb00005f7, "2,d", XP_ONLY },	/* ldio.s isrc2,idest */
+ { "ldio.b",	0x4c000008, 0xb00007f7, "2,d", XP_ONLY },	/* ldio.b isrc2,idest */
+ { "stio.l",	0x4c000409, 0xb00003f6, "1,2", XP_ONLY },	/* stio.l isrc1ni,isrc2 */
+ { "stio.s",	0x4c000209, 0xb00005f6, "1,2", XP_ONLY },	/* stio.s isrc1ni,isrc2 */
+ { "stio.b",	0x4c000009, 0xb00007f6, "1,2", XP_ONLY },	/* stio.b isrc1ni,isrc2 */
+ { "ldint.l",	0x4c00040a, 0xb00003f5, "2,d", XP_ONLY },	/* ldint.l isrc2,idest */
+ { "ldint.s",	0x4c00020a, 0xb00005f5, "2,d", XP_ONLY },	/* ldint.s isrc2,idest */
+ { "ldint.b",	0x4c00000a, 0xb00007f5, "2,d", XP_ONLY },	/* ldint.b isrc2,idest */
+ { "scyc.b",	0x4c00000b, 0xb00007f4, "2", XP_ONLY },		/* scyc.b isrc2 */

  /* CTRL-Format Instructions */
  { "br",		0x68000000, 0x94000000, "l", E_DELAY },	/* br lbroff */
Index: opcodes/i860-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/i860-dis.c,v
retrieving revision 1.3
diff -c -3 -p -r1.3 i860-dis.c
*** opcodes/i860-dis.c	18 May 2003 21:24:33 -0000	1.3
--- opcodes/i860-dis.c	24 May 2003 04:13:06 -0000
***************
*** 1,5 ****
  /* Disassembler for the i860.
!    Copyright 2000 Free Software Foundation, Inc.

     Contributed by Jason Eckhardt <jle@cygnus.com>.

--- 1,5 ----
  /* Disassembler for the i860.
!    Copyright 2000, 2003 Free Software Foundation, Inc.

     Contributed by Jason Eckhardt <jle@cygnus.com>.

*************** static const char *const frnames[] =
*** 37,45 ****
    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};

! /* Control/status register names (encoded as 0..5 in the instruction).  */
  static const char *const crnames[] =
!  {"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""};


  /* Prototypes.  */
--- 37,47 ----
    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};

! /* Control/status register names (encoded as 0..11 in the instruction).
!    Registers bear, ccr, p0, p1, p2 and p3 are XP only.  */
  static const char *const crnames[] =
!  {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
!   "p0", "p1", "p2", "p3", "--", "--", "--", "--" };


  /* Prototypes.  */
*************** print_insn_i860 (memaddr, info)
*** 190,196 ****
  	    /* Control register.  */
  	    case 'c':
  	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
! 				     crnames[(insn >> 21) & 0x7]);
  	      break;

  	    /* 16-bit immediate (sign extend, except for bitwise ops).  */
--- 192,198 ----
  	    /* Control register.  */
  	    case 'c':
  	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
! 				     crnames[(insn >> 21) & 0xf]);
  	      break;

  	    /* 16-bit immediate (sign extend, except for bitwise ops).  */


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