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[patch] *-dis.c: Fix formatting.
- To: binutils at sources dot redhat dot com
- Subject: [patch] *-dis.c: Fix formatting.
- From: Kazu Hirata <kazu at hxi dot com>
Hi,
Attached is a patch to fix formatting of *-dis.c. OK to apply?
Thanks,
Kazu Hirata
2001-08-17 Kazu Hirata <kazu@hxi.com>
* avr-dis.c: Fix formatting.
* i370-dis.c: Likewise.
* i860-dis.c: Likewise.
Index: avr-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/avr-dis.c,v
retrieving revision 1.9
diff -u -r1.9 avr-dis.c
--- avr-dis.c 2001/03/13 22:58:34 1.9
+++ avr-dis.c 2001/08/17 19:22:55
@@ -1,5 +1,5 @@
/* Disassemble AVR instructions.
- Copyright 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by Denis Chertykov <denisc@overta.ru>
@@ -22,9 +22,7 @@
#include "dis-asm.h"
#include "opintl.h"
-
-struct avr_opcodes_s
-{
+struct avr_opcodes_s {
char *name;
char *constraints;
char *opcode;
@@ -37,8 +35,7 @@
#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN, 0},
-struct avr_opcodes_s avr_opcodes[] =
-{
+struct avr_opcodes_s avr_opcodes[] = {
#include "opcode/avr.h"
{NULL, NULL, NULL, 0, 0, 0, 0}
};
@@ -66,7 +63,7 @@
insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */
else
insn = (insn & 0x01f0) >> 4; /* destination register */
-
+
sprintf (buf, "r%d", insn);
break;
@@ -76,11 +73,11 @@
else
sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
break;
-
+
case 'w':
sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
break;
-
+
case 'a':
if (regs)
sprintf (buf, "r%d", 16 + (insn & 7));
@@ -131,11 +128,11 @@
case 'b':
{
unsigned int x;
-
+
x = (insn & 7);
x |= (insn >> 7) & (3 << 3);
x |= (insn >> 8) & (1 << 5);
-
+
if (insn & 0x8)
*buf++ = 'Y';
else
@@ -144,12 +141,12 @@
sprintf (comment, "0x%02x", x);
}
break;
-
+
case 'h':
sprintf (buf, "0x%x",
((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2);
break;
-
+
case 'L':
{
int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
@@ -169,7 +166,7 @@
case 'i':
sprintf (buf, "0x%04X", insn2);
break;
-
+
case 'M':
sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
@@ -180,7 +177,7 @@
fprintf (stderr, _("Internal disassembler error"));
ok = 0;
break;
-
+
case 'K':
{
unsigned int x;
@@ -190,15 +187,15 @@
sprintf (comment, "%d", x);
}
break;
-
+
case 's':
sprintf (buf, "%d", insn & 7);
break;
-
+
case 'S':
sprintf (buf, "%d", (insn >> 4) & 7);
break;
-
+
case 'P':
{
unsigned int x;
@@ -212,24 +209,24 @@
case 'p':
{
unsigned int x;
-
+
x = (insn >> 3) & 0x1f;
sprintf (buf, "0x%02x", x);
sprintf (comment, "%d", x);
}
break;
-
+
case '?':
*buf = '\0';
break;
-
+
default:
sprintf (buf, "??");
fprintf (stderr, _("unknown constraint `%c'"), constraint);
ok = 0;
}
- return ok;
+ return ok;
}
static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));
@@ -241,18 +238,17 @@
{
bfd_byte buffer[2];
int status;
- status = info->read_memory_func(addr, buffer, 2, info);
+ status = info->read_memory_func (addr, buffer, 2, info);
if (status != 0)
{
- info->memory_error_func(status, addr, info);
+ info->memory_error_func (status, addr, info);
return -1;
}
return bfd_getl16 (buffer);
}
-
int
-print_insn_avr(addr, info)
+print_insn_avr (addr, info)
bfd_vma addr;
disassemble_info *info;
{
@@ -268,13 +264,13 @@
if (!initialized)
{
initialized = 1;
-
+
for (opcode = avr_opcodes; opcode->name; opcode++)
{
- char * s;
+ char *s;
unsigned int bin = 0;
unsigned int mask = 0;
-
+
for (s = opcode->opcode; *s; ++s)
{
bin <<= 1;
@@ -289,13 +285,13 @@
}
insn = avrdis_opcode (addr, info);
-
+
for (opcode = avr_opcodes; opcode->name; opcode++)
{
if ((insn & opcode->bin_mask) == opcode->bin_opcode)
break;
}
-
+
/* Special case: disassemble `ldd r,b+0' as `ld r,b', and
`std b+0,r' as `st b,r' (next entry in the table). */
Index: i370-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/i370-dis.c,v
retrieving revision 1.2
diff -u -r1.2 i370-dis.c
--- i370-dis.c 2000/04/14 04:16:58 1.2
+++ i370-dis.c 2001/08/17 19:22:56
@@ -1,6 +1,6 @@
/* i370-dis.c -- Disassemble Instruction 370 (ESA/390) instructions
- Copyright 1994, 2000 Free Software Foundation, Inc.
+ Copyright 1994, 2000, 2001 Free Software Foundation, Inc.
PowerPC version written by Ian Lance Taylor, Cygnus Support
Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org>
@@ -26,8 +26,7 @@
#include "opcode/i370.h"
/* This file provides several disassembler functions, all of which use
- the disassembler interface defined in dis-asm.h.
-*/
+ the disassembler interface defined in dis-asm.h. */
int
print_insn_i370 (memaddr, info)
@@ -47,11 +46,11 @@
return -1;
}
- /* Cast the bytes into the insn (in a host-endian indep way) */
+ /* Cast the bytes into the insn (in a host-endian indep way). */
insn.i[0] = (buffer[0] << 24) & 0xff000000;
insn.i[0] |= (buffer[1] << 16) & 0xff0000;
insn.i[0] |= (buffer[2] << 8) & 0xff00;
- insn.i[0] |= buffer[3] & 0xff;
+ insn.i[0] |= buffer[3] & 0xff;
insn.i[1] = (buffer[4] << 24) & 0xff000000;
insn.i[1] |= (buffer[5] << 16) & 0xff0000;
@@ -65,99 +64,99 @@
i370_insn_t masked;
int invalid;
- /* Mask off operands, and look for a match ... */
+ /* Mask off operands, and look for a match ... */
masked = insn;
if (2 == opcode->len)
- {
- masked.i[0] >>= 16;
- masked.i[0] &= 0xffff;
- }
+ {
+ masked.i[0] >>= 16;
+ masked.i[0] &= 0xffff;
+ }
masked.i[0] &= opcode->mask.i[0];
- if (masked.i[0] != opcode->opcode.i[0]) continue;
+ if (masked.i[0] != opcode->opcode.i[0])
+ continue;
if (6 == opcode->len)
- {
- masked.i[1] &= opcode->mask.i[1];
- if (masked.i[1] != opcode->opcode.i[1]) continue;
- }
+ {
+ masked.i[1] &= opcode->mask.i[1];
+ if (masked.i[1] != opcode->opcode.i[1])
+ continue;
+ }
- /* Found a match. adjust a tad */
+ /* Found a match. Adjust a tad. */
if (2 == opcode->len)
- {
- insn.i[0] >>= 16;
- insn.i[0] &= 0xffff;
- }
+ {
+ insn.i[0] >>= 16;
+ insn.i[0] &= 0xffff;
+ }
/* Make two passes over the operands. First see if any of them
have extraction functions, and, if they do, make sure the
instruction is valid. */
invalid = 0;
for (opindex = opcode->operands; *opindex != 0; opindex++)
- {
- operand = i370_operands + *opindex;
- if (operand->extract)
- (*operand->extract) (insn, &invalid);
- }
- if (invalid) continue;
+ {
+ operand = i370_operands + *opindex;
+ if (operand->extract)
+ (*operand->extract) (insn, &invalid);
+ }
+ if (invalid)
+ continue;
/* The instruction is valid. */
(*info->fprintf_func) (info->stream, "%s", opcode->name);
if (opcode->operands[0] != 0)
- (*info->fprintf_func) (info->stream, "\t");
+ (*info->fprintf_func) (info->stream, "\t");
/* Now extract and print the operands. */
for (opindex = opcode->operands; *opindex != 0; opindex++)
- {
- long value;
+ {
+ long value;
- operand = i370_operands + *opindex;
+ operand = i370_operands + *opindex;
- /* Extract the value from the instruction. */
- if (operand->extract)
- value = (*operand->extract) (insn, (int *) NULL);
- else
- {
- value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1);
- }
-
- /* Print the operand as directed by the flags. */
- if ((operand->flags & I370_OPERAND_OPTIONAL) != 0)
- {
- if (value)
- (*info->fprintf_func) (info->stream, "(r%ld)", value);
- }
- else if ((operand->flags & I370_OPERAND_SBASE) != 0)
- {
- (*info->fprintf_func) (info->stream, "(r%ld)", value);
- }
- else if ((operand->flags & I370_OPERAND_INDEX) != 0)
- {
- if (value)
- (*info->fprintf_func) (info->stream, "(r%ld,", value);
- else
- (*info->fprintf_func) (info->stream, "(,");
- }
- else if ((operand->flags & I370_OPERAND_LENGTH) != 0)
- {
- (*info->fprintf_func) (info->stream, "(%ld,", value);
- }
- else if ((operand->flags & I370_OPERAND_BASE) != 0)
- (*info->fprintf_func) (info->stream, "r%ld)", value);
- else if ((operand->flags & I370_OPERAND_GPR) != 0)
- (*info->fprintf_func) (info->stream, "r%ld,", value);
- else if ((operand->flags & I370_OPERAND_FPR) != 0)
- (*info->fprintf_func) (info->stream, "f%ld,", value);
- else if ((operand->flags & I370_OPERAND_RELATIVE) != 0)
- (*info->fprintf_func) (info->stream, "%ld", value);
- else
- (*info->fprintf_func) (info->stream, " %ld, ", value);
+ /* Extract the value from the instruction. */
+ if (operand->extract)
+ value = (*operand->extract) (insn, (int *) NULL);
+ else
+ {
+ value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1);
+ }
+
+ /* Print the operand as directed by the flags. */
+ if ((operand->flags & I370_OPERAND_OPTIONAL) != 0)
+ {
+ if (value)
+ (*info->fprintf_func) (info->stream, "(r%ld)", value);
+ }
+ else if ((operand->flags & I370_OPERAND_SBASE) != 0)
+ {
+ (*info->fprintf_func) (info->stream, "(r%ld)", value);
+ }
+ else if ((operand->flags & I370_OPERAND_INDEX) != 0)
+ {
+ if (value)
+ (*info->fprintf_func) (info->stream, "(r%ld,", value);
+ else
+ (*info->fprintf_func) (info->stream, "(,");
+ }
+ else if ((operand->flags & I370_OPERAND_LENGTH) != 0)
+ {
+ (*info->fprintf_func) (info->stream, "(%ld,", value);
+ }
+ else if ((operand->flags & I370_OPERAND_BASE) != 0)
+ (*info->fprintf_func) (info->stream, "r%ld)", value);
+ else if ((operand->flags & I370_OPERAND_GPR) != 0)
+ (*info->fprintf_func) (info->stream, "r%ld,", value);
+ else if ((operand->flags & I370_OPERAND_FPR) != 0)
+ (*info->fprintf_func) (info->stream, "f%ld,", value);
+ else if ((operand->flags & I370_OPERAND_RELATIVE) != 0)
+ (*info->fprintf_func) (info->stream, "%ld", value);
+ else
+ (*info->fprintf_func) (info->stream, " %ld, ", value);
+ }
- }
-
return opcode->len;
-
}
-
/* We could not find a match. */
(*info->fprintf_func) (info->stream, ".short 0x%02x%02x", buffer[0], buffer[1]);
Index: i860-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/i860-dis.c,v
retrieving revision 1.2
diff -u -r1.2 i860-dis.c
--- i860-dis.c 2000/08/09 03:33:42 1.2
+++ i860-dis.c 2001/08/17 19:22:56
@@ -1,5 +1,5 @@
/* Disassembler for the i860.
- Copyright 2000 Free Software Foundation, Inc.
+ Copyright 2000, 2001 Free Software Foundation, Inc.
Contributed by Jason Eckhardt <jle@cygnus.com>.
@@ -24,29 +24,30 @@
#define I860_REG_PREFIX "%"
/* Integer register names (encoded as 0..31 in the instruction). */
-static const char *const grnames[] =
- {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
+static const char *const grnames[] = {
+ "r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
- "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+};
/* FP register names (encoded as 0..31 in the instruction). */
-static const char *const frnames[] =
- {"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+static const char *const frnames[] = {
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
- "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
+};
/* Control/status register names (encoded as 0..5 in the instruction). */
-static const char *const crnames[] =
- {"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""};
+static const char *const crnames[] = {
+ "fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""
+};
-
/* Prototypes. */
-static int sign_ext PARAMS((unsigned int, int));
+static int sign_ext PARAMS((unsigned int, int));
static void print_br_address PARAMS((disassemble_info *, bfd_vma, long));
-
/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */
#define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \
|| (op) == 0x34 || (op) == 0x35 \
@@ -55,7 +56,6 @@
|| (op) == 0x33 || (op) == 0x37 \
|| (op) == 0x3b || (op) == 0x3f)
-
/* Sign extend N-bit number. */
static int
sign_ext (x, n)
@@ -68,7 +68,6 @@
return t;
}
-
/* Print a PC-relative branch offset. VAL is the sign extended value
from the branch instruction. */
static void
@@ -78,12 +77,12 @@
long val;
{
- long adj = (long)memaddr + 4 + (val << 2);
+ long adj = (long) memaddr + 4 + (val << 2);
(*info->fprintf_func) (info->stream, "0x%08x", adj);
-
+
/* Attempt to obtain a symbol for the target address. */
-
+
if (info->print_address_func && adj != 0)
{
(*info->fprintf_func) (info->stream, "\t// ");
@@ -91,7 +90,6 @@
}
}
-
/* Print one instruction. */
int
print_insn_i860 (memaddr, info)
@@ -138,7 +136,7 @@
const char *s;
int val;
- /* If this a flop and its dual bit is set, prefix with 'd.'. */
+ /* If this a flop and its dual bit is set, prefix with 'd.'. */
if ((insn & 0xfc000000) == 0x48000000 && (insn & 0x200))
(*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
else
@@ -285,4 +283,3 @@
return sizeof (insn);
}
-