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Re: Why pass HAVE_32BIT_GPRS to OPCODE_IS_MEMBER?
- To: Thiemo Seufer <ica2_ts at csv dot ica dot uni-stuttgart dot de>
- Subject: Re: Why pass HAVE_32BIT_GPRS to OPCODE_IS_MEMBER?
- From: Richard Sandiford <r dot sandiford at redhat dot com>
- Date: 08 Aug 2001 13:22:33 +0100
- Cc: binutils at sources dot redhat dot com
- References: <20010808114854.G3399@rembrandt.csv.ica.uni-stuttgart.de>
Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> writes:
> > In any event, my personal preference is to nuke the gp32 arg to
> > OPCODE_IS_MEMBER, and assemble "move" as a macro, and use -mtune to
> > schedule preference of 'or' vs. 'add'.
>
> Even without the need for 'or' this would be the IMHO cleaner
> solution.
Same here. Is the patch below OK? It uses "addu" instead of "or" with
-mgp32 and -mabi=32. Can change it to use "or" if the concensus is that
that's safer.
Tested on mips-elf mips64-elf and mipsel-elf.
[include/ChangeLog]
* opcode/mips.h (INSN_GP32): Remove.
(OPCODE_IS_MEMBER): Remove gp32 parameter.
(M_MOVE): New macro identifier.
[opcodes/ChangeLog]
* mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32
argument.
* mips-opc.c (G6): Undefine.
(mips_builtin_opcodes): Remove gp32 entry for "move". Add macro
as the first "move" alternative.
[gas/ChangeLog]
* config/tc-mips.c (move_register): New function.
(macro_build): Remove OPCODE_IS_MEMBER's gp32 argument.
(mips_ip): Likewise.
(macro2): Use move_register rather than macro_build for moves.
(mips16_macro): Likewise.
(macro): Likewise. Handle M_MOVE.
[gas/testsuite/ChangeLog]
* gas/mips/mips-gp32-fp32.d: Expect addu rather than or for moves.
* gas/mips/mips-gp32-fp64.d: Likewise.
* gas/mips/mips-abi32.d: Likewise.
* gas/mips/mips-gp32-fp32-pic.d: Likewise.
* gas/mips/mips-gp32-fp64-pic.d: Likewise.
* gas/mips/mips-abi32-pic.d: Likewise.
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.16
diff -u -p -d -r1.16 mips.h
--- include/opcode/mips.h 2001/08/01 11:33:44 1.16
+++ include/opcode/mips.h 2001/08/08 11:48:04
@@ -326,8 +326,6 @@ struct mips_opcode
#define INSN_4100 0x00040000
/* Toshiba R3900 instruction. */
#define INSN_3900 0x00080000
-/* 32-bit code running on a ISA3+ CPU. */
-#define INSN_GP32 0x00100000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -369,15 +367,10 @@ struct mips_opcode
/* Test for membership in an ISA including chip specific ISAs.
INSN is pointer to an element of the opcode table; ISA is the
specified ISA to test against; and CPU is the CPU specific ISA
- to test, or zero if no CPU specific ISA test is desired.
- The gp32 arg is set when you need to force 32-bit register usage on
- a machine with 64-bit registers; see the documentation under -mgp32
- in the MIPS gas docs. */
+ to test, or zero if no CPU specific ISA test is desired. */
-#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \
- ((((insn)->membership & isa) != 0 \
- && ((insn)->membership & INSN_GP32 ? gp32 : 1) \
- ) \
+#define OPCODE_IS_MEMBER(insn, isa, cpu) \
+ (((insn)->membership & isa) != 0 \
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
@@ -508,6 +501,7 @@ enum
M_LWR_A,
M_LWR_AB,
M_LWU_AB,
+ M_MOVE,
M_MUL,
M_MUL_I,
M_MULO,
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.17
diff -u -p -d -r1.17 mips-dis.c
--- opcodes/mips-dis.c 2001/08/07 12:36:13 1.17
+++ opcodes/mips-dis.c 2001/08/08 11:48:04
@@ -469,7 +469,7 @@ print_insn_mips (memaddr, word, info)
{
register const char *d;
- if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor, 0))
+ if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor))
continue;
(*info->fprintf_func) (info->stream, "%s", op->name);
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.23
diff -u -p -d -r1.23 mips-opc.c
--- opcodes/mips-opc.c 2001/07/21 20:46:51 1.23
+++ opcodes/mips-opc.c 2001/08/08 11:48:04
@@ -96,8 +96,6 @@ Software Foundation, 59 Temple Place - S
#define G3 (I4 \
)
-#define G6 INSN_GP32
-
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
@@ -121,7 +119,7 @@ const struct mips_opcode mips_builtin_op
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
-{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1|G6 },/* or */
+{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 },
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.60
diff -u -p -d -r1.60 tc-mips.c
--- gas/config/tc-mips.c 2001/08/07 13:22:46 1.60
+++ gas/config/tc-mips.c 2001/08/08 11:48:06
@@ -685,6 +685,7 @@ static void check_absolute_expr PARAMS (
expressionS *));
static void load_register PARAMS ((int *, int, expressionS *, int));
static void load_address PARAMS ((int *counter, int reg, expressionS *ep));
+static void move_register PARAMS ((int *, int, int));
static void macro PARAMS ((struct mips_cl_insn * ip));
static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
#ifdef LOSING_COMPILER
@@ -2533,8 +2534,7 @@ macro_build (place, counter, ep, name, f
{
if (strcmp (fmt, insn.insn_mo->args) == 0
&& insn.insn_mo->pinfo != INSN_MACRO
- && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch,
- HAVE_32BIT_GPRS)
+ && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
&& (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
break;
@@ -3430,6 +3430,19 @@ load_address (counter, reg, ep)
abort ();
}
+/* Move the contents of register SOURCE into register DEST. */
+
+static void
+move_register (counter, dest, source)
+ int *counter;
+ int dest;
+ int source;
+{
+ macro_build ((char *) NULL, counter, (expressionS *) NULL,
+ HAVE_32BIT_GPRS ? "addu" : "daddu",
+ "d,v,t", dest, source, 0);
+}
+
/*
* Build macros
* This routine implements the seemingly endless macro or synthesized
@@ -3503,7 +3516,7 @@ macro (ip)
if (dreg == sreg)
macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
else
- macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0);
+ move_register (&icnt, dreg, sreg);
macro_build ((char *) NULL, &icnt, NULL,
dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
@@ -4056,10 +4069,9 @@ macro (ip)
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
{
if (strcmp (s2, "mflo") == 0)
- macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg,
- sreg);
+ move_register (&icnt, dreg, sreg);
else
- macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0);
+ move_register (&icnt, dreg, 0);
return;
}
if (imm_expr.X_op == O_constant
@@ -4072,7 +4084,7 @@ macro (ip)
"d,w", dreg, sreg);
}
else
- macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0);
+ move_register (&icnt, dreg, 0);
return;
}
@@ -5189,8 +5201,7 @@ macro (ip)
if (lreg <= 31)
{
if (offset_expr.X_op == O_absent)
- macro_build ((char *) NULL, &icnt, NULL, "move", "d,s",
- lreg, 0);
+ move_register (&icnt, lreg, 0);
else
{
assert (offset_expr.X_op == O_constant);
@@ -5808,6 +5819,10 @@ macro (ip)
ip->insn_opcode);
return;
+ case M_MOVE:
+ move_register (&icnt, dreg, sreg);
+ return;
+
#ifdef LOSING_COMPILER
default:
/* Try and see if this is a new itbl instruction.
@@ -6039,7 +6054,7 @@ macro2 (ip)
{
as_warn (_("Instruction %s: result is always false"),
ip->insn_mo->name);
- macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0);
+ move_register (&icnt, dreg, 0);
return;
}
if (imm_expr.X_op == O_constant
@@ -6778,8 +6793,7 @@ mips16_macro (ip)
expr1.X_add_number = 0;
macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
if (xreg != yreg)
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
- "move", "y,X", xreg, yreg);
+ move_register (&icnt, xreg, yreg);
expr1.X_add_number = 2;
macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
@@ -6948,7 +6962,7 @@ mips_ip (str, ip)
assert (strcmp (insn->name, str) == 0);
- if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch, HAVE_32BIT_GPRS))
+ if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch))
ok = true;
else
ok = false;
Index: gas/testsuite/gas/mips/mips-gp32-fp32.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp32.d,v
retrieving revision 1.2
diff -u -p -d -r1.2 mips-gp32-fp32.d
--- gas/testsuite/gas/mips/mips-gp32-fp32.d 2001/08/05 00:53:28 1.2
+++ gas/testsuite/gas/mips/mips-gp32-fp32.d 2001/08/08 11:48:06
@@ -60,7 +60,7 @@ Disassembly of section .text:
c8: a8240000 swl a0,0\(at\)
cc: b8240003 swr a0,3\(at\)
d0: 3c043ff0 lui a0,0x3ff0
- d4: 00002825 move a1,zero
+ d4: 00002821 move a1,zero
d8: 3c010000 lui at,0x0
dc: 8c240000 lw a0,0\(at\)
e0: 8c250004 lw a1,4\(at\)
@@ -72,7 +72,7 @@ Disassembly of section .text:
f8: 2c840001 sltiu a0,a0,1
fc: 24a40064 addiu a0,a1,100
100: 0004202b sltu a0,zero,a0
- 104: 00a02025 move a0,a1
+ 104: 00a02021 move a0,a1
0+0108 <[^>]*>:
...
Index: gas/testsuite/gas/mips/mips-gp32-fp32-pic.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d,v
retrieving revision 1.2
diff -u -p -d -r1.2 mips-gp32-fp32-pic.d
--- gas/testsuite/gas/mips/mips-gp32-fp32-pic.d 2001/08/05 00:53:28 1.2
+++ gas/testsuite/gas/mips/mips-gp32-fp32-pic.d 2001/08/08 11:48:06
@@ -98,7 +98,7 @@ Disassembly of section .text:
160: a8240000 swl a0,0\(at\)
164: b8240003 swr a0,3\(at\)
168: 3c043ff0 lui a0,0x3ff0
- 16c: 00002825 move a1,zero
+ 16c: 00002821 move a1,zero
170: 8f810000 lw at,0\(gp\)
174: 8c240000 lw a0,0\(at\)
178: 8c250004 lw a1,4\(at\)
@@ -111,7 +111,7 @@ Disassembly of section .text:
194: 2c840001 sltiu a0,a0,1
198: 24a40064 addiu a0,a1,100
19c: 0004202b sltu a0,zero,a0
- 1a0: 00a02025 move a0,a1
+ 1a0: 00a02021 move a0,a1
0+01a4 <[^>]*>:
...
Index: gas/testsuite/gas/mips/mips-gp32-fp64.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp64.d,v
retrieving revision 1.2
diff -u -p -d -r1.2 mips-gp32-fp64.d
--- gas/testsuite/gas/mips/mips-gp32-fp64.d 2001/08/05 00:53:28 1.2
+++ gas/testsuite/gas/mips/mips-gp32-fp64.d 2001/08/08 11:48:06
@@ -60,7 +60,7 @@ Disassembly of section .text:
c8: a8240000 swl a0,0\(at\)
cc: b8240003 swr a0,3\(at\)
d0: 3c043ff0 lui a0,0x3ff0
- d4: 00002825 move a1,zero
+ d4: 00002821 move a1,zero
d8: 3c010000 lui at,0x0
dc: 8c240000 lw a0,0\(at\)
e0: 8c250004 lw a1,4\(at\)
@@ -70,7 +70,7 @@ Disassembly of section .text:
f0: 2c840001 sltiu a0,a0,1
f4: 24a40064 addiu a0,a1,100
f8: 0004202b sltu a0,zero,a0
- fc: 00a02025 move a0,a1
+ fc: 00a02021 move a0,a1
100: 46231040 add.d \$f1,\$f2,\$f3
0+0104 <[^>]*>:
Index: gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d,v
retrieving revision 1.2
diff -u -p -d -r1.2 mips-gp32-fp64-pic.d
--- gas/testsuite/gas/mips/mips-gp32-fp64-pic.d 2001/08/05 00:53:28 1.2
+++ gas/testsuite/gas/mips/mips-gp32-fp64-pic.d 2001/08/08 11:48:06
@@ -98,7 +98,7 @@ Disassembly of section .text:
160: a8240000 swl a0,0\(at\)
164: b8240003 swr a0,3\(at\)
168: 3c043ff0 lui a0,0x3ff0
- 16c: 00002825 move a1,zero
+ 16c: 00002821 move a1,zero
170: 8f810000 lw at,0\(gp\)
174: 8c240000 lw a0,0\(at\)
178: 8c250004 lw a1,4\(at\)
@@ -110,7 +110,7 @@ Disassembly of section .text:
190: 2c840001 sltiu a0,a0,1
194: 24a40064 addiu a0,a1,100
198: 0004202b sltu a0,zero,a0
- 19c: 00a02025 move a0,a1
+ 19c: 00a02021 move a0,a1
1a0: 46231040 add.d \$f1,\$f2,\$f3
0+01a4 <[^>]*>:
Index: gas/testsuite/gas/mips/mips-abi32.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-abi32.d,v
retrieving revision 1.2
diff -u -p -d -r1.2 mips-abi32.d
--- gas/testsuite/gas/mips/mips-abi32.d 2001/08/05 00:53:28 1.2
+++ gas/testsuite/gas/mips/mips-abi32.d 2001/08/08 11:48:06
@@ -60,7 +60,7 @@ Disassembly of section .text:
c8: a8240000 swl a0,0\(at\)
cc: b8240003 swr a0,3\(at\)
d0: 3c043ff0 lui a0,0x3ff0
- d4: 00002825 move a1,zero
+ d4: 00002821 move a1,zero
d8: 3c010000 lui at,0x0
dc: 8c240000 lw a0,0\(at\)
e0: 8c250004 lw a1,4\(at\)
@@ -72,7 +72,7 @@ Disassembly of section .text:
f8: 2c840001 sltiu a0,a0,1
fc: 24a40064 addiu a0,a1,100
100: 0004202b sltu a0,zero,a0
- 104: 00a02025 move a0,a1
+ 104: 00a02021 move a0,a1
0+0108 <[^>]*>:
...
Index: gas/testsuite/gas/mips/mips-abi32-pic.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips-abi32-pic.d,v
retrieving revision 1.2
diff -u -p -d -r1.2 mips-abi32-pic.d
--- gas/testsuite/gas/mips/mips-abi32-pic.d 2001/08/05 00:53:28 1.2
+++ gas/testsuite/gas/mips/mips-abi32-pic.d 2001/08/08 11:48:06
@@ -98,7 +98,7 @@ Disassembly of section .text:
160: a8240000 swl a0,0\(at\)
164: b8240003 swr a0,3\(at\)
168: 3c043ff0 lui a0,0x3ff0
- 16c: 00002825 move a1,zero
+ 16c: 00002821 move a1,zero
170: 8f810000 lw at,0\(gp\)
174: 8c240000 lw a0,0\(at\)
178: 8c250004 lw a1,4\(at\)
@@ -111,7 +111,7 @@ Disassembly of section .text:
194: 2c840001 sltiu a0,a0,1
198: 24a40064 addiu a0,a1,100
19c: 0004202b sltu a0,zero,a0
- 1a0: 00a02025 move a0,a1
+ 1a0: 00a02021 move a0,a1
0+01a4 <[^>]*>:
...