Re: [PATCH] Performance counter opcodes for MIPS R1[02]000

[Daniel Jacobowitz <dmj+ at andrew dot cmu dot edu>]

On Thu, Jun 21, 2001 at 06:44:45PM -0700, cgd@sibyte.com wrote:
> dmj+@andrew.cmu.edu ("Daniel Jacobowitz") writes:
> > On Thu, Jun 21, 2001 at 07:45:56AM +0200, Thiemo Seufer wrote:
> > > cgd@sibyte.com wrote:
> > > [snip]
> > > > The selection of t0 for that register name, for a binary unmarked with
> > > > ABI, is a change, and I don't understand why it's correct.
> > > 
> > > Ah, now I understand Your concern. I wasn't aware of the fact that
> > > there are unmarked binaries. I thought the use of ABI-flags was
> > > mandatory in ELF.
> > 
> > Nope.  Not only does, for instance, Linux/MIPS not use them - it would
> > be ABI-noncompliant to use them, unless I misread the psABI.  Only
> > noreorder, pic, cpic, and the four arch bits are defined for e_flags in
> > o32.
> 
> the psABI version that you're talking about is the one at:
> 
> 	http://www.sco.com/developer/devspecs/mipsabi.pdf
> 
> (MIPS RISC Processor Supplement 3rd Edition)?
> 
> 
> Not only does it only define those e_flags bits, but it doesn't define
> what the EF_MIPS_ARCH bits actually mean, and indicates that only
> those with EF_MIPS_ARCH bits set to all 0 are ABI-compliant!
> 
> It also donsn't seem to provide much friendliness to little-endian
> MIPS.  8-)

Indeed.  The trick is updating it without causing incompatibilities
with existing systems - that notice the changed e_flags and gripe.

-- 
Daniel Jacobowitz                           Carnegie Mellon University
MontaVista Software                         Debian GNU/Linux Developer