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[patch] MIPS32 updated
- To: binutils at sources dot redhat dot com
- Subject: [patch] MIPS32 updated
- From: Anders Norlander <anorland at acc dot umu dot se>
- Date: Fri, 1 Sep 2000 16:41:59 +0200 (MET_DST)
Hi,
here's an updated patch for MIPS32 support.
Changes from the previous post are:
* Patch binutils to use defines instead of hardcoded mips processor
numbers.
* The readelf utility is patched to print the EF_MIPS_MACH
field of the e_flags field.
* Adds a few instructions.
Ok to apply?
Regards,
Anders
binutils/ChangeLog
Fri Sep 1 14:06:19 2000 Anders Norlander <anorland@acc.umu.se>
* readelf.c (get_machine_flags): Also print EF_MIPS_MACH field.
include/opcode/ChangeLog
Fri Sep 1 11:41:03 2000 Anders Norlander <anorland@acc.umu.se>
Use defines instead of hard-coded processor numbers.
* mips.h (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
CPU_4KC, CPU_4KM, CPU_4KP): New defines.
* mips.h (OPCODE_IS_MEMBER): Use.
bfd/ChangeLog
Thu Aug 31 10:02:37 2000 Anders Norlander <anorland@acc.umu.se>
* cpu-mips.c (arch_info_struct): Add mips:4K
* bfd-in2.h (bfd_mach_mips4K): New define.
* archures.c: Add bfd_mach_mips4K to comment.
* elf32-mips.c (_bfd_mips_elf_final_write_processing): Return E_MIPS_ARCH_2 for
bfd_mach_mips4K.
gas/ChangeLog
Thu Aug 31 10:02:37 2000 Anders Norlander <anorland@acc.umu.se>
* config/tc-mips.c (md_begin): Recognize 4Kc, 4Km and 4Kp processors.
(md_parse_option): Ditto.
(md_longopts): Add -mips32 option.
(md_show_usage): Document new options.
(mips_ip): Assemble sdbbp 20 bit 'm' args for MIPS32.
(mips_ip): Assemble mfc0 with a sub-selection code.
(validate_mips_insn): Handle 'H' (OP_*_SEL) and 'm' (OP_*_CODE20).
(mips_cpu_to_str): New function.
(mips_ip): Use mips_cpu_to_str instead of printing numeric cpu value.
* config/tc-mips.c: Use CPU_* defines instead of hardcoded numbers.
* doc/as.texinfo: Document new options.
* doc/c-mips.texi: Ditto.
include/elf/ChangeLog
Thu Aug 31 10:02:37 2000 Anders Norlander <anorland@acc.umu.se>
* mips.h (E_MIPS_MACH_4K): New define.
include/opcode/ChangeLog
Thu Aug 31 10:02:37 2000 Anders Norlander <anorland@acc.umu.se>
* mips.h (OP_MASK_SEL, OP_SH_SEL): Define.
(OP_MASK_CODE20, OP_SH_CODE20): Define.
* mips.h: Add 'P' to used characters.
* mips.h: Use 'H' for coprocessor select field.
* mips.h: Use 'm' for 20 bit breakpoint code.
* mips.h: Document new arg characters and add to used characters.
* mips.h (INSN_MIPS32): New define for MIPS32 extensions.
(OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
opcodes/ChangeLog
Thu Aug 31 10:02:37 2000 Anders Norlander <anorland@acc.umu.se>
* mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores.
(mips_builtin_opcodes): Add mfc0 and mtc0 with sub-selection values.
* mips-opc.c (mips_builtin_opcodes): Add clo and clz opcodes.
(P4): New define.
(mips_builtin_opcodes): Add msub and msubu instructions for MIPS32.
(mips_builtin_opcodes): Add madd/maddu aliases for mad/madu for MIPS32.
(mips_builtin_opcodes): Support wait, deret, eret, movn, pref for MIPS32.
(mips_builtin_opcodes): Support tlbp, tlbr, tlbwi, tlbwr.
* mips-dis.c (print_insn_arg): Print sdbbp 'm' args.
(print_insn_arg): Handle 'H' args.
(set_mips_isa_type): Recognize 4K.
* mips-dis.c: Use CPU_* defines instead of hardcoded numbers.
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.19
diff -u -2 -p -r1.19 archures.c
--- bfd/archures.c 2000/07/20 16:21:06 1.19
+++ bfd/archures.c 2000/09/01 14:27:35
@@ -128,4 +128,5 @@ DESCRIPTION
.#define bfd_mach_mips8000 8000
.#define bfd_mach_mips10000 10000
+.#define bfd_mach_mips4K 32
.#define bfd_mach_mips16 16
. bfd_arch_i386, {* Intel 386 *}
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.61
diff -u -2 -p -r1.61 bfd-in2.h
--- bfd/bfd-in2.h 2000/08/22 19:33:16 1.61
+++ bfd/bfd-in2.h 2000/09/01 14:27:41
@@ -1367,4 +1367,5 @@ enum bfd_architecture
((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9a)
bfd_arch_mips, /* MIPS Rxxxx */
+/* Keep in sync with CPU_* defines in include/opcode/mips.h */
#define bfd_mach_mips3000 3000
#define bfd_mach_mips3900 3900
@@ -1381,4 +1382,5 @@ enum bfd_architecture
#define bfd_mach_mips8000 8000
#define bfd_mach_mips10000 10000
+#define bfd_mach_mips4K 32
#define bfd_mach_mips16 16
bfd_arch_i386, /* Intel 386 */
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.2
diff -u -2 -p -r1.2 cpu-mips.c
--- bfd/cpu-mips.c 2000/07/31 18:49:56 1.2
+++ bfd/cpu-mips.c 2000/09/01 14:27:41
@@ -54,4 +54,5 @@ I_mips6000,
I_mips8000,
I_mips10000,
+I_mips4K,
I_mips16
};
@@ -76,5 +77,5 @@ static const bfd_arch_info_type arch_inf
N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
-
+ N (32, 32, bfd_mach_mips4K, "mips:4K", false, NN(I_mips4K)),
N (64, 64, bfd_mach_mips16, "mips:16", false, 0),
Index: bfd/elf32-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-mips.c,v
retrieving revision 1.76
diff -u -2 -p -r1.76 elf32-mips.c
--- bfd/elf32-mips.c 2000/07/23 20:51:35 1.76
+++ bfd/elf32-mips.c 2000/09/01 14:27:47
@@ -1849,4 +1849,7 @@ elf_mips_mach (flags)
return bfd_mach_mips4650;
+ case E_MIPS_MACH_MIPS32:
+ return bfd_mach_mips4K;
+
default:
switch (flags & EF_MIPS_ARCH)
@@ -2348,4 +2351,9 @@ _bfd_mips_elf_final_write_processing (ab
val = E_MIPS_ARCH_4;
break;
+
+ case bfd_mach_mips4K:
+ val = E_MIPS_ARCH_2 | E_MIPS_MACH_MIPS32;
+ break;
+
}
Index: binutils/readelf.c
===================================================================
RCS file: /cvs/src/src/binutils/readelf.c,v
retrieving revision 1.68
diff -u -2 -p -r1.68 readelf.c
--- binutils/readelf.c 2000/08/17 23:00:38 1.68
+++ binutils/readelf.c 2000/09/01 14:27:51
@@ -1462,4 +1462,14 @@ get_machine_flags (e_flags, e_machine)
if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
strcat (buf, ", mips4");
+
+ switch ((e_flags & EF_MIPS_MACH))
+ {
+ case E_MIPS_MACH_3900: strcat (buf, ", 3900"); break;
+ case E_MIPS_MACH_4010: strcat (buf, ", 4010"); break;
+ case E_MIPS_MACH_4100: strcat (buf, ", 4100"); break;
+ case E_MIPS_MACH_4650: strcat (buf, ", 4650"); break;
+ case E_MIPS_MACH_4111: strcat (buf, ", 4111"); break;
+ case E_MIPS_MACH_MIPS32: strcat (buf, ", mips32"); break;
+ }
break;
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.23
diff -u -2 -p -r1.23 tc-mips.c
--- gas/config/tc-mips.c 2000/07/14 22:28:24 1.23
+++ gas/config/tc-mips.c 2000/09/01 14:27:57
@@ -264,5 +264,5 @@ static int mips_gp32 = 0;
-- Jim Blandy <jimb@cygnus.com> */
-#define hilo_interlocks (mips_cpu == 4010 \
+#define hilo_interlocks (mips_cpu == CPU_R4010 \
)
@@ -271,10 +271,10 @@ static int mips_gp32 = 0;
#define gpr_interlocks \
(mips_opts.isa != 1 \
- || mips_cpu == 3900)
+ || mips_cpu == CPU_R3900)
/* As with other "interlocks" this is used by hardware that has FP
(co-processor) interlocks. */
/* Itbl support may require additional care here. */
-#define cop_interlocks (mips_cpu == 4300 \
+#define cop_interlocks (mips_cpu == CPU_R4300 \
)
@@ -706,4 +706,5 @@ static void s_mips_weakext PARAMS ((int)
static void s_file PARAMS ((int));
static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
+static char *mips_cpu_to_str PARAMS ((int cpu));
@@ -852,4 +853,34 @@ static segT pdr_seg;
#endif
+static char *
+mips_cpu_to_str (cpu)
+ int cpu;
+{
+ static char s[16];
+ switch (cpu)
+ {
+ case CPU_R2000: return "R2000";
+ case CPU_R3000: return "R3000";
+ case CPU_R3900: return "R3900";
+ case CPU_R4000: return "R4000";
+ case CPU_R4010: return "R4010";
+ case CPU_VR4100: return "VR4100";
+ case CPU_R4111: return "R4111";
+ case CPU_R4300: return "R4300";
+ case CPU_R4400: return "R4400";
+ case CPU_R4600: return "R4600";
+ case CPU_R4650: return "R4650";
+ case CPU_R5000: return "R5000";
+ case CPU_R6000: return "R6000";
+ case CPU_R8000: return "R8000";
+ case CPU_R10000: return "R10000";
+ case CPU_4K: return "4K";
+ default:
+ sprintf (s, "%d", cpu);
+ return s;
+ }
+}
+
+
/*
* This function is called once, at assembler startup time. It should
@@ -894,17 +925,17 @@ md_begin ()
{
if (mips_opts.isa < 0)
- mips_cpu = 3000;
+ mips_cpu = CPU_R3000;
else if (mips_opts.isa == 2)
- mips_cpu = 6000;
+ mips_cpu = CPU_R6000;
else if (mips_opts.isa == 3)
- mips_cpu = 4000;
+ mips_cpu = CPU_R4000;
else if (mips_opts.isa == 4)
- mips_cpu = 8000;
+ mips_cpu = CPU_R8000;
else
- mips_cpu = 3000;
+ mips_cpu = CPU_R3000;
}
@@ -912,41 +943,47 @@ md_begin ()
|| strcmp (cpu, "mipstx39") == 0
)
- mips_cpu = 3900;
+ mips_cpu = CPU_R3900;
else if (strcmp (cpu, "r6000") == 0
|| strcmp (cpu, "mips2") == 0)
- mips_cpu = 6000;
+ mips_cpu = CPU_R6000;
else if (strcmp (cpu, "mips64") == 0
|| strcmp (cpu, "r4000") == 0
|| strcmp (cpu, "mips3") == 0)
- mips_cpu = 4000;
+ mips_cpu = CPU_R4000;
else if (strcmp (cpu, "r4400") == 0)
- mips_cpu = 4400;
+ mips_cpu = CPU_R4400;
else if (strcmp (cpu, "mips64orion") == 0
|| strcmp (cpu, "r4600") == 0)
- mips_cpu = 4600;
+ mips_cpu = CPU_R4600;
else if (strcmp (cpu, "r4650") == 0)
- mips_cpu = 4650;
+ mips_cpu = CPU_R4650;
else if (strcmp (cpu, "mips64vr4300") == 0)
- mips_cpu = 4300;
+ mips_cpu = CPU_R4300;
else if (strcmp (cpu, "mips64vr4111") == 0)
- mips_cpu = 4111;
+ mips_cpu = CPU_R4111;
else if (strcmp (cpu, "mips64vr4100") == 0)
- mips_cpu = 4100;
+ mips_cpu = CPU_VR4100;
else if (strcmp (cpu, "r4010") == 0)
- mips_cpu = 4010;
+ mips_cpu = CPU_R4010;
+
+ else if (strcmp (cpu, "4Kc") == 0
+ || strcmp (cpu, "4Kp") == 0
+ || strcmp (cpu, "4Km") == 0)
+ mips_cpu = CPU_4K;
+
else if (strcmp (cpu, "r5000") == 0
|| strcmp (cpu, "mips64vr5000") == 0)
- mips_cpu = 5000;
+ mips_cpu = CPU_R5000;
@@ -954,8 +991,8 @@ md_begin ()
else if (strcmp (cpu, "r8000") == 0
|| strcmp (cpu, "mips4") == 0)
- mips_cpu = 8000;
+ mips_cpu = CPU_R8000;
else if (strcmp (cpu, "r10000") == 0)
- mips_cpu = 10000;
+ mips_cpu = CPU_R10000;
else if (strcmp (cpu, "mips16") == 0)
@@ -963,27 +1000,28 @@ md_begin ()
else
- mips_cpu = 3000;
+ mips_cpu = CPU_R3000;
}
- if (mips_cpu == 3000
- || mips_cpu == 3900)
+ if (mips_cpu == CPU_R3000
+ || mips_cpu == CPU_R3900)
mips_isa_from_cpu = 1;
- else if (mips_cpu == 6000
- || mips_cpu == 4010)
+ else if (mips_cpu == CPU_R6000
+ || mips_cpu == CPU_R4010
+ || mips_cpu == CPU_MIPS32)
mips_isa_from_cpu = 2;
- else if (mips_cpu == 4000
- || mips_cpu == 4100
- || mips_cpu == 4111
- || mips_cpu == 4400
- || mips_cpu == 4300
- || mips_cpu == 4600
- || mips_cpu == 4650)
+ else if (mips_cpu == CPU_R4000
+ || mips_cpu == CPU_VR4100
+ || mips_cpu == CPU_R4111
+ || mips_cpu == CPU_R4400
+ || mips_cpu == CPU_R4300
+ || mips_cpu == CPU_R4600
+ || mips_cpu == CPU_R4650)
mips_isa_from_cpu = 3;
- else if (mips_cpu == 5000
- || mips_cpu == 8000
- || mips_cpu == 10000)
+ else if (mips_cpu == CPU_R5000
+ || mips_cpu == CPU_R8000
+ || mips_cpu == CPU_R10000)
mips_isa_from_cpu = 4;
@@ -1012,6 +1050,6 @@ md_begin ()
if (a != NULL)
{
- free (a);
- a = NULL;
+ free (a);
+ a = NULL;
}
@@ -1631,5 +1669,5 @@ append_insn (place, ip, address_expr, re
delay. */
if (! (hilo_interlocks
- || (mips_cpu == 3900 && (pinfo & INSN_MULT)))
+ || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT)))
&& (mips_optimize == 0
|| (pinfo & INSN_WRITE_LO)))
@@ -1653,5 +1691,5 @@ append_insn (place, ip, address_expr, re
Also the note tx39's multiply above. */
if (! (hilo_interlocks
- || (mips_cpu == 3900 && (pinfo & INSN_MULT)))
+ || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT)))
&& (mips_optimize == 0
|| (pinfo & INSN_WRITE_HI)))
@@ -1692,9 +1730,9 @@ append_insn (place, ip, address_expr, re
&& (pinfo & INSN_WRITE_LO)
&& ! (hilo_interlocks
- || (mips_cpu == 3900 && (pinfo & INSN_MULT))))
+ || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT))))
|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
&& (pinfo & INSN_WRITE_HI)
&& ! (hilo_interlocks
- || (mips_cpu == 3900 && (pinfo & INSN_MULT)))))
+ || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT)))))
prev_prev_nop = 1;
else
@@ -2047,5 +2085,5 @@ append_insn (place, ip, address_expr, re
| INSN_WRITE_COND_CODE)))
|| (! (hilo_interlocks
- || (mips_cpu == 3900 && (pinfo & INSN_MULT)))
+ || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT)))
&& (prev_pinfo
& (INSN_READ_LO
@@ -2531,5 +2569,5 @@ macro_build (place, counter, ep, name, f
&& OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_cpu,
mips_gp32)
- && (mips_cpu != 4650 || (insn.insn_mo->pinfo & FP_D) == 0))
+ && (mips_cpu != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
break;
@@ -4846,5 +4884,5 @@ macro (ip)
goto ld;
case M_LDC1_AB:
- if (mips_cpu == 4650)
+ if (mips_cpu == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
@@ -4935,5 +4973,5 @@ macro (ip)
goto st;
case M_SDC1_AB:
- if (mips_cpu == 4650)
+ if (mips_cpu == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
@@ -5423,5 +5461,5 @@ macro (ip)
case M_L_DOB:
- if (mips_cpu == 4650)
+ if (mips_cpu == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
@@ -5464,5 +5502,5 @@ macro (ip)
* generate the extra instruction?
*/
- if (mips_cpu == 4650)
+ if (mips_cpu == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
@@ -5482,5 +5520,5 @@ macro (ip)
case M_S_DAB:
- if (mips_cpu == 4650)
+ if (mips_cpu == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
@@ -6111,5 +6149,5 @@ macro2 (ip)
case M_S_DOB:
- if (mips_cpu == 4650)
+ if (mips_cpu == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
@@ -6954,4 +6992,5 @@ validate_mips_insn (opc)
case 'F': break;
case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
+ case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
case 'I': break;
case 'L': break;
@@ -6973,4 +7012,5 @@ validate_mips_insn (opc)
case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
case 'l': break;
+ case 'm': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
@@ -7085,5 +7125,5 @@ mips_ip (str, ip)
if (insn->pinfo != INSN_MACRO)
{
- if (mips_cpu == 4650 && (insn->pinfo & FP_D) != 0)
+ if (mips_cpu == CPU_R4650 && (insn->pinfo & FP_D) != 0)
ok = false;
}
@@ -7101,6 +7141,6 @@ mips_ip (str, ip)
static char buf[100];
sprintf (buf,
- _("opcode not supported on this processor: %d (MIPS%d)"),
- mips_cpu, mips_opts.isa);
+ _("opcode not supported on this processor: %s (MIPS%d)"),
+ mips_cpu_to_str (mips_cpu), mips_opts.isa);
insn_error = buf;
@@ -7239,4 +7279,18 @@ mips_ip (str, ip)
continue;
+ case 'm': /* full 20 bit break code */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned) imm_expr.X_add_number > 0xfffff)
+ {
+ as_warn (_("Illegal break code (%ld)"),
+ (long) imm_expr.X_add_number);
+ imm_expr.X_add_number &= 0xfffff;
+ }
+ ip->insn_opcode |= imm_expr.X_add_number << 6;
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
case 'B': /* syscall code */
my_getExpression (&imm_expr, s);
@@ -7903,4 +7957,26 @@ mips_ip (str, ip)
continue;
+ case 'H': /* 3 bit coprocessor select code */
+ if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
+ s += 2;
+ if (isdigit ((unsigned char) *s))
+ {
+ c = 0;
+ do
+ {
+ c *= 10;
+ c += *s - '0';
+ ++s;
+ }
+ while (isdigit ((unsigned char) *s));
+ }
+ else
+ c = 8; /* Invalid sel value */
+
+ if (c > 7)
+ as_bad (_("invalid coprocessor sub-selection value (0-7)"));
+ ip->insn_opcode |= c;
+ continue;
+
default:
as_bad (_("bad char = '%c'\n"), *args);
@@ -8876,4 +8952,8 @@ struct option md_longopts[] = {
#define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
{"no-m3900", no_argument, NULL, OPTION_NO_M3900},
+#define OPTION_MIPS32 (OPTION_MD_BASE + 28)
+ {"mips32", no_argument, NULL, OPTION_MIPS32},
+#define OPTION_NO_MIPS32 (OPTION_MD_BASE + 29)
+ {"no-mips32", no_argument, NULL, OPTION_NO_MIPS32},
#define OPTION_MABI (OPTION_MD_BASE + 38)
@@ -9006,5 +9086,5 @@ md_parse_option (c, arg)
|| strcmp (p, "10k") == 0
|| strcmp (p, "10K") == 0)
- mips_cpu = 10000;
+ mips_cpu = CPU_R10000;
break;
@@ -9013,5 +9093,5 @@ md_parse_option (c, arg)
|| strcmp (p, "2k") == 0
|| strcmp (p, "2K") == 0)
- mips_cpu = 2000;
+ mips_cpu = CPU_R2000;
break;
@@ -9020,7 +9100,7 @@ md_parse_option (c, arg)
|| strcmp (p, "3k") == 0
|| strcmp (p, "3K") == 0)
- mips_cpu = 3000;
+ mips_cpu = CPU_R3000;
else if (strcmp (p, "3900") == 0)
- mips_cpu = 3900;
+ mips_cpu = CPU_R3900;
break;
@@ -9029,19 +9109,23 @@ md_parse_option (c, arg)
|| strcmp (p, "4k") == 0
|| strcmp (p, "4K") == 0)
- mips_cpu = 4000;
+ mips_cpu = CPU_R4000;
else if (strcmp (p, "4100") == 0)
- mips_cpu = 4100;
+ mips_cpu = CPU_VR4100;
else if (strcmp (p, "4111") == 0)
- mips_cpu = 4111;
+ mips_cpu = CPU_R4111;
else if (strcmp (p, "4300") == 0)
- mips_cpu = 4300;
+ mips_cpu = CPU_R4300;
else if (strcmp (p, "4400") == 0)
- mips_cpu = 4400;
+ mips_cpu = CPU_R4400;
else if (strcmp (p, "4600") == 0)
- mips_cpu = 4600;
+ mips_cpu = CPU_R4600;
else if (strcmp (p, "4650") == 0)
- mips_cpu = 4650;
+ mips_cpu = CPU_R4650;
else if (strcmp (p, "4010") == 0)
- mips_cpu = 4010;
+ mips_cpu = CPU_R4010;
+ else if (strcmp (p, "4Kc") == 0
+ || strcmp (p, "4Kp") == 0
+ || strcmp (p, "4Km") == 0)
+ mips_cpu = CPU_MIPS32;
break;
@@ -9050,5 +9134,5 @@ md_parse_option (c, arg)
|| strcmp (p, "5k") == 0
|| strcmp (p, "5K") == 0)
- mips_cpu = 5000;
+ mips_cpu = CPU_R5000;
break;
@@ -9057,5 +9141,5 @@ md_parse_option (c, arg)
|| strcmp (p, "6k") == 0
|| strcmp (p, "6K") == 0)
- mips_cpu = 6000;
+ mips_cpu = CPU_R6000;
break;
@@ -9064,10 +9148,10 @@ md_parse_option (c, arg)
|| strcmp (p, "8k") == 0
|| strcmp (p, "8K") == 0)
- mips_cpu = 8000;
+ mips_cpu = CPU_R8000;
break;
case 'o':
if (strcmp (p, "orion") == 0)
- mips_cpu = 4600;
+ mips_cpu = CPU_R4600;
break;
@@ -9082,5 +9166,5 @@ md_parse_option (c, arg)
case 5721:
case 7000:
- mips_cpu = 5000;
+ mips_cpu = CPU_R5000;
break;
default:
@@ -9090,8 +9174,8 @@ md_parse_option (c, arg)
if (sv
- && (mips_cpu != 4300
- && mips_cpu != 4100
- && mips_cpu != 4111
- && mips_cpu != 5000))
+ && (mips_cpu != CPU_R4300
+ && mips_cpu != CPU_VR4100
+ && mips_cpu != CPU_R4111
+ && mips_cpu != CPU_R5000))
{
as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg);
@@ -9109,5 +9193,5 @@ md_parse_option (c, arg)
case OPTION_M4650:
- mips_cpu = 4650;
+ mips_cpu = CPU_R4650;
break;
@@ -9116,5 +9200,5 @@ md_parse_option (c, arg)
case OPTION_M4010:
- mips_cpu = 4010;
+ mips_cpu = CPU_R4010;
break;
@@ -9123,5 +9207,5 @@ md_parse_option (c, arg)
case OPTION_M4100:
- mips_cpu = 4100;
+ mips_cpu = CPU_VR4100;
break;
@@ -9129,7 +9213,13 @@ md_parse_option (c, arg)
break;
+ case OPTION_MIPS32:
+ mips_cpu = CPU_MIPS32;
+ break;
+ case OPTION_NO_MIPS32:
+ break;
+
case OPTION_M3900:
- mips_cpu = 3900;
+ mips_cpu = CPU_R3900;
break;
@@ -9345,4 +9435,7 @@ MIPS options:\n\
show (stream, "8000", &column, &first);
show (stream, "10000", &column, &first);
+ show (stream, "4Kc", &column, &first);
+ show (stream, "4Kp", &column, &first);
+ show (stream, "4Km", &column, &first);
fputc ('\n', stream);
@@ -9358,5 +9451,9 @@ MIPS options:\n\
show (stream, "4100", &column, &first);
show (stream, "4650", &column, &first);
+
fputc ('\n', stream);
+
+ fprintf (stream, _("\
+-mips32 generate MIPS32 instructions\n"));
fprintf(stream, _("\
Index: gas/doc/as.texinfo
===================================================================
RCS file: /cvs/src/src/gas/doc/as.texinfo,v
retrieving revision 1.19
diff -u -2 -p -r1.19 as.texinfo
--- gas/doc/as.texinfo 2000/08/05 18:41:46 1.19
+++ gas/doc/as.texinfo 2000/09/01 14:28:00
@@ -279,5 +279,5 @@ Here is a brief summary of how to invoke
@ifset MIPS
[ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
- [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ]
+ [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ] [ -mips32 ] [ -no-mips32 ]
[ --trap ] [ --break ]
[ --emulation=@var{name} ]
@@ -679,4 +679,9 @@ the @samp{mad} and @samp{madu} instructi
instructions around accesses to the @samp{HI} and @samp{LO} registers.
@samp{-no-m4650} turns off this option.
+
+@item -mips32
+@itemx -no-mips32
+Generate code for the @sc{MIPS32} architecture. This tells the assembler to accept
+ISA level 2 instructions and MIPS32 extensions including some @sc{r4000} instructions.
@item -mcpu=@var{CPU}
Index: gas/doc/c-mips.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-mips.texi,v
retrieving revision 1.7
diff -u -2 -p -r1.7 c-mips.texi
--- gas/doc/c-mips.texi 2000/07/15 15:09:13 1.7
+++ gas/doc/c-mips.texi 2000/09/01 14:28:01
@@ -142,4 +142,7 @@ rm7000,
8000,
10000
+4Kc
+4Km
+4Kp
@end quotation
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/src/include/elf/mips.h,v
retrieving revision 1.7
diff -u -2 -p -r1.7 mips.h
--- include/elf/mips.h 2000/06/07 04:08:12 1.7
+++ include/elf/mips.h 2000/09/01 14:28:02
@@ -154,4 +154,8 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_4650 0x00850000
#define E_MIPS_MACH_4111 0x00880000
+/* -mips32 code.
+ It is easier to treat MIPS32 as a machine rather than an architecture. */
+#define E_MIPS_MACH_MIPS32 0x00890000
+
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.5
diff -u -2 -p -r1.5 mips.h
--- include/opcode/mips.h 2000/02/22 19:01:25 1.5
+++ include/opcode/mips.h 2000/09/01 14:28:02
@@ -127,4 +127,8 @@ Software Foundation, 59 Temple Place - S
#define OP_MASK_PERFREG 0x1f /* Performance monitoring */
#define OP_SH_PERFREG 1
+#define OP_SH_SEL 0 /* Coprocessor select field */
+#define OP_MASK_SEL 0x7
+#define OP_SH_CODE20 6 /* 20 bit breakpoint code */
+#define OP_MASK_CODE20 0xfffff
/* This structure holds information for a particular instruction. */
@@ -184,4 +188,5 @@ struct mips_opcode
"C" 25 bit coprocessor function code (OP_*_COPZ)
"B" 20 bit syscall function code (OP_*_SYSCALL)
+ "m" 20 bit breakpoint code (OP_*_CODE20)
"x" accept and ignore register name
"z" must be zero register
@@ -201,4 +206,5 @@ struct mips_opcode
"G" 5 bit destination register (OP_*_RD)
"P" 5 bit performance-monitor register (OP_*_PERFREG)
+ "H" 3 bit select field (OP_*_SEL)
Macro instructions:
@@ -216,5 +222,5 @@ struct mips_opcode
Characters used so far, for quick reference when adding more:
"<>(),"
- "ABCDEFGILMNSTRVW"
+ "ABCDEFGHIJLMNPSTRVW"
"abcdfhijklopqrstuvwxz"
*/
@@ -310,4 +316,6 @@ struct mips_opcode
#define INSN_ISA4 0x00000004
#define INSN_ISA5 0x00000005
+/* MIPS32 instruction (4Kc, 4Km, 4Kp) */
+#define INSN_MIPS32 0x00000100
/* Chip specific instructions. These are bitmasks. */
@@ -324,4 +332,27 @@ struct mips_opcode
#define INSN_GP32 0x00001000
+
+/* CPU defines, use instead of hardcoding processor number. Keep this
+ in sync with bfd/bfd-in2.h in order for machine selection to work. */
+#define CPU_R2000 2000
+#define CPU_R3000 3000
+#define CPU_R3900 3900
+#define CPU_R4000 4000
+#define CPU_R4010 4010
+#define CPU_VR4100 4100
+#define CPU_R4111 4111
+#define CPU_R4300 4300
+#define CPU_R4400 4400
+#define CPU_R4600 4600
+#define CPU_R4650 4650
+#define CPU_R5000 5000
+#define CPU_R6000 6000
+#define CPU_R8000 8000
+#define CPU_R10000 10000
+#define CPU_MIPS16 16
+#define CPU_MIPS32 32
+#define CPU_4K CPU_MIPS32
+
+
/* Test for membership in an ISA including chip specific ISAs.
INSN is pointer to an element of the opcode table; ISA is the
@@ -336,14 +367,16 @@ struct mips_opcode
&& ((insn)->membership & INSN_ISA) <= isa \
&& ((insn)->membership & INSN_GP32 ? gp32 : 1)) \
- || (cpu == 4650 \
+ || (cpu == CPU_R4650 \
&& ((insn)->membership & INSN_4650) != 0) \
- || (cpu == 4010 \
+ || (cpu == CPU_R4010 \
&& ((insn)->membership & INSN_4010) != 0) \
- || ((cpu == 4100 \
- || cpu == 4111 \
+ || ((cpu == CPU_VR4100 \
+ || cpu == CPU_R4111 \
) \
&& ((insn)->membership & INSN_4100) != 0) \
- || (cpu == 3900 \
- && ((insn)->membership & INSN_3900) != 0))
+ || (cpu == CPU_R3900 \
+ && ((insn)->membership & INSN_3900) != 0) \
+ || (cpu == CPU_MIPS32 \
+ && ((insn)->membership & INSN_MIPS32) != 0))
/* This is a list of macro expanded instructions.
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.6
diff -u -2 -p -r1.6 mips-dis.c
--- opcodes/mips-dis.c 2000/05/24 15:24:56 1.6
+++ opcodes/mips-dis.c 2000/09/01 14:28:03
@@ -178,4 +178,9 @@ print_insn_arg (d, l, pc, info)
break;
+ case 'm':
+ (*info->fprintf_func) (info->stream, "0x%x",
+ (l >> OP_SH_CODE20) & OP_MASK_CODE20);
+ break;
+
case 'C':
(*info->fprintf_func) (info->stream, "0x%x",
@@ -236,5 +241,9 @@ print_insn_arg (d, l, pc, info)
break;
+ case 'H':
+ (*info->fprintf_func) (info->stream, "%d", l & OP_MASK_SEL);
+ break;
+
default:
/* xgettext:c-format */
@@ -266,65 +275,69 @@ set_mips_isa_type (mach, isa, cputype)
{
case bfd_mach_mips3000:
- target_processor = 3000;
+ target_processor = CPU_R3000;
mips_isa = 1;
break;
case bfd_mach_mips3900:
- target_processor = 3900;
+ target_processor = CPU_R3900;
mips_isa = 1;
break;
case bfd_mach_mips4000:
- target_processor = 4000;
+ target_processor = CPU_R4000;
mips_isa = 3;
break;
case bfd_mach_mips4010:
- target_processor = 4010;
+ target_processor = CPU_R4010;
mips_isa = 2;
break;
case bfd_mach_mips4100:
- target_processor = 4100;
+ target_processor = CPU_VR4100;
mips_isa = 3;
break;
case bfd_mach_mips4111:
- target_processor = 4100;
+ target_processor = CPU_VR4100;
mips_isa = 3;
break;
case bfd_mach_mips4300:
- target_processor = 4300;
+ target_processor = CPU_R4300;
mips_isa = 3;
break;
case bfd_mach_mips4400:
- target_processor = 4400;
+ target_processor = CPU_R4400;
mips_isa = 3;
break;
case bfd_mach_mips4600:
- target_processor = 4600;
+ target_processor = CPU_R4600;
mips_isa = 3;
break;
case bfd_mach_mips4650:
- target_processor = 4650;
+ target_processor = CPU_R4650;
mips_isa = 3;
break;
+ case bfd_mach_mips4K:
+ target_processor = CPU_4K;
+ mips_isa = 2;
+ break;
case bfd_mach_mips5000:
- target_processor = 5000;
+ target_processor = CPU_R5000;
mips_isa = 4;
break;
case bfd_mach_mips6000:
- target_processor = 6000;
+ target_processor = CPU_R6000;
mips_isa = 2;
break;
case bfd_mach_mips8000:
- target_processor = 8000;
+ target_processor = CPU_R8000;
mips_isa = 4;
break;
case bfd_mach_mips10000:
- target_processor = 10000;
+ target_processor = CPU_R10000;
mips_isa = 4;
break;
case bfd_mach_mips16:
- target_processor = 16;
+ target_processor = CPU_MIPS16;
mips_isa = 3;
break;
default:
- target_processor = 3000;
+ target_processor = CPU_R3000;
mips_isa = 3;
break;
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.8
diff -u -2 -p -r1.8 mips-opc.c
--- opcodes/mips-opc.c 2000/07/31 18:50:56 1.8
+++ opcodes/mips-opc.c 2000/09/01 14:28:04
@@ -79,4 +79,5 @@ Software Foundation, 59 Temple Place - S
#define I5 INSN_ISA5
#define P3 INSN_4650
+#define P4 INSN_MIPS32
#define L1 INSN_4010
#define V1 INSN_4100
@@ -318,5 +319,5 @@ const struct mips_opcode mips_builtin_op
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
-{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1 },
+{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1|P4 },
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
@@ -328,4 +329,6 @@ const struct mips_opcode mips_builtin_op
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
+{"clo", "d,s", 0x70000021, 0xfc1f07ff, WR_d|RD_s, P4 },
+{"clz", "d,s", 0x70000020, 0xfc1f07ff, WR_d|RD_s, P4 },
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
@@ -356,5 +359,5 @@ const struct mips_opcode mips_builtin_op
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
-{"deret", "", 0x4200001f, 0xffffffff, 0, G2|M1 },
+{"deret", "", 0x4200001f, 0xffffffff, 0, G2|M1|P4 },
/* For ddiv, see the comments about div. */
{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
@@ -428,5 +431,5 @@ const struct mips_opcode mips_builtin_op
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
-{"eret", "", 0x42000018, 0xffffffff, 0, I3|M1 },
+{"eret", "", 0x42000018, 0xffffffff, 0, I3|M1|P4 },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
@@ -525,17 +528,20 @@ const struct mips_opcode mips_builtin_op
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 },
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
-{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
-{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
+{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3|P4 },
+{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3|P4 },
{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
+{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P4 },
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1 },
{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 },
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
+{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P4 },
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1},
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 },
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
+{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, P4 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
@@ -551,5 +557,5 @@ const struct mips_opcode mips_builtin_op
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 },
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
-{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1 },
+{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|P4 },
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1 },
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 },
@@ -559,5 +565,5 @@ const struct mips_opcode mips_builtin_op
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 },
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5},
-{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1 },
+{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|P4 },
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1 },
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 },
@@ -568,6 +574,9 @@ const struct mips_opcode mips_builtin_op
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
+{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P4 },
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
+{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P4 },
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
+{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, P4 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
@@ -579,5 +588,5 @@ const struct mips_opcode mips_builtin_op
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
-{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3},
+{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, P3|P4 },
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
@@ -612,5 +621,5 @@ const struct mips_opcode mips_builtin_op
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
-{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1 },
+{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|P4},
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
@@ -649,4 +658,5 @@ const struct mips_opcode mips_builtin_op
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 },
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 },
+{"sdbbp", "m", 0x7000003f, 0xfc00003f, TRAP, P4 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
@@ -756,8 +766,8 @@ const struct mips_opcode mips_builtin_op
{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 },
-{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1|M1 },
-{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1|M1 },
-{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1|M1 },
-{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1|M1 },
+{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1|M1|P4},
+{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1|M1|P4},
+{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1|M1|P4},
+{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1|M1|P4},
{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
@@ -800,5 +810,5 @@ const struct mips_opcode mips_builtin_op
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
-{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1 },
+{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1|P4 },
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },