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patch: MIPS32 support


Hi,

this patch adds support for the MIPS32 standard to gas/opcodes/bfd.
I'd appreciate feedback from people with experience of the mips code
in binutils.

MIPS32 builds on ISA 1&2 + some extensions and enhancements from
higher ISAs.

The only MIPS32 processors I know of are the 4K cores (4Kc, 4Km, 4Kp).
Since these processors don't have a number like the classic MIPS processors.
Internally I used 4750 to indicate these processors, I came up with that
number by putting together 4 + ascii value of 'K' + '0' (4 75 0). Suggestions
for a better solution would be appreciated.

There might be better names for things like 'bfd_mach_mips4K', perhaps
bfd_mach_mips32?

Feedback welcome.

Regards,
Anders
bfd/ChangeLog

 	* cpu-mips.c (arch_info_struct): Add mips:4K
 	* bfd-in2.h (bfd_mach_mips4K): New define.
 	* archures.c: Add bfd_mach_mips4K to comment.
 	* elf32-mips.c (_bfd_mips_elf_final_write_processing): Return E_MIPS_ARCH_2 for
 	bfd_mach_mips4K.


gas/ChangeLog

 	* config/tc-mips.c (md_begin): Recognize 4Kc, 4Km and 4Kp processors.
 	(md_parse_option): Ditto.
 	(md_longopts): Add -mips32 option.
 	(md_show_usage): Document new options.
 	(mips_ip): Assemble sdbbp 20 bit 'm' args for MIPS32.
 	(mips_ip): Assemble mfc0 with a sub-selection code.
 	(validate_mips_insn): Handle 'H' (OP_*_SEL) and 'm' (OP_*_CODE20).

 	* doc/as.texinfo: Document new options.
 	* doc/c-mips.texi: Ditto.


include/elf/ChangeLog

 	* mips.h (E_MIPS_MACH_4K): New define.


include/opcode/ChangeLog

 	* mips.h (OP_MASK_SEL, OP_SH_SEL): Define.
	(OP_MASK_CODE20, OP_SH_CODE20): Define.
 	* mips.h: Add 'P' to used characters.
 	* mips.h: Use 'H' for coprocessor select field.
	* mips.h: Use 'm' for 20 bit breakpoint code.
 	* mips.h: Document and add to used characters.

 
Thu Aug 17 11:34:43 2000  Anders Norlander  <anorland@acc.umu.se>
 
 	* mips.h (INSN_MIPS32): New define for MIPS32 extensions.
 	(OPCODE_IS_MEMBER): Recognize MIPS32 (4750).


opcodes/ChangeLog
 
 	* mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores.
 	(mips_builtin_opcodes): Add mfc0 and mtc0 with sub-selection values.
  
	* mips-opc.c (mips_builtin_opcodes): Add clo and clz opcodes.
 	(P4): New define.
 	(mips_builtin_opcodes): Add msub and msubu instructions for MIPS32.
 	(mips_builtin_opcodes): Add madd/maddu aliases for mad/madu for MIPS32.
 	(mips_builtin_opcodes): Support wait, deret, eret, movn, pref for MIPS32.
 
 	* mips-dis.c (print_insn_arg): Print sdbbp 'm' args.
 	(print_insn_arg): Handle 'H' args.
 	(set_mips_isa_type): Recognize 4K.


Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.19
diff -c -3 -p -r1.19 archures.c
*** bfd/archures.c	2000/07/20 16:21:06	1.19
--- bfd/archures.c	2000/08/30 15:04:37
*************** DESCRIPTION
*** 127,132 ****
--- 127,133 ----
  .#define bfd_mach_mips6000		6000
  .#define bfd_mach_mips8000		8000
  .#define bfd_mach_mips10000		10000
+ .#define bfd_mach_mips4K                4750
  .#define bfd_mach_mips16		16
  .  bfd_arch_i386,      {* Intel 386 *}
  .#define bfd_mach_i386_i386 0
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.61
diff -c -3 -p -r1.61 bfd-in2.h
*** bfd/bfd-in2.h	2000/08/22 19:33:16	1.61
--- bfd/bfd-in2.h	2000/08/30 15:04:40
*************** enum bfd_architecture 
*** 1380,1385 ****
--- 1380,1386 ----
  #define bfd_mach_mips6000              6000
  #define bfd_mach_mips8000              8000
  #define bfd_mach_mips10000             10000
+ #define bfd_mach_mips4K                4750
  #define bfd_mach_mips16                16
    bfd_arch_i386,      /* Intel 386 */
  #define bfd_mach_i386_i386 0
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.2
diff -c -3 -p -r1.2 cpu-mips.c
*** bfd/cpu-mips.c	2000/07/31 18:49:56	1.2
--- bfd/cpu-mips.c	2000/08/30 15:04:40
*************** I_mips5000, 
*** 53,58 ****
--- 53,59 ----
  I_mips6000, 
  I_mips8000, 
  I_mips10000,
+ I_mips4K,
  I_mips16
  };
  
*************** static const bfd_arch_info_type arch_inf
*** 75,81 ****
    N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
    N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
    N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
! 
  
    N (64, 64, bfd_mach_mips16,   "mips:16",   false, 0),
  };
--- 76,82 ----
    N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
    N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
    N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
!   N (32, 32, bfd_mach_mips4K,   "mips:4K",   false, NN(I_mips4K)),
  
    N (64, 64, bfd_mach_mips16,   "mips:16",   false, 0),
  };
Index: bfd/elf32-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-mips.c,v
retrieving revision 1.76
diff -c -3 -p -r1.76 elf32-mips.c
*** bfd/elf32-mips.c	2000/07/23 20:51:35	1.76
--- bfd/elf32-mips.c	2000/08/30 15:04:47
*************** elf_mips_mach (flags)
*** 1848,1853 ****
--- 1848,1856 ----
      case E_MIPS_MACH_4650:
        return bfd_mach_mips4650;
  
+     case E_MIPS_MACH_4K:
+       return bfd_mach_mips4K;
+ 
      default:
        switch (flags & EF_MIPS_ARCH)
  	{
*************** _bfd_mips_elf_final_write_processing (ab
*** 2347,2352 ****
--- 2350,2360 ----
      case bfd_mach_mips8000:
        val = E_MIPS_ARCH_4;
        break;
+ 
+     case bfd_mach_mips4K:
+       val = E_MIPS_ARCH_2 | E_MIPS_MACH_4K;
+       break;
+       
      }
  
    elf_elfheader (abfd)->e_flags &= ~ (EF_MIPS_ARCH | EF_MIPS_MACH);
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.23
diff -c -3 -p -r1.23 tc-mips.c
*** gas/config/tc-mips.c	2000/07/14 22:28:24	1.23
--- gas/config/tc-mips.c	2000/08/30 15:04:57
*************** md_begin ()
*** 944,949 ****
--- 944,955 ----
        else if (strcmp (cpu, "r4010") == 0)
          mips_cpu = 4010;
  
+       
+       else if (strcmp (cpu, "4Kc") == 0
+ 	       || strcmp (cpu, "4Kp") == 0
+ 	       || strcmp (cpu, "4Km") == 0)
+ 	mips_cpu = 4750;
+ 
  
        else if (strcmp (cpu, "r5000") == 0
  	       || strcmp (cpu, "mips64vr5000") == 0)
*************** md_begin ()
*** 970,976 ****
      mips_isa_from_cpu = 1;
  
    else if (mips_cpu == 6000
! 	   || mips_cpu == 4010)
      mips_isa_from_cpu = 2;
  
    else if (mips_cpu == 4000
--- 976,983 ----
      mips_isa_from_cpu = 1;
  
    else if (mips_cpu == 6000
! 	   || mips_cpu == 4010
! 	   || mips_cpu == 4750)
      mips_isa_from_cpu = 2;
  
    else if (mips_cpu == 4000
*************** md_begin ()
*** 1011,1018 ****
    cpu = NULL;
    if (a != NULL)
      {
!     free (a);
!     a = NULL;
      }
  
    if (mips_opts.isa == 1 && mips_trap)
--- 1018,1025 ----
    cpu = NULL;
    if (a != NULL)
      {
!       free (a);
!       a = NULL;
      }
  
    if (mips_opts.isa == 1 && mips_trap)
*************** validate_mips_insn (opc)
*** 6953,6958 ****
--- 6960,6966 ----
        case 'E':	USE_BITS (OP_MASK_RT,		OP_SH_RT);	break;
        case 'F': break;
        case 'G':	USE_BITS (OP_MASK_RD,		OP_SH_RD);	break;
+       case 'H': USE_BITS (OP_MASK_SEL,		OP_SH_SEL);	break;
        case 'I': break;
        case 'L': break;
        case 'M':	USE_BITS (OP_MASK_CCC,		OP_SH_CCC);	break;
*************** validate_mips_insn (opc)
*** 6972,6977 ****
--- 6980,6986 ----
        case 'j':	USE_BITS (OP_MASK_DELTA,	OP_SH_DELTA);	break;
        case 'k':	USE_BITS (OP_MASK_CACHE,	OP_SH_CACHE);	break;
        case 'l': break;
+       case 'm': USE_BITS (OP_MASK_CODE20,	OP_SH_CODE20);	break;
        case 'o': USE_BITS (OP_MASK_DELTA,	OP_SH_DELTA);	break;
        case 'p':	USE_BITS (OP_MASK_DELTA,	OP_SH_DELTA);	break;
        case 'q':	USE_BITS (OP_MASK_CODE2,	OP_SH_CODE2);	break;
*************** mips_ip (str, ip)
*** 7238,7243 ****
--- 7247,7266 ----
  	      s = expr_end;
  	      continue;
  
+ 	    case 'm':		/* full 20 bit break code */
+ 	      my_getExpression (&imm_expr, s);
+ 	      check_absolute_expr (ip, &imm_expr);
+ 	      if ((unsigned) imm_expr.X_add_number > 0xfffff)
+ 		{
+ 		  as_warn (_("Illegal break code (%ld)"),
+ 			   (long) imm_expr.X_add_number);
+ 		  imm_expr.X_add_number &= 0xfffff;
+ 		}
+ 	      ip->insn_opcode |= imm_expr.X_add_number << 6;
+ 	      imm_expr.X_op = O_absent;
+ 	      s = expr_end;
+ 	      continue;
+ 
  	    case 'B':		/* syscall code */
  	      my_getExpression (&imm_expr, s);
  	      check_absolute_expr (ip, &imm_expr);
*************** mips_ip (str, ip)
*** 7902,7907 ****
--- 7925,7952 ----
  		ip->insn_opcode |= regno << OP_SH_CCC;
                continue;
  
+ 	    case 'H':		/* 3 bit coprocessor select code */
+ 	      if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
+ 		s += 2;
+ 	      if (isdigit ((unsigned char) *s))
+ 		{
+ 		  c = 0;
+ 		  do
+ 		    {
+ 		      c *= 10;
+ 		      c += *s - '0';
+ 		      ++s;
+ 		    }
+ 		  while (isdigit ((unsigned char) *s));
+ 		}
+ 	      else
+ 		c = 8; /* Invalid sel value */
+ 
+ 	      if (c > 7)
+ 		as_bad (_("invalid coprocessor sub-selection value (0-7)"));
+ 	      ip->insn_opcode |= c;
+ 	      continue;
+ 
  	    default:
  	      as_bad (_("bad char = '%c'\n"), *args);
  	      internalError ();
*************** struct option md_longopts[] = {
*** 8875,8880 ****
--- 8920,8929 ----
    {"m3900", no_argument, NULL, OPTION_M3900},
  #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
    {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
+ #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
+   {"mips32", no_argument, NULL, OPTION_MIPS32},
+ #define OPTION_NO_MIPS32 (OPTION_MD_BASE + 29)
+   {"no-mips32", no_argument, NULL, OPTION_NO_MIPS32},
  
  #define OPTION_MABI (OPTION_MD_BASE + 38)
    {"mabi", required_argument, NULL, OPTION_MABI},
*************** md_parse_option (c, arg)
*** 9043,9048 ****
--- 9092,9101 ----
  		    mips_cpu = 4650;
  		else if (strcmp (p, "4010") == 0)
                    mips_cpu = 4010;
+ 		else if (strcmp (p, "4Kc") == 0
+ 			 || strcmp (p, "4Kp") == 0
+ 			 || strcmp (p, "4Km") == 0)
+ 		  mips_cpu = 4750;
  		break;
  
  	      case '5':
*************** md_parse_option (c, arg)
*** 9128,9133 ****
--- 9181,9192 ----
      case OPTION_NO_M4100:
        break;
  
+     case OPTION_MIPS32:
+       mips_cpu = 4750;
+       break;
+ 
+     case OPTION_NO_MIPS32:
+       break;
  
      case OPTION_M3900:
        mips_cpu = 3900;
*************** MIPS options:\n\
*** 9344,9349 ****
--- 9403,9412 ----
    show (stream, "6000", &column, &first);
    show (stream, "8000", &column, &first);
    show (stream, "10000", &column, &first);
+   show (stream, "4K", &column, &first);
+   show (stream, "4Kp", &column, &first);
+   show (stream, "4Kc", &column, &first);
+   show (stream, "4Km", &column, &first);
    fputc ('\n', stream);
  
    fprintf (stream, _("\
*************** MIPS options:\n\
*** 9357,9363 ****
--- 9420,9430 ----
    show (stream, "4010", &column, &first);
    show (stream, "4100", &column, &first);
    show (stream, "4650", &column, &first);
+   
    fputc ('\n', stream);
+ 
+   fprintf (stream, _("\
+ -mips32                 generate MIPS32 instructions\n"));
  
    fprintf(stream, _("\
  -mips16			generate mips16 instructions\n\
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/src/include/elf/mips.h,v
retrieving revision 1.7
diff -c -3 -p -r1.7 mips.h
*** include/elf/mips.h	2000/06/07 04:08:12	1.7
--- include/elf/mips.h	2000/08/30 15:05:00
*************** END_RELOC_NUMBERS (R_MIPS_maxext)
*** 153,158 ****
--- 153,159 ----
  #define E_MIPS_MACH_4100	0x00830000
  #define E_MIPS_MACH_4650	0x00850000
  #define E_MIPS_MACH_4111	0x00880000
+ #define E_MIPS_MACH_4K          0x00890000
  
  
  /* Processor specific section indices.  These sections do not actually
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.5
diff -c -3 -p -r1.5 mips.h
*** include/opcode/mips.h	2000/02/22 19:01:25	1.5
--- include/opcode/mips.h	2000/08/30 15:05:00
*************** Software Foundation, 59 Temple Place - S
*** 126,131 ****
--- 126,135 ----
  #define OP_MASK_MMISUB          0x1f
  #define OP_MASK_PERFREG		0x1f	/* Performance monitoring */
  #define OP_SH_PERFREG		1
+ #define OP_SH_SEL		0	/* Coprocessor select field */
+ #define OP_MASK_SEL		0x7
+ #define OP_SH_CODE20		6	/* 20 bit breakpoint code */
+ #define OP_MASK_CODE20		0xfffff
  
  /* This structure holds information for a particular instruction.  */
  
*************** struct mips_opcode
*** 183,188 ****
--- 187,193 ----
     "w" 5 bit same register used as both target and destination (OP_*_RT)
     "C" 25 bit coprocessor function code (OP_*_COPZ)
     "B" 20 bit syscall function code (OP_*_SYSCALL)
+    "m" 20 bit breakpoint code (OP_*_CODE20)
     "x" accept and ignore register name
     "z" must be zero register
  
*************** struct mips_opcode
*** 200,205 ****
--- 205,211 ----
     "E" 5 bit target register (OP_*_RT)
     "G" 5 bit destination register (OP_*_RD)
     "P" 5 bit performance-monitor register (OP_*_PERFREG)
+    "H" 3 bit select field (OP_*_SEL)
  
     Macro instructions:
     "A" General 32 bit expression
*************** struct mips_opcode
*** 215,221 ****
  
     Characters used so far, for quick reference when adding more:
     "<>(),"
!    "ABCDEFGILMNSTRVW"
     "abcdfhijklopqrstuvwxz"
  */
  
--- 221,227 ----
  
     Characters used so far, for quick reference when adding more:
     "<>(),"
!    "ABCDEFGHIJLMNPSTRVW"
     "abcdfhijklopqrstuvwxz"
  */
  
*************** struct mips_opcode
*** 320,325 ****
--- 326,334 ----
  /* Toshiba R3900 instruction.  */
  #define INSN_3900                   0x00000080
  
+ /* MIPS 4K family instructions */
+ #define INSN_MIPS32                 0x00000100
+ 
  /* 32-bit code running on a ISA3+ CPU. */
  #define INSN_GP32                   0x00001000
  
*************** struct mips_opcode
*** 344,350 ****
  	  )							\
  	 && ((insn)->membership & INSN_4100) != 0)		\
       || (cpu == 3900						\
! 	 && ((insn)->membership & INSN_3900) != 0))
  
  /* This is a list of macro expanded instructions.
   *
--- 353,361 ----
  	  )							\
  	 && ((insn)->membership & INSN_4100) != 0)		\
       || (cpu == 3900						\
! 	 && ((insn)->membership & INSN_3900) != 0)              \
!      || (cpu == 4750                                            \
! 	 && ((insn)->membership & INSN_MIPS32) != 0))
  
  /* This is a list of macro expanded instructions.
   *
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.6
diff -c -3 -p -r1.6 mips-dis.c
*** opcodes/mips-dis.c	2000/05/24 15:24:56	1.6
--- opcodes/mips-dis.c	2000/08/30 15:05:02
*************** print_insn_arg (d, l, pc, info)
*** 177,182 ****
--- 177,187 ----
  			     (l >> OP_SH_CODE2) & OP_MASK_CODE2);
        break;
  
+     case 'm':
+       (*info->fprintf_func) (info->stream, "0x%x",
+ 			     (l >> OP_SH_CODE20) & OP_MASK_CODE20);
+       break;
+ 
      case 'C':
        (*info->fprintf_func) (info->stream, "0x%x",
  			     (l >> OP_SH_COPZ) & OP_MASK_COPZ);
*************** print_insn_arg (d, l, pc, info)
*** 235,241 ****
--- 240,250 ----
  			     (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
        break;
  
+     case 'H':
+       (*info->fprintf_func) (info->stream, "%d", l & OP_MASK_SEL);
+       break;
  
+ 
      default:
        /* xgettext:c-format */
        (*info->fprintf_func) (info->stream,
*************** set_mips_isa_type (mach, isa, cputype)
*** 303,308 ****
--- 312,321 ----
        case bfd_mach_mips4650:
  	target_processor = 4650;
  	mips_isa = 3;
+ 	break;
+       case bfd_mach_mips4K:
+ 	target_processor = 4750;
+ 	mips_isa = 2;
  	break;
        case bfd_mach_mips5000:
  	target_processor = 5000;
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.8
diff -c -3 -p -r1.8 mips-opc.c
*** opcodes/mips-opc.c	2000/07/31 18:50:56	1.8
--- opcodes/mips-opc.c	2000/08/30 15:05:04
*************** Software Foundation, 59 Temple Place - S
*** 78,83 ****
--- 78,84 ----
  #define I4	INSN_ISA4
  #define I5	INSN_ISA5
  #define P3	INSN_4650
+ #define P4	INSN_MIPS32
  #define L1	INSN_4010
  #define V1      INSN_4100
  #define T3      INSN_3900
*************** const struct mips_opcode mips_builtin_op
*** 317,323 ****
  {"c.ngt.s", "M,S,T",	0x4600003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4|M1	},
  {"c.ngt.ps","S,T",	0x46c0003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
  {"c.ngt.ps","M,S,T",	0x46c0003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
! {"cache",   "k,o(b)",	0xbc000000, 0xfc000000, RD_b,		I3|T3|M1	},
  {"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
  {"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
  {"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
--- 318,324 ----
  {"c.ngt.s", "M,S,T",	0x4600003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4|M1	},
  {"c.ngt.ps","S,T",	0x46c0003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
  {"c.ngt.ps","M,S,T",	0x46c0003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
! {"cache",   "k,o(b)",	0xbc000000, 0xfc000000, RD_b,		I3|T3|M1|P4	},
  {"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
  {"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
  {"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
*************** const struct mips_opcode mips_builtin_op
*** 327,332 ****
--- 328,335 ----
  {"cfc1",    "t,S",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	I1	},
  {"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
  {"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3,	I1	},
+ {"clo",     "d,s",	0x70000021, 0xfc1f07ff, WR_d|RD_s,	P4	},
+ {"clz",     "d,s",	0x70000020, 0xfc1f07ff, WR_d|RD_s,	P4	},
  {"ctc0",    "t,G",	0x40c00000, 0xffe007ff,	COD|RD_t|WR_CC,	I1	},
  {"ctc1",    "t,G",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	I1	},
  {"ctc1",    "t,S",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	I1	},
*************** const struct mips_opcode mips_builtin_op
*** 355,361 ****
  /* dctr and dctw are used on the r5000.  */
  {"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,	I3	},
  {"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,	I3	},
! {"deret",   "",         0x4200001f, 0xffffffff,    0,	G2|M1	},
  /* For ddiv, see the comments about div.  */
  {"ddiv",    "z,s,t",	0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,	I3	},
  {"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,	I3	},
--- 358,364 ----
  /* dctr and dctw are used on the r5000.  */
  {"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,	I3	},
  {"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,	I3	},
! {"deret",   "",         0x4200001f, 0xffffffff,    0,	G2|M1|P4	},
  /* For ddiv, see the comments about div.  */
  {"ddiv",    "z,s,t",	0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,	I3	},
  {"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,	I3	},
*************** const struct mips_opcode mips_builtin_op
*** 427,433 ****
  {"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,	I3	},
  {"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,	I3	},
  {"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,	I3	},
! {"eret",    "",		0x42000018, 0xffffffff,	0,	I3|M1	},
  {"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
  {"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
  {"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
--- 430,436 ----
  {"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,	I3	},
  {"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,	I3	},
  {"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,	I3	},
! {"eret",    "",		0x42000018, 0xffffffff,	0,	I3|M1|P4	},
  {"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
  {"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
  {"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
*************** const struct mips_opcode mips_builtin_op
*** 524,542 ****
  {"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,	I3	},
  {"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,	I3	},
  {"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,	I4	},
! {"mad",	    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3	},
! {"madu",    "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3	},
  {"madd.d",  "D,R,S,T",	0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I4	},
  {"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
  {"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
  {"madd",    "s,t",	0x0000001c, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
  {"madd",    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	        G1|M1	},
  {"madd",    "d,s,t",	0x70000000, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1	},
  {"maddu",   "s,t",	0x0000001d, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
  {"maddu",   "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	G1|M1},
  {"maddu",   "d,s,t",	0x70000001, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1},
  {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	V1	},
  {"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,	I1	},
  {"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1},
  {"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1},
  {"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
--- 527,548 ----
  {"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,	I3	},
  {"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,	I3	},
  {"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,	I4	},
! {"mad",	    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3|P4	},
! {"madu",    "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3|P4	},
  {"madd.d",  "D,R,S,T",	0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I4	},
  {"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
  {"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
  {"madd",    "s,t",	0x0000001c, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
+ {"madd",    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
  {"madd",    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	        G1|M1	},
  {"madd",    "d,s,t",	0x70000000, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1	},
  {"maddu",   "s,t",	0x0000001d, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
+ {"maddu",   "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
  {"maddu",   "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	G1|M1},
  {"maddu",   "d,s,t",	0x70000001, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1},
  {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	V1	},
  {"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,	I1	},
+ {"mfc0",    "t,G,H",	0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,	P4	},
  {"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1},
  {"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1},
  {"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
*************** const struct mips_opcode mips_builtin_op
*** 550,556 ****
  {"movf.d",  "D,S,N",	0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
  {"movf.s",  "D,S,N",	0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
  {"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5	},
! {"movn",    "d,v,t",	0x0000000b, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1	},
  {"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,L1	},
  {"movn.d",  "D,S,t",	0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
  {"movn.s",  "D,S,t",	0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
--- 556,562 ----
  {"movf.d",  "D,S,N",	0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
  {"movf.s",  "D,S,N",	0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
  {"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5	},
! {"movn",    "d,v,t",	0x0000000b, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1|P4	},
  {"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,L1	},
  {"movn.d",  "D,S,t",	0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
  {"movn.s",  "D,S,t",	0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
*************** const struct mips_opcode mips_builtin_op
*** 558,564 ****
  {"movt.d",  "D,S,N",	0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
  {"movt.s",  "D,S,N",	0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
  {"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5},
! {"movz",    "d,v,t",	0x0000000a, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1	},
  {"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,L1	},
  {"movz.d",  "D,S,t",	0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
  {"movz.s",  "D,S,t",	0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
--- 564,570 ----
  {"movt.d",  "D,S,N",	0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
  {"movt.s",  "D,S,N",	0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
  {"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5},
! {"movz",    "d,v,t",	0x0000000a, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1|P4	},
  {"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,L1	},
  {"movz.d",  "D,S,t",	0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
  {"movz.s",  "D,S,t",	0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
*************** const struct mips_opcode mips_builtin_op
*** 567,574 ****
--- 573,583 ----
  {"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
  {"msub.ps", "D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
  {"msub",    "s,t",	0x0000001e, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,L1	},
+ {"msub",    "s,t",	0x70000004, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
  {"msubu",   "s,t",	0x0000001f, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,L1	},
+ {"msubu",   "s,t",	0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
  {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	I1	},
+ {"mtc0",    "t,G,H",	0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,	P4	},
  {"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
  {"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
  {"mtc2",    "t,G",	0x48800000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	I1	},
*************** const struct mips_opcode mips_builtin_op
*** 578,584 ****
  {"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},
  {"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},
  {"mul.ps",  "D,V,T",	0x46c00002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
! {"mul",     "d,v,t",	0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3},
  {"mul",     "d,v,t",	0,    (int) M_MUL,	INSN_MACRO,	I1	},
  {"mul",     "d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,	I1	},
  {"mulo",    "d,v,t",	0,    (int) M_MULO,	INSN_MACRO,	I1	},
--- 587,593 ----
  {"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},
  {"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},
  {"mul.ps",  "D,V,T",	0x46c00002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
! {"mul",     "d,v,t",	0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,	P3|P4	},
  {"mul",     "d,v,t",	0,    (int) M_MUL,	INSN_MACRO,	I1	},
  {"mul",     "d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,	I1	},
  {"mulo",    "d,v,t",	0,    (int) M_MULO,	INSN_MACRO,	I1	},
*************** const struct mips_opcode mips_builtin_op
*** 611,617 ****
  {"pll.ps",  "D,V,T",	0x46c0002c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
  {"plu.ps",  "D,V,T",	0x46c0002d, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
  
! {"pref",    "k,o(b)",	0xcc000000, 0xfc000000, RD_b,		G3|M1	},
  {"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t,	I4	},
  
  {"pul.ps",  "D,V,T",	0x46c0002e, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
--- 620,626 ----
  {"pll.ps",  "D,V,T",	0x46c0002c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
  {"plu.ps",  "D,V,T",	0x46c0002d, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
  
! {"pref",    "k,o(b)",	0xcc000000, 0xfc000000, RD_b,		G3|M1|P4},
  {"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t,	I4	},
  
  {"pul.ps",  "D,V,T",	0x46c0002e, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
*************** const struct mips_opcode mips_builtin_op
*** 648,653 ****
--- 657,663 ----
  {"sdbbp",   "",		0x0000000e, 0xffffffff,	TRAP,           G2|M1	},
  {"sdbbp",   "c",	0x0000000e, 0xfc00ffff,	TRAP,		G2|M1	},
  {"sdbbp",   "c,q",	0x0000000e, 0xfc00003f,	TRAP,		G2|M1	},
+ {"sdbbp",   "m",	0x7000003f, 0xfc00003f, TRAP,		P4	},
  {"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
  {"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
  {"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,	I2	},
*************** const struct mips_opcode mips_builtin_op
*** 755,763 ****
  {"tgeu",    "s,t,q",	0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
  {"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,	I2		}, /* tgeiu */
  {"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,	I2	},
! {"tlbp",    "",		0x42000008, 0xffffffff,	INSN_TLB,	I1|M1	},
! {"tlbr",    "",		0x42000001, 0xffffffff,	INSN_TLB,	I1|M1	},
! {"tlbwi",   "",		0x42000002, 0xffffffff,	INSN_TLB,	I1|M1	},
  {"tlbwr",   "",		0x42000006, 0xffffffff,	INSN_TLB,	I1|M1	},
  {"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,	I2		},
  {"tlt",     "s,t",	0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,	I2	 },
--- 765,773 ----
  {"tgeu",    "s,t,q",	0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
  {"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,	I2		}, /* tgeiu */
  {"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,	I2	},
! {"tlbp",    "",		0x42000008, 0xffffffff,	INSN_TLB,	I1|M1|P4},
! {"tlbr",    "",		0x42000001, 0xffffffff,	INSN_TLB,	I1|M1|P4},
! {"tlbwi",   "",		0x42000002, 0xffffffff,	INSN_TLB,	I1|M1|P4},
  {"tlbwr",   "",		0x42000006, 0xffffffff,	INSN_TLB,	I1|M1	},
  {"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,	I2		},
  {"tlt",     "s,t",	0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,	I2	 },
*************** const struct mips_opcode mips_builtin_op
*** 799,805 ****
  {"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
  {"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,	I1	},
  {"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,	I1	},
! {"wait",    "",		0x42000020, 0xffffffff,	TRAP,	I3|M1	},
  {"waiti",   "",		0x42000020, 0xffffffff,	TRAP,	L1	},
  {"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,	L1	},
  /* No hazard protection on coprocessor instructions--they shouldn't
--- 809,815 ----
  {"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
  {"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,	I1	},
  {"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,	I1	},
! {"wait",    "",		0x42000020, 0xffffffff,	TRAP,	I3|M1|P4	},
  {"waiti",   "",		0x42000020, 0xffffffff,	TRAP,	L1	},
  {"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,	L1	},
  /* No hazard protection on coprocessor instructions--they shouldn't
Index: gas/doc/as.texinfo
===================================================================
RCS file: /exports/disk1/synergenix/master/binutils/gas/doc/as.texinfo,v
retrieving revision 1.1.1.1
diff -c -2 -p -r1.1.1.1 as.texinfo
*** gas/doc/as.texinfo	2000/06/16 12:09:09	1.1.1.1
--- gas/doc/as.texinfo	2000/08/30 11:48:40
*************** Here is a brief summary of how to invoke
*** 266,270 ****
  @ifset MIPS
   [ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
!  [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ]
   [ --trap ] [ --break ]
   [ --emulation=@var{name} ]
--- 266,270 ----
  @ifset MIPS
   [ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
!  [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ] [ -mips32 ] [ -no-mips32 ]
   [ --trap ] [ --break ]
   [ --emulation=@var{name} ]
*************** the @samp{mad} and @samp{madu} instructi
*** 595,598 ****
--- 595,603 ----
  instructions around accesses to the @samp{HI} and @samp{LO} registers.
  @samp{-no-m4650} turns off this option.
+ 
+ @item -mips32
+ @itemx -no-mips32
+ Generate code for the @sc{MIPS32} architecture. This tells the assembler to accept
+ ISA level 2 instructions and MIPS32 extensions including some @sc{r4000} instructions.
  
  @item -mcpu=@var{CPU}
Index: gas/doc/c-mips.texi
===================================================================
RCS file: /exports/disk1/synergenix/master/binutils/gas/doc/c-mips.texi,v
retrieving revision 1.1.1.1
diff -c -2 -p -r1.1.1.1 c-mips.texi
*** gas/doc/c-mips.texi	2000/06/16 12:09:09	1.1.1.1
--- gas/doc/c-mips.texi	2000/08/30 11:48:40
*************** understood.  Valid @var{cpu} value are:
*** 136,139 ****
--- 136,143 ----
  8000,
  10000
+ 4K,
+ 4Kc
+ 4Km
+ 4Kp
  @end quotation

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