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patch for opcodes: PowerPC vector unit support
- To: binutils at sourceware dot cygnus dot com
- Subject: patch for opcodes: PowerPC vector unit support
- From: jtc at redback dot com (J.T. Conklin)
- Date: 02 May 2000 11:20:17 -0700
- Reply-To: jtc at redback dot com
2000-05-02 J.T. Conklin <jtc@redback.com>
* ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
vector unit operands.
(VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector
unit instruction formats.
(PPCVEC): New macro, mask for vector instructions.
(powerpc_operands): Add table entries for above operand types.
(powerpc_opcodes): Add table entries for vector instructions.
* ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask.
(print_insn_little_powerpc): Likewise.
(print_insn_powerpc): Prepend 'v' when printing vector registers.
Index: ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.4
diff -c -r1.4 ppc-opc.c
*** ppc-opc.c 2000/04/14 04:16:58 1.4
--- ppc-opc.c 2000/05/02 18:01:00
***************
*** 396,401 ****
--- 396,434 ----
/* The UI field in a D form instruction. */
#define UI U + 1
{ 16, 0, 0, 0, 0 },
+
+ /* The VA field in a VA, VX or VXR form instruction. */
+ #define VA UI + 1
+ #define VA_MASK (0x1f << 16)
+ {5, 16, 0, 0, PPC_OPERAND_VR},
+
+ /* The VB field in a VA, VX or VXR form instruction. */
+ #define VB VA + 1
+ #define VB_MASK (0x1f << 11)
+ {5, 11, 0, 0, PPC_OPERAND_VR},
+
+ /* The VC field in a VA form instruction. */
+ #define VC VB + 1
+ #define VC_MASK (0x1f << 6)
+ {5, 6, 0, 0, PPC_OPERAND_VR},
+
+ /* The VD or VS field in a VA, VX, VXR or X form instruction. */
+ #define VD VC + 1
+ #define VS VD
+ #define VD_MASK (0x1f << 21)
+ {5, 21, 0, 0, PPC_OPERAND_VR},
+
+ /* The SIMM field in a VX form instruction. */
+ #define SIMM VD + 1
+ { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
+
+ /* The UIMM field in a VX form instruction. */
+ #define UIMM SIMM + 1
+ { 5, 16, 0, 0, 0 },
+
+ /* The SHB field in a VA form instruction. */
+ #define SHB UIMM + 1
+ { 4, 6, 0, 0, 0 },
};
/* The functions used to insert and extract complicated operands. */
***************
*** 1105,1110 ****
--- 1138,1161 ----
#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
+ /* An VX form instruction. */
+ #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
+
+ /* The mask for an VX form instruction. */
+ #define VX_MASK VX(0x3f, 0x7ff)
+
+ /* An VA form instruction. */
+ #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f))
+
+ /* The mask for an VA form instruction. */
+ #define VXA_MASK VXA(0x3f, 0x7f)
+
+ /* An VXR form instruction. */
+ #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
+
+ /* The mask for a VXR form instruction. */
+ #define VXR_MASK VXR(0x3f, 0x3ff, 1)
+
/* An X form instruction. */
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
***************
*** 1272,1277 ****
--- 1323,1329 ----
#define PPC403 PPC
#define PPC750 PPC
#define PPC860 PPC
+ #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
***************
*** 1348,1353 ****
--- 1400,1563 ----
{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
+
+ { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
+ { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } },
+ { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
+ { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
+ { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
+ { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
+ { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
+ { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
+ { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
+ { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
+ { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
+ { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
+ { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
+ { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
+ { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
+ { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
+ { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+ { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
+ { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vslw", VX(4, 338), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
+ { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
+ { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
+ { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
+ { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
+ { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
+ { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
+ { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
+ { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
+ { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
+ { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
+ { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
+ { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
+ { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
***************
*** 2853,2858 ****
--- 3063,3081 ----
{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
+
+ { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
+ { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
+ { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
+ { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
+ { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
+ { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
+ { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
+ { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
+ { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
+ { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
+ { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
+ { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
Index: ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.2
diff -c -r1.2 ppc-dis.c
*** ppc-dis.c 2000/04/14 04:16:58 1.2
--- ppc-dis.c 2000/05/02 18:01:01
***************
*** 33,39 ****
int bigendian, int dialect));
/* Print a big endian PowerPC instruction. For convenience, also
! disassemble instructions supported by the Motorola PowerPC 601. */
int
print_insn_big_powerpc (memaddr, info)
--- 33,40 ----
int bigendian, int dialect));
/* Print a big endian PowerPC instruction. For convenience, also
! disassemble instructions supported by the Motorola PowerPC 601
! and the Altivec vector unit. */
int
print_insn_big_powerpc (memaddr, info)
***************
*** 41,51 ****
struct disassemble_info *info;
{
return print_insn_powerpc (memaddr, info, 1,
! PPC_OPCODE_PPC | PPC_OPCODE_601);
}
/* Print a little endian PowerPC instruction. For convenience, also
! disassemble instructions supported by the Motorola PowerPC 601. */
int
print_insn_little_powerpc (memaddr, info)
--- 42,54 ----
struct disassemble_info *info;
{
return print_insn_powerpc (memaddr, info, 1,
! PPC_OPCODE_PPC | PPC_OPCODE_601 |
! PPC_OPCODE_ALTIVEC);
}
/* Print a little endian PowerPC instruction. For convenience, also
! disassemble instructions supported by the Motorola PowerPC 601
! and the Altivec vector unit. */
int
print_insn_little_powerpc (memaddr, info)
***************
*** 53,59 ****
struct disassemble_info *info;
{
return print_insn_powerpc (memaddr, info, 0,
! PPC_OPCODE_PPC | PPC_OPCODE_601);
}
/* Print a POWER (RS/6000) instruction. */
--- 56,63 ----
struct disassemble_info *info;
{
return print_insn_powerpc (memaddr, info, 0,
! PPC_OPCODE_PPC | PPC_OPCODE_601 |
! PPC_OPCODE_ALTIVEC);
}
/* Print a POWER (RS/6000) instruction. */
***************
*** 181,186 ****
--- 185,192 ----
(*info->fprintf_func) (info->stream, "r%ld", value);
else if ((operand->flags & PPC_OPERAND_FPR) != 0)
(*info->fprintf_func) (info->stream, "f%ld", value);
+ else if ((operand->flags & PPC_OPERAND_VR) != 0)
+ (*info->fprintf_func) (info->stream, "v%ld", value);
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
(*info->print_address_func) (memaddr + value, info);
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
--
J.T. Conklin
RedBack Networks