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patch for 102785-CR-1
- To: binutils at sourceware dot cygnus dot com
- Subject: patch for 102785-CR-1
- From: Chandra Chavva <cchavva at cygnus dot com>
- Date: Fri, 11 Feb 2000 16:25:11 -0800 (PST)
- cc: gcc-patches at gcc dot gnu dot org
Hi,
The case 102785-CR-1 is mitsubishi d30v. This is want they want
Here is an excerpt from the PR.
>1. The combinations listed as follows are prohibited.
> 1.1 Pararell executions
> 1.1.1
> MU: ST2W or ST4HB
> IU: ADDHppp,SUBHppp, SATHp, SRC
The correct rule is as follows.
1.1 Pararell executions
1.1.1
MU: All the store instructions
(STB,STH,STHH, STW,ST2W,ST4HB,ST2H)
IU: ADDHppp,SUBHppp, SATHp, SRC
We are sorry for our internal miscommunication.
Here is the patch for it. Please let me know if the patch is fine or not.
Thanks
Chandra
Index: ChangeLog
===================================================================
RCS file: /cvs/cvsfiles/devo/opcodes/ChangeLog,v
retrieving revision 1.1024.8.2
diff -p -r1.1024.8.2 ChangeLog
*** ChangeLog 1999/10/29 02:46:35 1.1024.8.2
--- ChangeLog 2000/02/11 23:42:15
***************
*** 1,3 ****
--- 1,8 ----
+ 2000-02-11 Chandra Chavva <cchavva@cygnus.com>
+
+ * d30v-opc.c (d30v_opcode_tab) : Added FLAG_2WORD to ST2H, STB, STH
+ STHH, STW and ST2H opcodes to prohibit parallel procedure.
+
1999-10-29 Nick Clifton <nickc@cygnus.com>
* d30v-opc.c (mvtacc): Use format SHORT_AR not SHORT_AA
Index: d30v-opc.c
===================================================================
RCS file: /cvs/cvsfiles/devo/opcodes/d30v-opc.c,v
retrieving revision 1.19.8.1
diff -p -r1.19.8.1 d30v-opc.c
*** d30v-opc.c 1999/10/29 02:46:39 1.19.8.1
--- d30v-opc.c 2000/02/11 23:42:15
*************** const struct d30v_opcode d30v_opcode_tab
*** 311,323 ****
{ "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 },
{ "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },
{ "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 },
! { "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM, 0 },
{ "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 },
{ "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 },
! { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
! { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
! { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
! { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
{ "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
{ "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
{ "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 },
--- 311,323 ----
{ "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 },
{ "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },
{ "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 },
! { "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 },
{ "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 },
{ "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 },
! { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 },
! { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 },
! { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 },
! { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 },
{ "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
{ "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
{ "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 },
Index: d30v.h
===================================================================
RCS file: /cvs/cvsfiles/devo/include/opcode/d30v.h,v
retrieving revision 1.10.32.1
diff -p -r1.10.32.1 d30v.h
*** d30v.h 1999/10/29 02:45:47 1.10.32.1
--- d30v.h 2000/02/12 00:23:23
*************** struct d30v_opcode
*** 147,153 ****
#define FLAG_JMP (1L<<13) /* instruction is a branch */
#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */
#define FLAG_MEM (1L<<15) /* reads/writes memory */
! #define FLAG_2WORD (1L<<16) /* 2 word/4 byte operation */
#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */
#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */
#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */
--- 147,154 ----
#define FLAG_JMP (1L<<13) /* instruction is a branch */
#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */
#define FLAG_MEM (1L<<15) /* reads/writes memory */
! #define FLAG_2WORD (1L<<16) /* 1 word/2 byte &2 word/4 byte
! operations. Need to be fixed later */
#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */
#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */
#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */