SIM: Add support for MCore 340 processor

[Nick Clifton <nickc at cygnus dot com>]

Hi Guys,

  As preparation for submitting the Cygnus version of the port of GCC
  to Motorola's M*Core processor, I am submitting (and applying!) the
  following patch to SIM to add support for the M*Core 340 part.

Cheers
	Nick

2000-02-10  Nick Clifton  <nickc@cygnus.com>

	* interp.c (target_big_endian): New variable.
	(mcore_extract_unsigned_integer, mcore_store_unsigned_integer,
	wlat, rlat, sim_resume, sim_load): Add supprot for little
	endian targets. 

Index: sim/mcore/interp.c
===================================================================
RCS file: /cvs/src//src/sim/mcore/interp.c,v
retrieving revision 1.1.1.7
diff -p -r1.1.1.7 interp.c
*** interp.c	2000/01/25 02:40:50	1.1.1.7
--- interp.c	2000/02/10 21:54:29
*************** with this program; if not, write to the 
*** 36,41 ****
--- 36,42 ----
  typedef long int           word;
  typedef unsigned long int  uword;
  
+ static int            target_big_endian = 0;
  static unsigned long  heap_ptr = 0;
  host_callback *       callback;
  
*************** mcore_extract_unsigned_integer (addr, le
*** 58,64 ****
--- 59,71 ----
       the least significant.  */
    retval = 0;
  
+   if (! target_big_endian)
      {
+       for (p = endaddr; p > startaddr;)
+ 	retval = (retval << 8) | * -- p;
+     }
+   else
+     {
        for (p = startaddr; p < endaddr;)
  	retval = (retval << 8) | * p ++;
      }
*************** mcore_store_unsigned_integer (addr, len,
*** 76,81 ****
--- 83,97 ----
    unsigned char * startaddr = (unsigned char *)addr;
    unsigned char * endaddr = startaddr + len;
  
+   if (! target_big_endian)
+     {
+       for (p = startaddr; p < endaddr;)
+ 	{
+ 	  * p ++ = val & 0xff;
+ 	  val >>= 8;
+ 	}
+     }
+   else
      {
        for (p = endaddr; p > startaddr;)
  	{
*************** wlat (x, v)
*** 216,221 ****
--- 232,245 ----
        
  	  cpu.asregs.exception = SIGBUS;
  	}
+       else if (! target_big_endian)
+ 	{
+ 	  unsigned char * p = cpu.mem + x;
+ 	  p[3] = v >> 24;
+ 	  p[2] = v >> 16;
+ 	  p[1] = v >> 8;
+ 	  p[0] = v;
+ 	}
        else
  	{
  	  unsigned char * p = cpu.mem + x;
*************** what (x, v)
*** 248,253 ****
--- 272,283 ----
        
  	  cpu.asregs.exception = SIGBUS;
  	}
+       else if (! target_big_endian)
+ 	{
+ 	  unsigned char * p = cpu.mem + x;
+ 	  p[1] = v >> 8;
+ 	  p[0] = v;
+ 	}
        else
  	{
  	  unsigned char * p = cpu.mem + x;
*************** rlat (x)
*** 299,304 ****
--- 329,339 ----
  	  cpu.asregs.exception = SIGBUS;
  	  return 0;
  	}
+       else if (! target_big_endian)
+ 	{
+ 	  unsigned char * p = cpu.mem + x;
+ 	  return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
+ 	}
        else
  	{
  	  unsigned char * p = cpu.mem + x;
*************** rhat (x)
*** 329,334 ****
--- 364,374 ----
  	  cpu.asregs.exception = SIGBUS;
  	  return 0;
  	}
+       else if (! target_big_endian)
+ 	{
+ 	  unsigned char * p = cpu.mem + x;
+ 	  return (p[1] << 8) | p[0];
+ 	}
        else
  	{
  	  unsigned char * p = cpu.mem + x;
*************** sim_resume (sd, step, siggnal)
*** 762,772 ****
--- 802,818 ----
        
        if (pc & 02)
  	{
+ 	  if (! target_big_endian)
+ 	    inst = ibuf >> 16;
+ 	  else
  	    inst = ibuf & 0xFFFF;
  	  needfetch = 1;
  	}
        else
  	{
+ 	  if (! target_big_endian)
+ 	    inst = ibuf & 0xFFFF;
+ 	  else
  	    inst = ibuf >> 16;
  	}
  
*************** sim_load (sd, prog, abfd, from_tty)
*** 1952,1957 ****
--- 1998,2004 ----
    if (prog_bfd == NULL)
      return SIM_RC_FAIL;
    
+   target_big_endian = bfd_big_endian (prog_bfd);
      
    if (abfd == NULL)
      bfd_close (prog_bfd);