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Re: R_MIPS16_GPREL patch
Date: Wed, 14 Jul 1999 10:56:51 -0700
From: Richard Henderson <rth@cygnus.com>
On Wed, Jul 14, 1999 at 09:55:41AM -0700, Mark Mitchell wrote:
> + /* R_MIPS16_GPREL is used for GP-relative addressing in mips16
> + mode. A typical instruction will have a format like this:
>
> + +--------------+--------------------------------+
> + ! EXTEND ! Imm 10:5 ! Imm 15:11 !
> + +--------------+--------------------------------+
> + ! Major ! rx ! ry ! Imm 4:0 !
> + +--------------+--------------------------------+
Perhaps it didn't mention it, but I'm fairly sure you have
the same little-endian issue to deal with here. Or maybe
I'm just missing where the word swap is happening?
Yes, when viewing the values as 32 bits, there is the same word swap
issue here. Sorry I missed it when looking at the code.
I think of the cases as different. R_MIPS16_26 is used for an
instruction which is 32 bits even in 16 bit mode. R_MIPS16_GPREL is
actually two instructions: the extend instruction followed by the
actual instruction. This is conventional way that the mips16 chip
handles large opcodes: an extend instruction precedes a conventional
instruction.
Mark, if you look at the relocate_section code from before your
changes, you'll see that it treats the R_MIPS16_26 relocation as
operating on two separate 16-bit instructions.
Ian