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Changes checked in to ARM code
- To: binutils at sourceware dot cygnus dot com
- Subject: Changes checked in to ARM code
- From: Donald Lindsay <dlindsay at cygnus dot com>
- Date: Mon, 15 Nov 1999 20:34:14 -0800 (PST)
I have checked in changes, fixed to address the comments made by reviewers
Nick Clifton and Jeff Law. The changes compile and test in devo: hopefully
the mechanical changes getting them from devo to sourceware didn't break
anything.
Don
Index: arm-dis.c
===================================================================
RCS file: /cvs/binutils/binutils/opcodes/arm-dis.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -p -r1.7 -r1.8
*** arm-dis.c 1999/10/27 18:14:17 1.7
--- arm-dis.c 1999/11/16 03:37:02 1.8
*************** print_insn_arm (pc, info, given)
*** 491,496 ****
--- 491,504 ----
func (stream, "\t; IMBRange");
}
break;
+ case 'X':
+ {
+ long reg;
+ reg = given >> bitstart;
+ reg &= (2 << (bitend - bitstart)) - 1;
+ func (stream, "%01x", reg & 0xf);
+ }
+ break;
case 'f':
{
long reg;
Index: arm-opc.h
===================================================================
RCS file: /cvs/binutils/binutils/opcodes/arm-opc.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -p -r1.1 -r1.2
*** arm-opc.h 1999/05/03 07:28:59 1.1
--- arm-opc.h 1999/11/16 03:37:02 1.2
*************** struct thumb_opcode
*** 33,38 ****
--- 33,39 ----
%% %
%<bitfield>d print the bitfield in decimal
%<bitfield>x print the bitfield in hex
+ %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
%<bitfield>r print as an ARM register
%<bitfield>f print a floating point constant if >7 else a
floating point register
Mon Nov 15 19:34:58 1999 Donald Lindsay <dlindsay@cygnus.com>
* arm-dis.c (print_insn_arm): Added general purpose 'X' format.
* arm-opc.h (print_insn_arm): Added comment documenting
the 'X' format just added to arm-dis.c.
Index: tc-arm.c
===================================================================
RCS file: /cvs/binutils/binutils/gas/config/tc-arm.c,v
retrieving revision 1.25
diff -p -r1.25 tc-arm.c
*** tc-arm.c 1999/10/28 03:03:53 1.25
--- tc-arm.c 1999/11/16 04:09:51
***************
*** 52,62 ****
#define ARM_HALFWORD 0x00000020 /* allow half word loads */
#define ARM_THUMB 0x00000040 /* allow BX instruction */
#define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
/* Architectures are the sum of the base and extensions */
#define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
! #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
/* Some useful combinations: */
--- 52,63 ----
#define ARM_HALFWORD 0x00000020 /* allow half word loads */
#define ARM_THUMB 0x00000040 /* allow BX instruction */
#define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
+ #define ARM_EXT_V5E 0x00000200 /* "El Segundo" */
/* Architectures are the sum of the base and extensions */
#define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
! #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5 )
#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
/* Some useful combinations: */
*************** static void do_mrs PARAMS ((char *, uns
*** 439,444 ****
--- 440,446 ----
static void do_mull PARAMS ((char *, unsigned long));
/* ARM THUMB */
static void do_bx PARAMS ((char *, unsigned long));
+
/* Coprocessor Instructions */
static void do_cdp PARAMS ((char *, unsigned long));
*************** static bfd_reloc_code_real_type arm_pars
*** 504,514 ****
#define LONGEST_INST 5
struct asm_opcode
{
CONST char * template; /* Basic string to match */
unsigned long value; /* Basic instruction code */
! CONST char * comp_suffix; /* Compulsory suffix that must follow conds */
CONST struct asm_flg * flags; /* Bits to toggle if flag 'n' set */
unsigned long variants; /* Which CPU variants this exists for */
/* Function to call to parse args */
--- 506,521 ----
#define LONGEST_INST 5
+
struct asm_opcode
{
CONST char * template; /* Basic string to match */
unsigned long value; /* Basic instruction code */
!
! /* Compulsory suffix that must follow conds. If "", then the
! instruction is not conditional and must have no suffix. */
! CONST char * comp_suffix;
!
CONST struct asm_flg * flags; /* Bits to toggle if flag 'n' set */
unsigned long variants; /* Which CPU variants this exists for */
/* Function to call to parse args */
*************** static CONST struct reg_entry reg_table[
*** 876,883 ****
{NULL, 0}
};
! #define BAD_ARGS _("Bad arguments to instruction");
! #define BAD_PC _("r15 not allowed here");
static struct hash_control * arm_ops_hsh = NULL;
static struct hash_control * arm_tops_hsh = NULL;
--- 883,892 ----
{NULL, 0}
};
! #define BAD_ARGS _("Bad arguments to instruction")
! #define BAD_PC _("r15 not allowed here")
! #define BAD_FLAGS _("Instruction should not have flags")
! #define BAD_COND _("Instruction is not conditional")
static struct hash_control * arm_ops_hsh = NULL;
static struct hash_control * arm_tops_hsh = NULL;
*************** s_thumb_set (equiv)
*** 1360,1366 ****
THUMB_SET_FUNC (symbolP, 1);
ARM_SET_THUMB (symbolP, 1);
! #if defined OBJ_COFF || defined OBJ_ELF
ARM_SET_INTERWORK (symbolP, support_interwork);
#endif
}
--- 1369,1375 ----
THUMB_SET_FUNC (symbolP, 1);
ARM_SET_THUMB (symbolP, 1);
! #if defined OBJ_ELF || defined OBJ_COFF
ARM_SET_INTERWORK (symbolP, support_interwork);
#endif
}
*************** do_bx (str, flags)
*** 3320,3332 ****
skip_whitespace (str);
if ((reg = reg_required_here (&str, 0)) == FAIL)
! return;
if (reg == REG_PC)
! as_tsktsk (_("Use of r15 in bx has undefined behaviour"));
end_of_line (str);
- return;
}
static void
--- 3329,3343 ----
skip_whitespace (str);
if ((reg = reg_required_here (&str, 0)) == FAIL)
! {
! inst.error = BAD_ARGS;
! return;
! }
if (reg == REG_PC)
! inst.error = BAD_PC;
end_of_line (str);
}
static void
*************** do_co_reg (str, flags)
*** 3487,3492 ****
--- 3498,3507 ----
return;
}
}
+ if (flags)
+ {
+ inst.error = BAD_COND;
+ }
end_of_line (str);
return;
*************** do_t_arit (str)
*** 4502,4516 ****
skip_whitespace (str);
! if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
! return;
!
! if (skip_past_comma (&str) == FAIL
|| (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
{
! if (! inst.error)
! inst.error = BAD_ARGS;
! return;
}
if (skip_past_comma (&str) != FAIL)
--- 4517,4528 ----
skip_whitespace (str);
! if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
! || skip_past_comma (&str) == FAIL
|| (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
{
! inst.error = BAD_ARGS;
! return;
}
if (skip_past_comma (&str) != FAIL)
*************** md_apply_fix3 (fixP, val, seg)
*** 5326,5332 ****
&& S_GET_SEGMENT (fixP->fx_addsy) != seg)
{
if (target_oabi
! && fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH)
value = 0;
else
value += md_pcrel_from (fixP);
--- 5338,5345 ----
&& S_GET_SEGMENT (fixP->fx_addsy) != seg)
{
if (target_oabi
! && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
! ))
value = 0;
else
value += md_pcrel_from (fixP);
*************** md_apply_fix3 (fixP, val, seg)
*** 5524,5529 ****
--- 5537,5543 ----
md_number_to_chars (buf, newval, INSN_SIZE);
break;
+
case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
newval = md_chars_to_number (buf, THUMB_SIZE);
{
*************** md_assemble (str)
*** 6053,6058 ****
--- 6067,6079 ----
if (opcode)
{
+ /* Check that this instruction is supported for this CPU. */
+ if ((opcode->variants & cpu_variant) == 0)
+ {
+ as_bad (_("selected processor does not support this opcode"));
+ return;
+ }
+
inst.instruction = opcode->value;
inst.size = opcode->size;
(*opcode->parms)(p);
*************** md_assemble (str)
*** 6063,6068 ****
--- 6084,6090 ----
else
{
CONST struct asm_opcode * opcode;
+ unsigned long cond_code;
inst.size = INSN_SIZE;
/* p now points to the end of the opcode, probably white space, but we
*************** md_assemble (str)
*** 6089,6099 ****
inst.instruction = opcode->value;
if (q == p) /* Just a simple opcode. */
{
! if (opcode->comp_suffix != 0)
! as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
! opcode->comp_suffix);
else
{
inst.instruction |= COND_ALWAYS;
(*opcode->parms)(q, 0);
}
--- 6111,6128 ----
inst.instruction = opcode->value;
if (q == p) /* Just a simple opcode. */
{
! if (opcode->comp_suffix)
! {
! if (*opcode->comp_suffix != '\0')
! as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
! str, opcode->comp_suffix);
! else
! /* Not a conditional instruction. */
! (*opcode->parms)(q, 0);
! }
else
{
+ /* A conditional instruction with default condition. */
inst.instruction |= COND_ALWAYS;
(*opcode->parms)(q, 0);
}
*************** md_assemble (str)
*** 6101,6107 ****
return;
}
! /* Now check for a conditional. */
r = q;
if (p - r >= 2)
{
--- 6130,6136 ----
return;
}
! /* Not just a simple opcode. Check if extra is a conditional. */
r = q;
if (p - r >= 2)
{
*************** md_assemble (str)
*** 6117,6134 ****
as_tsktsk (
_("Warning: Use of the 'nv' conditional is deprecated\n"));
! inst.instruction |= cond->value;
r += 2;
}
else
! inst.instruction |= COND_ALWAYS;
}
else
! inst.instruction |= COND_ALWAYS;
/* If there is a compulsory suffix, it should come here, before
any optional flags. */
! if (opcode->comp_suffix)
{
CONST char *s = opcode->comp_suffix;
--- 6146,6179 ----
as_tsktsk (
_("Warning: Use of the 'nv' conditional is deprecated\n"));
! cond_code = cond->value;
r += 2;
}
else
! cond_code = COND_ALWAYS;
}
else
! cond_code = COND_ALWAYS;
+
+ /* Apply the conditional, or complain it's not allowed. */
+ if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
+ {
+ /* Instruction isn't conditional */
+ if (cond_code != COND_ALWAYS)
+ {
+ as_bad (_("Opcode `%s' is unconditional\n"), str);
+ return;
+ }
+ }
+ else
+ /* Instruction is conditional: set the condition into it. */
+ inst.instruction |= cond_code;
+
+
/* If there is a compulsory suffix, it should come here, before
any optional flags. */
! if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
{
CONST char *s = opcode->comp_suffix;
*************** _("Warning: Use of the 'nv' conditional
*** 6228,6234 ****
if (regnum != FAIL)
insert_reg_alias (str, regnum);
else
! as_warn (_("register '%s' does not exist"), q);
}
else if (regnum != FAIL)
{
--- 6273,6279 ----
if (regnum != FAIL)
insert_reg_alias (str, regnum);
else
! as_warn (_("register '%s' does not exist\n"), q);
}
else if (regnum != FAIL)
{
*************** _("Warning: Use of the 'nv' conditional
*** 6265,6271 ****
* -m[arm]8[10] Arm 8 processors
* -m[arm]9[20][tdmi] Arm 9 processors
* -mstrongarm[110[0]] StrongARM processors
! * -m[arm]v[2345] Arm architecures
* -mall All (except the ARM1)
* FP variants:
* -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
--- 6310,6316 ----
* -m[arm]8[10] Arm 8 processors
* -m[arm]9[20][tdmi] Arm 9 processors
* -mstrongarm[110[0]] StrongARM processors
! * -m[arm]v[2345] Arm architectures
* -mall All (except the ARM1)
* FP variants:
* -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
*************** md_parse_option (c, arg)
*** 6532,6537 ****
--- 6577,6583 ----
else
goto bad;
break;
+
case 's':
if (streq (str, "strongarm")
*************** md_parse_option (c, arg)
*** 6576,6592 ****
default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
}
break;
!
case '5':
cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
-
switch (*++str)
{
case 't': cpu_variant |= ARM_THUMB; break;
case 0: break;
default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
}
break;
default:
as_bad (_("Invalid architecture variant -m%s"), arg);
--- 6622,6639 ----
default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
}
break;
!
case '5':
cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
switch (*++str)
{
case 't': cpu_variant |= ARM_THUMB; break;
+ case 'e': cpu_variant |= ARM_EXT_V5E; break;
case 0: break;
default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
}
break;
+
default:
as_bad (_("Invalid architecture variant -m%s"), arg);
Mon Nov 15 20:12:43 1999 Donald Lindsay <dlindsay@cygnus.com>
* config/tc-arm.c (do_mia,do_mar,do_mra,do_pld,do_ldrl,do_co_reg): Small
improvements in error checking.
(md_assemble): Support for unconditional ARM instructions.
(md_parse_option): Support for -m[arm]v5e flag.