[binutils-gdb] RISC-V: Disassemble x0 based addresses as 0.

[Jim Wilson <wilson at sourceware dot org>]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=35fd2b2bcf370837a03f077acf1222f0a7e9c4d1

commit 35fd2b2bcf370837a03f077acf1222f0a7e9c4d1
Author: Jim Wilson <jimw@sifive.com>
Date:   Tue Jan 9 16:40:06 2018 -0800

    RISC-V: Disassemble x0 based addresses as 0.
    
    	gas/
    	* testsuite/gas/riscv/auipc-x0.d: New.
    	* testsuite/gas/riscv/auipc-x0.s: New.
    
    	opcodes/
    	* riscv-dis.c (maybe_print_address): If base_reg is zero,
    	then the hi_addr value is zero.

Diff:
---
 gas/ChangeLog                      |  5 +++++
 gas/testsuite/gas/riscv/auipc-x0.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/auipc-x0.s |  4 ++++
 opcodes/ChangeLog                  |  5 +++++
 opcodes/riscv-dis.c                |  2 +-
 5 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 287656b..4ab6fa3 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-09  Jim Wilson  <jimw@sifive.com>
+
+	* testsuite/gas/riscv/auipc-x0.d: New.
+	* testsuite/gas/riscv/auipc-x0.s: New.
+
 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 
 	* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
diff --git a/gas/testsuite/gas/riscv/auipc-x0.d b/gas/testsuite/gas/riscv/auipc-x0.d
new file mode 100644
index 0000000..bcf95af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/auipc-x0.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+#...
+[ 	]+40:[ 	]+00000017[ 	]+auipc[ 	]+zero,0x0
+[ 	]+44:[ 	]+00002003[ 	]+lw[ 	]+zero,0\(zero\) # 0 .*
diff --git a/gas/testsuite/gas/riscv/auipc-x0.s b/gas/testsuite/gas/riscv/auipc-x0.s
new file mode 100644
index 0000000..f7b394c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/auipc-x0.s
@@ -0,0 +1,4 @@
+target:
+	.skip 64
+	auipc x0, 0
+	lw x0, 0(x0)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 96bc41c..24d1101 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-09  Jim Wilson  <jimw@sifive.com>
+
+	* riscv-dis.c (maybe_print_address): If base_reg is zero,
+	then the hi_addr value is zero.
+
 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 
 	* arm-dis.c (arm_opcodes): Add csdb.
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index cc427b4..cc642d4 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -101,7 +101,7 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
 {
   if (pd->hi_addr[base_reg] != (bfd_vma)-1)
     {
-      pd->print_addr = pd->hi_addr[base_reg] + offset;
+      pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
       pd->hi_addr[base_reg] = -1;
     }
   else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)