[binutils-gdb] x86/Intel: don't mistake riz/eiz as base register

[Jan Beulich <jbeulich at sourceware dot org>]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=1187cf29b1f77b4d806c3bbe1fcd86fc7387eeb9

commit 1187cf29b1f77b4d806c3bbe1fcd86fc7387eeb9
Author: Jan Beulich <jbeulich@novell.com>
Date:   Mon Nov 13 12:20:30 2017 +0100

    x86/Intel: don't mistake riz/eiz as base register
    
    Just like we make rsp/esp a base register even if it comes second, make
    riz/eiz an index register even if it comes first.

Diff:
---
 gas/ChangeLog                  | 8 ++++++++
 gas/config/tc-i386-intel.c     | 4 +++-
 gas/testsuite/gas/i386/intel.d | 3 +++
 gas/testsuite/gas/i386/intel.s | 6 ++++++
 4 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2c63aaa..d18c381 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,13 @@
 2017-11-13  Jan Beulich  <jbeulich@suse.com>
 
+	* config/tc-i386-intel.c (i386_intel_simplify_register): Also
+	recognize RegRiz/RegEiz as index-only registers.
+	* testsuite/gas/i386/intel.s: Add tests exercising base/index
+	swapping.
+	* testsuite/gas/i386/intel.d: Adjust expectations.
+
+2017-11-13  Jan Beulich  <jbeulich@suse.com>
+
 	* config/tc-i386.c (i386_index_check): Break out ...
 	(i386_addressing_mode): ... this new function.
 	* config/tc-i386-intel.c (i386_intel_operand): Do base/index
diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c
index 36ae818..b8874e4 100644
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -288,7 +288,9 @@ i386_intel_simplify_register (expressionS *e)
   else if (!intel_state.index
 	   && (i386_regtab[reg_num].reg_type.bitfield.regxmm
 	       || i386_regtab[reg_num].reg_type.bitfield.regymm
-	       || i386_regtab[reg_num].reg_type.bitfield.regzmm))
+	       || i386_regtab[reg_num].reg_type.bitfield.regzmm
+	       || i386_regtab[reg_num].reg_num == RegRiz
+	       || i386_regtab[reg_num].reg_num == RegEiz))
     intel_state.index = i386_regtab + reg_num;
   else if (!intel_state.base && !intel_state.in_scale)
     intel_state.base = i386_regtab + reg_num;
diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d
index d10b4f0..836acd60 100644
--- a/gas/testsuite/gas/i386/intel.d
+++ b/gas/testsuite/gas/i386/intel.d
@@ -698,6 +698,9 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 4b 90 90 90 90 90 	cmovnp -0x6f6f6f70\(%eax\),%edx
 [ 	]*[a-f0-9]+:	66 0f 4a 90 90 90 90 90 	cmovp  -0x6f6f6f70\(%eax\),%dx
 [ 	]*[a-f0-9]+:	66 0f 4b 90 90 90 90 90 	cmovnp -0x6f6f6f70\(%eax\),%dx
+[ 	]*[a-f0-9]+:	8b 04 04             	mov    \(%esp,%eax(,1)?\),%eax
+[ 	]*[a-f0-9]+:	8b 04 20             	mov    \(%eax(,%eiz)?(,1)?\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 69 92 04 08    	vgatherdps %xmm2,\(%eax,%xmm1(,1)?\),%xmm0
 [ 	]*[a-f0-9]+:	24 2f                	and    \$0x2f,%al
 [ 	]*[a-f0-9]+:	0f                   	\.byte 0xf
 [a-f0-9]+ <barn>:
diff --git a/gas/testsuite/gas/i386/intel.s b/gas/testsuite/gas/i386/intel.s
index 045d6ae..813daaa 100644
--- a/gas/testsuite/gas/i386/intel.s
+++ b/gas/testsuite/gas/i386/intel.s
@@ -699,6 +699,12 @@ fidivr  dword ptr [ebx]
  cmovpe  dx, 0x90909090[eax]
  cmovpo dx, 0x90909090[eax]
 
+ # Check base/index swapping
+	.allow_index_reg
+ mov    eax, [eax+esp]
+ mov    eax, [eiz+eax]
+ vgatherdps xmm0, [xmm1+eax], xmm2
+
 	# Test that disassembly of a partial instruction shows the partial byte:
 	# https://www.sourceware.org/ml/binutils/2015-08/msg00226.html
 	.byte 0x24