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[binutils-gdb] Add assembler and disassembler support for the new Armv8.4-a registers for AArch64.
- From: Tamar Christina <tnfchris at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 9 Nov 2017 16:29:24 -0000
- Subject: [binutils-gdb] Add assembler and disassembler support for the new Armv8.4-a registers for AArch64.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=793a194839bc8add71fdc7429c58b10f0667a6f6
commit 793a194839bc8add71fdc7429c58b10f0667a6f6
Author: Tamar Christina <tamar.christina@arm.com>
Date: Thu Nov 9 15:48:43 2017 +0000
Add assembler and disassembler support for the new Armv8.4-a registers for AArch64.
Some of these instructions have been back-ported as optional extensions to
Armv8.2-a and higher, but others are only available for Armv8.4-a.
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
sder32_el2, vncr_el2.
(aarch64_sys_reg_supported_p): Likewise.
(aarch64_pstatefields): Add dit register.
(aarch64_pstatefield_supported_p): Likewise.
(aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
gas/testsuite
* gas/aarch64/armv8_4-a-registers-illegal.d: New.
* gas/aarch64/armv8_4-a-registers-illegal.l: New.
* gas/aarch64/armv8_4-a-registers-illegal.s: New.
* gas/aarch64/armv8_4-a-registers.d: New.
* gas/aarch64/armv8_4-a-registers.s: New.
Diff:
---
gas/ChangeLog | 8 +
.../gas/aarch64/armv8_4-a-registers-illegal.d | 3 +
.../gas/aarch64/armv8_4-a-registers-illegal.l | 178 +++++++++++++++++++
.../gas/aarch64/armv8_4-a-registers-illegal.s | 80 +++++++++
gas/testsuite/gas/aarch64/armv8_4-a-registers.d | 192 +++++++++++++++++++++
gas/testsuite/gas/aarch64/armv8_4-a-registers.s | 94 ++++++++++
opcodes/ChangeLog | 17 ++
opcodes/aarch64-opc.c | 148 +++++++++++++++-
8 files changed, 719 insertions(+), 1 deletion(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 441dc22..3d032f2 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.d: New.
+ * gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.l: New.
+ * gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.s: New.
+ * gas/testsuite/gas/aarch64/armv8_4-a-registers.d: New.
+ * gas/testsuite/gas/aarch64/armv8_4-a-registers.s: New.
+
2017-11-09 Tamar Christina <tamar.christina@arm.com>
* config/tc-aarch64.c (process_omitted_operand):
diff --git a/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.d b/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.d
new file mode 100644
index 0000000..098552b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.d
@@ -0,0 +1,3 @@
+#as: -march=armv8.4-a+crypto+sm4+sha3
+#source: armv8_4-a-registers-illegal.s
+#error-output: armv8_4-a-registers-illegal.l
diff --git a/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.l b/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.l
new file mode 100644
index 0000000..41373f7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.l
@@ -0,0 +1,178 @@
+[^:]+: Assembler messages:
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,VSTTBR_EL2'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, vsttbr_el2
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,VSTCR_EL2'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, vstcr_el2
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTP_TVAL_EL0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cntp_tval_el0
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTP_CTL_EL0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cntp_ctl_el0
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTP_CVAL_EL0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cntp_cval_el0
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTV_TVAL_EL0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cntv_tval_el0
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTV_CTL_EL0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cntv_ctl_el0
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTV_CVAL_EL0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cntv_cval_el0
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTHVS_TVAL_EL2'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cnthvs_tval_el2
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTHVS_CVAL_EL2'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cnthvs_cval_el2
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTHVS_CTL_EL2'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cnthvs_ctl_el2
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTHPS_TVAL_EL2'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cnthps_tval_el2
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTHPS_CVAL_EL2'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cnthps_cval_el2
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,CNTHPS_CTL_EL2'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, cnthps_ctl_el2
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,SDER32_EL2'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, sder32_el2
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,VNCR_EL2'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, vncr_el2
+[^:]+:[0-9]+: Error: operand mismatch -- `msr DIT,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: msr dit, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `mrs W0,DIT'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: mrs x0, dit
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi VAE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi vae1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi ASIDE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi aside1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi VAAE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi vaae1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi VALE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi vale1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi VAALE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi vaale1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi IPAS2E1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi ipas2e1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi IPAS2LE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi ipas2le1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi VAE2OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi vae2os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi VALE2OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi vale2os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi VAE3OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi vae3os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi VALE3OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi vale3os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAE1,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvae1, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAAE1,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvaae1, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVALE1,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvale1, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAALE1,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvaale1, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAE1IS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvae1is, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAAE1IS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvaae1is, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVALE1IS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvale1is, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAALE1IS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvaale1is, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvae1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAAE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvaae1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVALE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvale1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAALE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvaale1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RIPAS2E1IS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi ripas2e1is, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RIPAS2LE1IS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi ripas2le1is, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RIPAS2E1,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi ripas2e1, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RIPAS2LE1,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi ripas2le1, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RIPAS2E1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi ripas2e1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RIPAS2LE1OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi ripas2le1os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAE2,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvae2, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVALE2,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvale2, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAE2IS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvae2is, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVALE2IS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvale2is, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAE2OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvae2os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVALE2OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvale2os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAE3,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvae3, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVALE3,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvale3, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAE3IS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvae3is, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVALE3IS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvale3is, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVAE3OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvae3os, x0
+[^:]+:[0-9]+: Error: operand mismatch -- `tlbi RVALE3OS,W0'
+[^:]+:[0-9]+: Info: did you mean this\?
+[^:]+:[0-9]+: Info: tlbi rvale3os, x0
diff --git a/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.s b/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.s
new file mode 100644
index 0000000..d31fff2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.s
@@ -0,0 +1,80 @@
+# Secure second stage
+MRS W0, VSTTBR_EL2
+MRS W0, VSTCR_EL2
+
+# Timer changes
+MRS W0, CNTP_TVAL_EL0
+MRS W0, CNTP_CTL_EL0
+MRS W0, CNTP_CVAL_EL0
+MRS W0, CNTV_TVAL_EL0
+MRS W0, CNTV_CTL_EL0
+MRS W0, CNTV_CVAL_EL0
+
+MRS W0, CNTHVS_TVAL_EL2
+MRS W0, CNTHVS_CVAL_EL2
+MRS W0, CNTHVS_CTL_EL2
+MRS W0, CNTHPS_TVAL_EL2
+MRS W0, CNTHPS_CVAL_EL2
+MRS W0, CNTHPS_CTL_EL2
+
+# Debug state
+MRS W0, SDER32_EL2
+
+# Nested Virtualization
+MRS W0, VNCR_EL2
+
+# PSTATE
+MSR DIT, #01
+MSR DIT, W0
+MRS W0, DIT
+
+# TLB Maintenance instructions
+TLBI VMALLE1OS
+TLBI VAE1OS, W0
+TLBI ASIDE1OS, W0
+TLBI VAAE1OS, W0
+TLBI VALE1OS, W0
+TLBI VAALE1OS, W0
+TLBI IPAS2E1OS, W0
+TLBI IPAS2LE1OS, W0
+TLBI VAE2OS, W0
+TLBI VALE2OS, W0
+TLBI VMALLS12E1OS
+TLBI VAE3OS, W0
+TLBI VALE3OS, W0
+TLBI ALLE2OS
+TLBI ALLE1OS
+TLBI ALLE3OS
+
+# TLB Range Maintenance Instructions
+TLBI RVAE1, W0
+TLBI RVAAE1, W0
+TLBI RVALE1, W0
+TLBI RVAALE1, W0
+TLBI RVAE1IS, W0
+TLBI RVAAE1IS, W0
+TLBI RVALE1IS, W0
+TLBI RVAALE1IS, W0
+TLBI RVAE1OS, W0
+TLBI RVAAE1OS, W0
+TLBI RVALE1OS, W0
+TLBI RVAALE1OS, W0
+TLBI RIPAS2E1IS, W0
+TLBI RIPAS2LE1IS, W0
+TLBI RIPAS2E1, W0
+TLBI RIPAS2LE1, W0
+TLBI RIPAS2E1OS, W0
+TLBI RIPAS2LE1OS, W0
+TLBI RVAE2, W0
+TLBI RVALE2, W0
+TLBI RVAE2IS, W0
+TLBI RVALE2IS, W0
+TLBI RVAE2OS, W0
+TLBI RVALE2OS, W0
+TLBI RVAE3, W0
+TLBI RVALE3, W0
+TLBI RVAE3IS, W0
+TLBI RVALE3IS, W0
+TLBI RVAE3OS, W0
+TLBI RVALE3OS, W0
+
diff --git a/gas/testsuite/gas/aarch64/armv8_4-a-registers.d b/gas/testsuite/gas/aarch64/armv8_4-a-registers.d
new file mode 100644
index 0000000..f643c89
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_4-a-registers.d
@@ -0,0 +1,192 @@
+#as: -march=armv8.4-a
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+:\s+d53c2603 mrs x3, vsttbr_el2
+[^:]+:\s+d53c260b mrs x11, vsttbr_el2
+[^:]+:\s+d53c260f mrs x15, vsttbr_el2
+[^:]+:\s+d53c2643 mrs x3, vstcr_el2
+[^:]+:\s+d53c264b mrs x11, vstcr_el2
+[^:]+:\s+d53c264f mrs x15, vstcr_el2
+[^:]+:\s+d53be203 mrs x3, cntp_tval_el0
+[^:]+:\s+d53be20b mrs x11, cntp_tval_el0
+[^:]+:\s+d53be20f mrs x15, cntp_tval_el0
+[^:]+:\s+d53be223 mrs x3, cntp_ctl_el0
+[^:]+:\s+d53be22b mrs x11, cntp_ctl_el0
+[^:]+:\s+d53be22f mrs x15, cntp_ctl_el0
+[^:]+:\s+d53be243 mrs x3, cntp_cval_el0
+[^:]+:\s+d53be24b mrs x11, cntp_cval_el0
+[^:]+:\s+d53be24f mrs x15, cntp_cval_el0
+[^:]+:\s+d53be303 mrs x3, cntv_tval_el0
+[^:]+:\s+d53be30b mrs x11, cntv_tval_el0
+[^:]+:\s+d53be30f mrs x15, cntv_tval_el0
+[^:]+:\s+d53be323 mrs x3, cntv_ctl_el0
+[^:]+:\s+d53be32b mrs x11, cntv_ctl_el0
+[^:]+:\s+d53be32f mrs x15, cntv_ctl_el0
+[^:]+:\s+d53be343 mrs x3, cntv_cval_el0
+[^:]+:\s+d53be34b mrs x11, cntv_cval_el0
+[^:]+:\s+d53be34f mrs x15, cntv_cval_el0
+[^:]+:\s+d53ce403 mrs x3, cnthvs_tval_el2
+[^:]+:\s+d53ce40b mrs x11, cnthvs_tval_el2
+[^:]+:\s+d53ce40f mrs x15, cnthvs_tval_el2
+[^:]+:\s+d53ce443 mrs x3, cnthvs_cval_el2
+[^:]+:\s+d53ce44b mrs x11, cnthvs_cval_el2
+[^:]+:\s+d53ce44f mrs x15, cnthvs_cval_el2
+[^:]+:\s+d53ce423 mrs x3, cnthvs_ctl_el2
+[^:]+:\s+d53ce42b mrs x11, cnthvs_ctl_el2
+[^:]+:\s+d53ce42f mrs x15, cnthvs_ctl_el2
+[^:]+:\s+d53ce503 mrs x3, cnthps_tval_el2
+[^:]+:\s+d53ce50b mrs x11, cnthps_tval_el2
+[^:]+:\s+d53ce50f mrs x15, cnthps_tval_el2
+[^:]+:\s+d53ce543 mrs x3, cnthps_cval_el2
+[^:]+:\s+d53ce54b mrs x11, cnthps_cval_el2
+[^:]+:\s+d53ce54f mrs x15, cnthps_cval_el2
+[^:]+:\s+d53ce523 mrs x3, cnthps_ctl_el2
+[^:]+:\s+d53ce52b mrs x11, cnthps_ctl_el2
+[^:]+:\s+d53ce52f mrs x15, cnthps_ctl_el2
+[^:]+:\s+d53c1323 mrs x3, sder32_el2
+[^:]+:\s+d53c132b mrs x11, sder32_el2
+[^:]+:\s+d53c132f mrs x15, sder32_el2
+[^:]+:\s+d53c2203 mrs x3, vncr_el2
+[^:]+:\s+d53c220b mrs x11, vncr_el2
+[^:]+:\s+d53c220f mrs x15, vncr_el2
+[^:]+:\s+d503415f msr dit, #0x1
+[^:]+:\s+d503405f msr dit, #0x0
+[^:]+:\s+d51b42a3 msr dit, x3
+[^:]+:\s+d51b42ab msr dit, x11
+[^:]+:\s+d51b42af msr dit, x15
+[^:]+:\s+d53b42a3 mrs x3, dit
+[^:]+:\s+d53b42ab mrs x11, dit
+[^:]+:\s+d53b42af mrs x15, dit
+[^:]+:\s+d508811f tlbi vmalle1os
+[^:]+:\s+d50c811f tlbi alle2os
+[^:]+:\s+d50c819f tlbi alle1os
+[^:]+:\s+d50e811f tlbi alle3os
+[^:]+:\s+d50c81df tlbi vmalls12e1os
+[^:]+:\s+d5088123 tlbi vae1os, x3
+[^:]+:\s+d508812b tlbi vae1os, x11
+[^:]+:\s+d508812f tlbi vae1os, x15
+[^:]+:\s+d5088143 tlbi aside1os, x3
+[^:]+:\s+d508814b tlbi aside1os, x11
+[^:]+:\s+d508814f tlbi aside1os, x15
+[^:]+:\s+d5088163 tlbi vaae1os, x3
+[^:]+:\s+d508816b tlbi vaae1os, x11
+[^:]+:\s+d508816f tlbi vaae1os, x15
+[^:]+:\s+d50881a3 tlbi vale1os, x3
+[^:]+:\s+d50881ab tlbi vale1os, x11
+[^:]+:\s+d50881af tlbi vale1os, x15
+[^:]+:\s+d50881e3 tlbi vaale1os, x3
+[^:]+:\s+d50881eb tlbi vaale1os, x11
+[^:]+:\s+d50881ef tlbi vaale1os, x15
+[^:]+:\s+d50c8403 tlbi ipas2e1os, x3
+[^:]+:\s+d50c840b tlbi ipas2e1os, x11
+[^:]+:\s+d50c840f tlbi ipas2e1os, x15
+[^:]+:\s+d50c8483 tlbi ipas2le1os, x3
+[^:]+:\s+d50c848b tlbi ipas2le1os, x11
+[^:]+:\s+d50c848f tlbi ipas2le1os, x15
+[^:]+:\s+d50c8123 tlbi vae2os, x3
+[^:]+:\s+d50c812b tlbi vae2os, x11
+[^:]+:\s+d50c812f tlbi vae2os, x15
+[^:]+:\s+d50c81a3 tlbi vale2os, x3
+[^:]+:\s+d50c81ab tlbi vale2os, x11
+[^:]+:\s+d50c81af tlbi vale2os, x15
+[^:]+:\s+d50e8123 tlbi vae3os, x3
+[^:]+:\s+d50e812b tlbi vae3os, x11
+[^:]+:\s+d50e812f tlbi vae3os, x15
+[^:]+:\s+d50e81a3 tlbi vale3os, x3
+[^:]+:\s+d50e81ab tlbi vale3os, x11
+[^:]+:\s+d50e81af tlbi vale3os, x15
+[^:]+:\s+d5088623 tlbi rvae1, x3
+[^:]+:\s+d508862b tlbi rvae1, x11
+[^:]+:\s+d508862f tlbi rvae1, x15
+[^:]+:\s+d5088663 tlbi rvaae1, x3
+[^:]+:\s+d508866b tlbi rvaae1, x11
+[^:]+:\s+d508866f tlbi rvaae1, x15
+[^:]+:\s+d50886a3 tlbi rvale1, x3
+[^:]+:\s+d50886ab tlbi rvale1, x11
+[^:]+:\s+d50886af tlbi rvale1, x15
+[^:]+:\s+d50886e3 tlbi rvaale1, x3
+[^:]+:\s+d50886eb tlbi rvaale1, x11
+[^:]+:\s+d50886ef tlbi rvaale1, x15
+[^:]+:\s+d5088223 tlbi rvae1is, x3
+[^:]+:\s+d508822b tlbi rvae1is, x11
+[^:]+:\s+d508822f tlbi rvae1is, x15
+[^:]+:\s+d5088263 tlbi rvaae1is, x3
+[^:]+:\s+d508826b tlbi rvaae1is, x11
+[^:]+:\s+d508826f tlbi rvaae1is, x15
+[^:]+:\s+d50882a3 tlbi rvale1is, x3
+[^:]+:\s+d50882ab tlbi rvale1is, x11
+[^:]+:\s+d50882af tlbi rvale1is, x15
+[^:]+:\s+d50882e3 tlbi rvaale1is, x3
+[^:]+:\s+d50882eb tlbi rvaale1is, x11
+[^:]+:\s+d50882ef tlbi rvaale1is, x15
+[^:]+:\s+d5088523 tlbi rvae1os, x3
+[^:]+:\s+d508852b tlbi rvae1os, x11
+[^:]+:\s+d508852f tlbi rvae1os, x15
+[^:]+:\s+d5088563 tlbi rvaae1os, x3
+[^:]+:\s+d508856b tlbi rvaae1os, x11
+[^:]+:\s+d508856f tlbi rvaae1os, x15
+[^:]+:\s+d50885a3 tlbi rvale1os, x3
+[^:]+:\s+d50885ab tlbi rvale1os, x11
+[^:]+:\s+d50885af tlbi rvale1os, x15
+[^:]+:\s+d50885e3 tlbi rvaale1os, x3
+[^:]+:\s+d50885eb tlbi rvaale1os, x11
+[^:]+:\s+d50885ef tlbi rvaale1os, x15
+[^:]+:\s+d50c8043 tlbi ripas2e1is, x3
+[^:]+:\s+d50c804b tlbi ripas2e1is, x11
+[^:]+:\s+d50c804f tlbi ripas2e1is, x15
+[^:]+:\s+d50c80c3 tlbi ripas2le1is, x3
+[^:]+:\s+d50c80cb tlbi ripas2le1is, x11
+[^:]+:\s+d50c80cf tlbi ripas2le1is, x15
+[^:]+:\s+d50c8443 tlbi ripas2e1, x3
+[^:]+:\s+d50c844b tlbi ripas2e1, x11
+[^:]+:\s+d50c844f tlbi ripas2e1, x15
+[^:]+:\s+d50c84c3 tlbi ripas2le1, x3
+[^:]+:\s+d50c84cb tlbi ripas2le1, x11
+[^:]+:\s+d50c84cf tlbi ripas2le1, x15
+[^:]+:\s+d50c8463 tlbi ripas2e1os, x3
+[^:]+:\s+d50c846b tlbi ripas2e1os, x11
+[^:]+:\s+d50c846f tlbi ripas2e1os, x15
+[^:]+:\s+d50c84e3 tlbi ripas2le1os, x3
+[^:]+:\s+d50c84eb tlbi ripas2le1os, x11
+[^:]+:\s+d50c84ef tlbi ripas2le1os, x15
+[^:]+:\s+d50c8623 tlbi rvae2, x3
+[^:]+:\s+d50c862b tlbi rvae2, x11
+[^:]+:\s+d50c862f tlbi rvae2, x15
+[^:]+:\s+d50c86a3 tlbi rvale2, x3
+[^:]+:\s+d50c86ab tlbi rvale2, x11
+[^:]+:\s+d50c86af tlbi rvale2, x15
+[^:]+:\s+d50c8223 tlbi rvae2is, x3
+[^:]+:\s+d50c822b tlbi rvae2is, x11
+[^:]+:\s+d50c822f tlbi rvae2is, x15
+[^:]+:\s+d50c82a3 tlbi rvale2is, x3
+[^:]+:\s+d50c82ab tlbi rvale2is, x11
+[^:]+:\s+d50c82af tlbi rvale2is, x15
+[^:]+:\s+d50c8523 tlbi rvae2os, x3
+[^:]+:\s+d50c852b tlbi rvae2os, x11
+[^:]+:\s+d50c852f tlbi rvae2os, x15
+[^:]+:\s+d50c85a3 tlbi rvale2os, x3
+[^:]+:\s+d50c85ab tlbi rvale2os, x11
+[^:]+:\s+d50c85af tlbi rvale2os, x15
+[^:]+:\s+d50e8623 tlbi rvae3, x3
+[^:]+:\s+d50e862b tlbi rvae3, x11
+[^:]+:\s+d50e862f tlbi rvae3, x15
+[^:]+:\s+d50e86a3 tlbi rvale3, x3
+[^:]+:\s+d50e86ab tlbi rvale3, x11
+[^:]+:\s+d50e86af tlbi rvale3, x15
+[^:]+:\s+d50e8223 tlbi rvae3is, x3
+[^:]+:\s+d50e822b tlbi rvae3is, x11
+[^:]+:\s+d50e822f tlbi rvae3is, x15
+[^:]+:\s+d50e82a3 tlbi rvale3is, x3
+[^:]+:\s+d50e82ab tlbi rvale3is, x11
+[^:]+:\s+d50e82af tlbi rvale3is, x15
+[^:]+:\s+d50e8523 tlbi rvae3os, x3
+[^:]+:\s+d50e852b tlbi rvae3os, x11
+[^:]+:\s+d50e852f tlbi rvae3os, x15
+[^:]+:\s+d50e85a3 tlbi rvale3os, x3
+[^:]+:\s+d50e85ab tlbi rvale3os, x11
+[^:]+:\s+d50e85af tlbi rvale3os, x15
diff --git a/gas/testsuite/gas/aarch64/armv8_4-a-registers.s b/gas/testsuite/gas/aarch64/armv8_4-a-registers.s
new file mode 100644
index 0000000..b909b82
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_4-a-registers.s
@@ -0,0 +1,94 @@
+ .macro gen_mrs reg
+ .irp m, 3, 11, 15
+ MRS X\m, \reg
+ .endr
+ .endm
+
+ .macro gen_tlbi reg
+ .irp m, 3, 11, 15
+ TLBI \reg, X\m
+ .endr
+ .endm
+func:
+ # Secure second stage
+ gen_mrs VSTTBR_EL2
+ gen_mrs VSTCR_EL2
+
+ # Timer changes
+ gen_mrs CNTP_TVAL_EL0
+ gen_mrs CNTP_CTL_EL0
+ gen_mrs CNTP_CVAL_EL0
+ gen_mrs CNTV_TVAL_EL0
+ gen_mrs CNTV_CTL_EL0
+ gen_mrs CNTV_CVAL_EL0
+
+ gen_mrs CNTHVS_TVAL_EL2
+ gen_mrs CNTHVS_CVAL_EL2
+ gen_mrs CNTHVS_CTL_EL2
+ gen_mrs CNTHPS_TVAL_EL2
+ gen_mrs CNTHPS_CVAL_EL2
+ gen_mrs CNTHPS_CTL_EL2
+
+ # Debug state
+ gen_mrs SDER32_EL2
+
+ # Nested Virtualization
+ gen_mrs VNCR_EL2
+
+ # PSTATE
+ MSR DIT, #01
+ MSR DIT, #00
+ MSR DIT, X3
+ MSR DIT, X11
+ MSR DIT, X15
+ gen_mrs DIT
+
+ # TLB Maintenance instructions
+ TLBI VMALLE1OS
+ TLBI ALLE2OS
+ TLBI ALLE1OS
+ TLBI ALLE3OS
+ TLBI VMALLS12E1OS
+ gen_tlbi VAE1OS
+ gen_tlbi ASIDE1OS
+ gen_tlbi VAAE1OS
+ gen_tlbi VALE1OS
+ gen_tlbi VAALE1OS
+ gen_tlbi IPAS2E1OS
+ gen_tlbi IPAS2LE1OS
+ gen_tlbi VAE2OS
+ gen_tlbi VALE2OS
+ gen_tlbi VAE3OS
+ gen_tlbi VALE3OS
+
+ # TLB Range Maintenance Instructions
+ gen_tlbi RVAE1
+ gen_tlbi RVAAE1
+ gen_tlbi RVALE1
+ gen_tlbi RVAALE1
+ gen_tlbi RVAE1IS
+ gen_tlbi RVAAE1IS
+ gen_tlbi RVALE1IS
+ gen_tlbi RVAALE1IS
+ gen_tlbi RVAE1OS
+ gen_tlbi RVAAE1OS
+ gen_tlbi RVALE1OS
+ gen_tlbi RVAALE1OS
+ gen_tlbi RIPAS2E1IS
+ gen_tlbi RIPAS2LE1IS
+ gen_tlbi RIPAS2E1
+ gen_tlbi RIPAS2LE1
+ gen_tlbi RIPAS2E1OS
+ gen_tlbi RIPAS2LE1OS
+ gen_tlbi RVAE2
+ gen_tlbi RVALE2
+ gen_tlbi RVAE2IS
+ gen_tlbi RVALE2IS
+ gen_tlbi RVAE2OS
+ gen_tlbi RVALE2OS
+ gen_tlbi RVAE3
+ gen_tlbi RVALE3
+ gen_tlbi RVAE3IS
+ gen_tlbi RVALE3IS
+ gen_tlbi RVAE3OS
+ gen_tlbi RVALE3OS
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4056d88..809cad3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,22 @@
2017-11-09 Tamar Christina <tamar.christina@arm.com>
+ * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
+ dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
+ cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
+ sder32_el2, vncr_el2.
+ (aarch64_sys_reg_supported_p): Likewise.
+ (aarch64_pstatefields): Add dit register.
+ (aarch64_pstatefield_supported_p): Likewise.
+ (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
+ vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
+ vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
+ rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
+ rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
+ ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
+ rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
+
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
* aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
(QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
(QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4461906..96ca085 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2465,7 +2465,8 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
MSR PAN, #uimm4
The immediate must be #0 or #1. */
if ((opnd->pstatefield == 0x03 /* UAO. */
- || opnd->pstatefield == 0x04) /* PAN. */
+ || opnd->pstatefield == 0x04 /* PAN. */
+ || opnd->pstatefield == 0x1a) /* DIT. */
&& opnds[1].imm.value > 1)
{
set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
@@ -4031,6 +4032,18 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
{ "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
{ "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
+
+ { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
+ { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
+ { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
+ { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
+ { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
+ { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
+ { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
+ { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
+ { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
+ { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
+ { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
{ 0, CPENC(0,0,0,0,0), 0 },
};
@@ -4168,9 +4181,87 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
return FALSE;
+ /* ARMv8.4 features. */
+
+ /* PSTATE.DIT. */
+ if (reg->value == CPEN_ (3, C2, 5)
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
+ return FALSE;
+
+ /* Virtualization extensions. */
+ if ((reg->value == CPENC(3, 4, C2, C6, 2)
+ || reg->value == CPENC(3, 4, C2, C6, 0)
+ || reg->value == CPENC(3, 4, C14, C4, 0)
+ || reg->value == CPENC(3, 4, C14, C4, 2)
+ || reg->value == CPENC(3, 4, C14, C4, 1)
+ || reg->value == CPENC(3, 4, C14, C5, 0)
+ || reg->value == CPENC(3, 4, C14, C5, 2)
+ || reg->value == CPENC(3, 4, C14, C5, 1)
+ || reg->value == CPENC(3, 4, C1, C3, 1)
+ || reg->value == CPENC(3, 4, C2, C2, 0))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
+ return FALSE;
+
+ /* ARMv8.4 TLB instructions. */
+ if ((reg->value == CPENS (0, C8, C1, 0)
+ || reg->value == CPENS (0, C8, C1, 1)
+ || reg->value == CPENS (0, C8, C1, 2)
+ || reg->value == CPENS (0, C8, C1, 3)
+ || reg->value == CPENS (0, C8, C1, 5)
+ || reg->value == CPENS (0, C8, C1, 7)
+ || reg->value == CPENS (4, C8, C4, 0)
+ || reg->value == CPENS (4, C8, C4, 4)
+ || reg->value == CPENS (4, C8, C1, 1)
+ || reg->value == CPENS (4, C8, C1, 5)
+ || reg->value == CPENS (4, C8, C1, 6)
+ || reg->value == CPENS (6, C8, C1, 1)
+ || reg->value == CPENS (6, C8, C1, 5)
+ || reg->value == CPENS (4, C8, C1, 0)
+ || reg->value == CPENS (4, C8, C1, 4)
+ || reg->value == CPENS (6, C8, C1, 0)
+ || reg->value == CPENS (0, C8, C6, 1)
+ || reg->value == CPENS (0, C8, C6, 3)
+ || reg->value == CPENS (0, C8, C6, 5)
+ || reg->value == CPENS (0, C8, C6, 7)
+ || reg->value == CPENS (0, C8, C2, 1)
+ || reg->value == CPENS (0, C8, C2, 3)
+ || reg->value == CPENS (0, C8, C2, 5)
+ || reg->value == CPENS (0, C8, C2, 7)
+ || reg->value == CPENS (0, C8, C5, 1)
+ || reg->value == CPENS (0, C8, C5, 3)
+ || reg->value == CPENS (0, C8, C5, 5)
+ || reg->value == CPENS (0, C8, C5, 7)
+ || reg->value == CPENS (4, C8, C0, 2)
+ || reg->value == CPENS (4, C8, C0, 6)
+ || reg->value == CPENS (4, C8, C4, 2)
+ || reg->value == CPENS (4, C8, C4, 6)
+ || reg->value == CPENS (4, C8, C4, 3)
+ || reg->value == CPENS (4, C8, C4, 7)
+ || reg->value == CPENS (4, C8, C6, 1)
+ || reg->value == CPENS (4, C8, C6, 5)
+ || reg->value == CPENS (4, C8, C2, 1)
+ || reg->value == CPENS (4, C8, C2, 5)
+ || reg->value == CPENS (4, C8, C5, 1)
+ || reg->value == CPENS (4, C8, C5, 5)
+ || reg->value == CPENS (6, C8, C6, 1)
+ || reg->value == CPENS (6, C8, C6, 5)
+ || reg->value == CPENS (6, C8, C2, 1)
+ || reg->value == CPENS (6, C8, C2, 5)
+ || reg->value == CPENS (6, C8, C5, 1)
+ || reg->value == CPENS (6, C8, C5, 5))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
+ return FALSE;
+
return TRUE;
}
+/* The CPENC below is fairly misleading, the fields
+ here are not in CPENC form. They are in op2op1 form. The fields are encoded
+ by ins_pstatefield, which just shifts the value by the width of the fields
+ in a loop. So if you CPENC them only the first value will be set, the rest
+ are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
+ value of 0b110000000001000000 (0x30040) while what you want is
+ 0b011010 (0x1a). */
const aarch64_sys_reg aarch64_pstatefields [] =
{
{ "spsel", 0x05, 0 },
@@ -4178,6 +4269,7 @@ const aarch64_sys_reg aarch64_pstatefields [] =
{ "daifclr", 0x1f, 0 },
{ "pan", 0x04, F_ARCHEXT },
{ "uao", 0x03, F_ARCHEXT },
+ { "dit", 0x1a, F_ARCHEXT },
{ 0, CPENC(0,0,0,0,0), 0 },
};
@@ -4198,6 +4290,11 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
+ /* DIT. Values are from aarch64_pstatefields. */
+ if (reg->value == 0x1a
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
+ return FALSE;
+
return TRUE;
}
@@ -4276,6 +4373,55 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
{ "vale2", CPENS (4, C8, C7, 5), F_HASXT },
{ "vale3", CPENS (6, C8, C7, 5), F_HASXT },
{ "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
+
+ { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
+ { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
+ { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
+ { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
+ { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
+ { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
+ { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
+ { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
+ { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
+ { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
+ { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
+ { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
+ { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
+ { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
+ { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
+ { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
+
+ { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
+ { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
+ { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
+ { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
+ { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
+ { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
+ { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
+ { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
+ { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
+ { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
+ { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
+ { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
+ { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
+ { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
+ { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
+ { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
+ { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
+ { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
+ { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
+ { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
+ { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
+ { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
+ { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
+ { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
+ { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
+ { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
+ { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
+ { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
+ { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
+ { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
+
{ 0, CPENS(0,0,0,0), 0 }
};