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[binutils-gdb] Adds command line support for Armv8.4-A, via the new command line option -march=armv8.4-a. Add supp
- From: Nick Clifton <nickc at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 8 Nov 2017 13:18:29 -0000
- Subject: [binutils-gdb] Adds command line support for Armv8.4-A, via the new command line option -march=armv8.4-a. Add supp
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=dec41383fff7116c9f66cdeca3105e968047a4e6
commit dec41383fff7116c9f66cdeca3105e968047a4e6
Author: Jiong Wang <jiong.wang@arm.com>
Date: Wed Nov 8 13:15:12 2017 +0000
Adds command line support for Armv8.4-A, via the new command line option -march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A
gas * config/tc-arm.c (arm_extensions):
(arm_archs): New entry for "armv8.4-a".
Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8.
(arm_ext_v8_2): New variable.
(enum arm_reg_type): New enumeration REG_TYPE_NSD.
(reg_expected_msgs): New entry for REG_TYPE_NSD.
(parse_typed_reg_or_scalar): Handle REG_TYPE_NSD.
(parse_scalar): Support REG_TYPE_VFS.
(enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC.
(parse_operands): Handle OP_RNSD and OP_RNSD_RNSC.
(NEON_SHAPE_DEF): New entries for DHH and DHS.
(neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding
for new FP16 instructions in ARMv8.2-A.
(do_neon_fmac_maybe_scalar_long): New function to encode new FP16
instructions in ARMv8.2-A.
(do_neon_vfmal): Wrapper function for vfmal.
(do_neon_vfmsl): Wrapper function for vfmsl.
(insns): New entries for vfmal and vfmsl.
* doc/c-arm.texi (-march): Document "armv8.4-a".
* testsuite/gas/arm/dotprod-mandatory.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16.s: New test source.
* testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source.
* testsuite/gas/arm/armv8_2-a-fp16.d: New test.
* testsuite/gas/arm/armv8_3-a-fp16.d: New test.
* testsuite/gas/arm/armv8_4-a-fp16.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file.
opcodes * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
FP16 instructions, including vfmal.f16 and vfmsl.f16.
include * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature.
(ARM_EXT2_V8_4A): New macro.
(ARM_AEXT2_V8_4A): Likewise.
(ARM_ARCH_V8_4A): Likewise.
Diff:
---
gas/ChangeLog | 32 +++
gas/config/tc-arm.c | 168 +++++++++++++-
gas/doc/c-arm.texi | 1 +
gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.d | 2 +
gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.l | 5 +
gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.s | 8 +
gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2.d | 249 +++++++++++++++++++++
gas/testsuite/gas/arm/armv8_2-a-fp16.d | 249 +++++++++++++++++++++
gas/testsuite/gas/arm/armv8_2-a-fp16.s | 46 ++++
gas/testsuite/gas/arm/armv8_3-a-fp16.d | 249 +++++++++++++++++++++
gas/testsuite/gas/arm/armv8_4-a-fp16.d | 249 +++++++++++++++++++++
gas/testsuite/gas/arm/dotprod-mandatory.d | 297 +++++++++++++++++++++++++
include/ChangeLog | 7 +
include/opcode/arm.h | 9 +-
opcodes/ChangeLog | 6 +
opcodes/arm-dis.c | 18 ++
16 files changed, 1590 insertions(+), 5 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c13f9b1..81fa312 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,35 @@
+2017-11-08 Jiong Wang <jiong.wang@arm.com>
+ Tamar Christina <tamar.christina@arm.com>
+
+ * config/tc-arm.c (arm_extensions):
+ (arm_archs): New entry for "armv8.4-a".
+ Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8.
+ (arm_ext_v8_2): New variable.
+ (enum arm_reg_type): New enumeration REG_TYPE_NSD.
+ (reg_expected_msgs): New entry for REG_TYPE_NSD.
+ (parse_typed_reg_or_scalar): Handle REG_TYPE_NSD.
+ (parse_scalar): Support REG_TYPE_VFS.
+ (enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC.
+ (parse_operands): Handle OP_RNSD and OP_RNSD_RNSC.
+ (NEON_SHAPE_DEF): New entries for DHH and DHS.
+ (neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding
+ for new FP16 instructions in ARMv8.2-A.
+ (do_neon_fmac_maybe_scalar_long): New function to encode new FP16
+ instructions in ARMv8.2-A.
+ (do_neon_vfmal): Wrapper function for vfmal.
+ (do_neon_vfmsl): Wrapper function for vfmsl.
+ (insns): New entries for vfmal and vfmsl.
+ * doc/c-arm.texi (-march): Document "armv8.4-a".
+ * testsuite/gas/arm/dotprod-mandatory.d: New test.
+ * testsuite/gas/arm/armv8_2-a-fp16.s: New test source.
+ * testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source.
+ * testsuite/gas/arm/armv8_2-a-fp16.d: New test.
+ * testsuite/gas/arm/armv8_3-a-fp16.d: New test.
+ * testsuite/gas/arm/armv8_4-a-fp16.d: New test.
+ * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test.
+ * testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test.
+ * testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file.
+
2017-11-08 Alan Modra <amodra@gmail.com>
* config/tc-xtensa.c (finish_vinsn): Properly pluralize error message.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 5d3dd4e..128ab38 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -235,6 +235,8 @@ static const arm_feature_set arm_ext_ras =
/* FP16 instructions. */
static const arm_feature_set arm_ext_fp16 =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
+static const arm_feature_set arm_ext_v8_2 =
+ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
static const arm_feature_set arm_ext_v8_3 =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
@@ -579,6 +581,7 @@ enum arm_reg_type
REG_TYPE_NQ,
REG_TYPE_VFSD,
REG_TYPE_NDQ,
+ REG_TYPE_NSD,
REG_TYPE_NSDQ,
REG_TYPE_VFC,
REG_TYPE_MVF,
@@ -619,6 +622,7 @@ const char * const reg_expected_msgs[] =
N_("Neon quad precision register expected"),
N_("VFP single or double precision register expected"),
N_("Neon double or quad precision register expected"),
+ N_("Neon single or double precision register expected"),
N_("VFP single, double or Neon quad precision register expected"),
N_("VFP system register expected"),
N_("Maverick MVF register expected"),
@@ -1506,6 +1510,8 @@ parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
|| (type == REG_TYPE_NSDQ
&& (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
|| reg->type == REG_TYPE_NQ))
+ || (type == REG_TYPE_NSD
+ && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
|| (type == REG_TYPE_MMXWC
&& (reg->type == REG_TYPE_MMXWCG)))
type = (enum arm_reg_type) reg->type;
@@ -1529,7 +1535,9 @@ parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
if (skip_past_char (&str, '[') == SUCCESS)
{
- if (type != REG_TYPE_VFD)
+ if (type != REG_TYPE_VFD
+ && !(type == REG_TYPE_VFS
+ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2)))
{
first_error (_("only D registers may be indexed"));
return FAIL;
@@ -1625,8 +1633,12 @@ parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
int reg;
char *str = *ccp;
struct neon_typed_alias atype;
+ enum arm_reg_type reg_type = REG_TYPE_VFD;
+
+ if (elsize == 4)
+ reg_type = REG_TYPE_VFS;
- reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
+ reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
return FAIL;
@@ -6486,6 +6498,7 @@ enum operand_parse_code
OP_RND, /* Neon double precision register (0..31) */
OP_RNQ, /* Neon quad precision register */
OP_RVSD, /* VFP single or double precision register */
+ OP_RNSD, /* Neon single or double precision register */
OP_RNDQ, /* Neon double or quad precision register */
OP_RNSDQ, /* Neon single, double or quad precision register */
OP_RNSC, /* Neon scalar D[X] */
@@ -6512,6 +6525,7 @@ enum operand_parse_code
OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
OP_RR_RNSC, /* ARM reg or Neon scalar. */
+ OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
@@ -6773,6 +6787,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
case OP_oRNQ:
case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
+ case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
case OP_oRNDQ:
case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
@@ -6830,6 +6845,18 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
}
break;
+ case OP_RNSD_RNSC:
+ {
+ po_scalar_or_goto (8, try_s_scalar);
+ break;
+ try_s_scalar:
+ po_scalar_or_goto (4, try_nsd);
+ break;
+ try_nsd:
+ po_reg_or_fail (REG_TYPE_NSD);
+ }
+ break;
+
case OP_RNDQ_RNSC:
{
po_scalar_or_goto (8, try_ndq);
@@ -13423,7 +13450,9 @@ NEON_ENC_TAB
X (2, (H, I), HALF), \
X (3, (H, H, H), HALF), \
X (3, (H, F, I), MIXED), \
- X (3, (F, H, I), MIXED)
+ X (3, (F, H, I), MIXED), \
+ X (3, (D, H, H), MIXED), \
+ X (3, (D, H, S), MIXED)
#define S2(A,B) NS_##A##B
#define S3(A,B,C) NS_##A##B##C
@@ -16133,6 +16162,133 @@ do_neon_mac_maybe_scalar_long (void)
neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
}
+/* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
+ internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
+
+static unsigned
+neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
+{
+ unsigned regno = NEON_SCALAR_REG (scalar);
+ unsigned elno = NEON_SCALAR_INDEX (scalar);
+
+ if (quad_p)
+ {
+ if (regno > 7 || elno > 3)
+ goto bad_scalar;
+
+ return ((regno & 0x7)
+ | ((elno & 0x1) << 3)
+ | (((elno >> 1) & 0x1) << 5));
+ }
+ else
+ {
+ if (regno > 15 || elno > 1)
+ goto bad_scalar;
+
+ return (((regno & 0x1) << 5)
+ | ((regno >> 1) & 0x7)
+ | ((elno & 0x1) << 3));
+ }
+
+bad_scalar:
+ first_error (_("scalar out of range for multiply instruction"));
+ return 0;
+}
+
+static void
+do_neon_fmac_maybe_scalar_long (int subtype)
+{
+ enum neon_shape rs;
+ int high8;
+ /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
+ field (bits[21:20]) has different meaning. For scalar index variant, it's
+ used to differentiate add and subtract, otherwise it's with fixed value
+ 0x2. */
+ int size = -1;
+
+ if (inst.cond != COND_ALWAYS)
+ as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
+ "behaviour is UNPREDICTABLE"));
+
+ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
+ _(BAD_FP16));
+
+ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
+ _(BAD_FPU));
+
+ /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
+ be a scalar index register. */
+ if (inst.operands[2].isscalar)
+ {
+ high8 = 0xfe000000;
+ if (subtype)
+ size = 16;
+ rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
+ }
+ else
+ {
+ high8 = 0xfc000000;
+ size = 32;
+ if (subtype)
+ inst.instruction |= (0x1 << 23);
+ rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
+ }
+
+ neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16);
+
+ /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
+ the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
+ so we simply pass -1 as size. */
+ unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
+ neon_three_same (quad_p, 0, size);
+
+ /* Undo neon_dp_fixup. Redo the high eight bits. */
+ inst.instruction &= 0x00ffffff;
+ inst.instruction |= high8;
+
+#define LOW1(R) ((R) & 0x1)
+#define HI4(R) (((R) >> 1) & 0xf)
+ /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
+ whether the instruction is in Q form and whether Vm is a scalar indexed
+ operand. */
+ if (inst.operands[2].isscalar)
+ {
+ unsigned rm
+ = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
+ inst.instruction &= 0xffffffd0;
+ inst.instruction |= rm;
+
+ if (!quad_p)
+ {
+ /* Redo Rn as well. */
+ inst.instruction &= 0xfff0ff7f;
+ inst.instruction |= HI4 (inst.operands[1].reg) << 16;
+ inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
+ }
+ }
+ else if (!quad_p)
+ {
+ /* Redo Rn and Rm. */
+ inst.instruction &= 0xfff0ff50;
+ inst.instruction |= HI4 (inst.operands[1].reg) << 16;
+ inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
+ inst.instruction |= HI4 (inst.operands[2].reg);
+ inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
+ }
+}
+
+static void
+do_neon_vfmal (void)
+{
+ return do_neon_fmac_maybe_scalar_long (0);
+}
+
+static void
+do_neon_vfmsl (void)
+{
+ return do_neon_fmac_maybe_scalar_long (1);
+}
+
static void
do_neon_dyadic_wide (void)
{
@@ -20644,6 +20800,10 @@ static const struct asm_opcode insns[] =
NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
+ /* New backported fma/fms instructions optional in v8.2. */
+ NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
+ NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
+
#undef THUMB_VARIANT
#define THUMB_VARIANT & fpu_neon_ext_v1
#undef ARM_VARIANT
@@ -26038,6 +26198,7 @@ static const struct arm_arch_option_table arm_archs[] =
ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP),
ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP),
ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP),
+ ARM_ARCH_OPT ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP),
ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
@@ -26736,6 +26897,7 @@ static const cpu_arch_ver_table cpu_arch_ver[] =
{16, ARM_ARCH_V8M_BASE},
{17, ARM_ARCH_V8M_MAIN},
{15, ARM_ARCH_V8R},
+ {16, ARM_ARCH_V8_4A},
{-1, ARM_ARCH_NONE}
};
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 9606de4..5e518c6 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -237,6 +237,7 @@ names are recognized:
@code{armv8.2-a},
@code{armv8.3-a},
@code{armv8-r},
+@code{armv8.4-a},
@code{iwmmxt}
@code{iwmmxt2}
and
diff --git a/gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.d b/gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.d
new file mode 100644
index 0000000..745ae05
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.2-a+fp16 -mfpu=neon-fp-armv8
+#error-output: armv8_2-a-fp16-illegal.l
diff --git a/gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.l b/gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.l
new file mode 100644
index 0000000..b407d6c
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.l
@@ -0,0 +1,5 @@
+[^:]*.s: Assembler messages:
+[^:]*:4: Error: scalar out of range for multiply instruction -- `vfmal.f16 d2,s0,s16\[1\]'
+[^:]*:5: Error: scalar out of range for multiply instruction -- `vfmsl.f16 q13,d1,d8\[3\]'
+[^:]*:7: Error: scalar out of range for multiply instruction -- `vfmal.f16 d16,s2,s15\[2\]'
+[^:]*:8: Error: scalar out of range for multiply instruction -- `vfmsl.f16 q13,d1,d7\[4\]'
diff --git a/gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.s b/gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.s
new file mode 100644
index 0000000..740dd5c
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a-fp16-illegal.s
@@ -0,0 +1,8 @@
+ .text
+func:
+ # Scalar base register out of bound
+ vfmal.f16 d2, s0, s16[1]
+ vfmsl.f16 q13, d1, d8[3]
+ # Scalar index out of bound
+ vfmal.f16 d16, s2, s15[2]
+ vfmsl.f16 q13, d1, d7[4]
diff --git a/gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2.d b/gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2.d
new file mode 100644
index 0000000..b03a8ae
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2.d
@@ -0,0 +1,249 @@
+#as: -march=armv8.2-a+fp16 -mfpu=neon-fp-armv8 -mthumb
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*: fc21 0810 vfmal.f16 d0, s2, s0
+.*: fe00 2810 vfmal.f16 d2, s0, s0\[0\]
+.*: fca1 0810 vfmsl.f16 d0, s2, s0
+.*: fe10 2818 vfmsl.f16 d2, s0, s0\[1\]
+.*: fc21 0814 vfmal.f16 d0, s2, s8
+.*: fe00 2814 vfmal.f16 d2, s0, s8\[0\]
+.*: fca1 0814 vfmsl.f16 d0, s2, s8
+.*: fe10 281c vfmsl.f16 d2, s0, s8\[1\]
+.*: fc21 0837 vfmal.f16 d0, s2, s15
+.*: fe00 2837 vfmal.f16 d2, s0, s15\[0\]
+.*: fca1 0837 vfmsl.f16 d0, s2, s15
+.*: fe10 283f vfmsl.f16 d2, s0, s15\[1\]
+.*: fc27 0890 vfmal.f16 d0, s15, s0
+.*: fe00 f810 vfmal.f16 d15, s0, s0\[0\]
+.*: fca7 0890 vfmsl.f16 d0, s15, s0
+.*: fe10 f818 vfmsl.f16 d15, s0, s0\[1\]
+.*: fc27 0894 vfmal.f16 d0, s15, s8
+.*: fe00 f814 vfmal.f16 d15, s0, s8\[0\]
+.*: fca7 0894 vfmsl.f16 d0, s15, s8
+.*: fe10 f81c vfmsl.f16 d15, s0, s8\[1\]
+.*: fc27 08b7 vfmal.f16 d0, s15, s15
+.*: fe00 f837 vfmal.f16 d15, s0, s15\[0\]
+.*: fca7 08b7 vfmsl.f16 d0, s15, s15
+.*: fe10 f83f vfmsl.f16 d15, s0, s15\[1\]
+.*: fc2f 0810 vfmal.f16 d0, s30, s0
+.*: fe40 e810 vfmal.f16 d30, s0, s0\[0\]
+.*: fcaf 0810 vfmsl.f16 d0, s30, s0
+.*: fe50 e818 vfmsl.f16 d30, s0, s0\[1\]
+.*: fc2f 0814 vfmal.f16 d0, s30, s8
+.*: fe40 e814 vfmal.f16 d30, s0, s8\[0\]
+.*: fcaf 0814 vfmsl.f16 d0, s30, s8
+.*: fe50 e81c vfmsl.f16 d30, s0, s8\[1\]
+.*: fc2f 0837 vfmal.f16 d0, s30, s15
+.*: fe40 e837 vfmal.f16 d30, s0, s15\[0\]
+.*: fcaf 0837 vfmsl.f16 d0, s30, s15
+.*: fe50 e83f vfmsl.f16 d30, s0, s15\[1\]
+.*: fc21 7810 vfmal.f16 d7, s2, s0
+.*: fe03 2890 vfmal.f16 d2, s7, s0\[0\]
+.*: fca1 7810 vfmsl.f16 d7, s2, s0
+.*: fe13 2898 vfmsl.f16 d2, s7, s0\[1\]
+.*: fc21 7814 vfmal.f16 d7, s2, s8
+.*: fe03 2894 vfmal.f16 d2, s7, s8\[0\]
+.*: fca1 7814 vfmsl.f16 d7, s2, s8
+.*: fe13 289c vfmsl.f16 d2, s7, s8\[1\]
+.*: fc21 7837 vfmal.f16 d7, s2, s15
+.*: fe03 28b7 vfmal.f16 d2, s7, s15\[0\]
+.*: fca1 7837 vfmsl.f16 d7, s2, s15
+.*: fe13 28bf vfmsl.f16 d2, s7, s15\[1\]
+.*: fc27 7890 vfmal.f16 d7, s15, s0
+.*: fe03 f890 vfmal.f16 d15, s7, s0\[0\]
+.*: fca7 7890 vfmsl.f16 d7, s15, s0
+.*: fe13 f898 vfmsl.f16 d15, s7, s0\[1\]
+.*: fc27 7894 vfmal.f16 d7, s15, s8
+.*: fe03 f894 vfmal.f16 d15, s7, s8\[0\]
+.*: fca7 7894 vfmsl.f16 d7, s15, s8
+.*: fe13 f89c vfmsl.f16 d15, s7, s8\[1\]
+.*: fc27 78b7 vfmal.f16 d7, s15, s15
+.*: fe03 f8b7 vfmal.f16 d15, s7, s15\[0\]
+.*: fca7 78b7 vfmsl.f16 d7, s15, s15
+.*: fe13 f8bf vfmsl.f16 d15, s7, s15\[1\]
+.*: fc2f 7810 vfmal.f16 d7, s30, s0
+.*: fe43 e890 vfmal.f16 d30, s7, s0\[0\]
+.*: fcaf 7810 vfmsl.f16 d7, s30, s0
+.*: fe53 e898 vfmsl.f16 d30, s7, s0\[1\]
+.*: fc2f 7814 vfmal.f16 d7, s30, s8
+.*: fe43 e894 vfmal.f16 d30, s7, s8\[0\]
+.*: fcaf 7814 vfmsl.f16 d7, s30, s8
+.*: fe53 e89c vfmsl.f16 d30, s7, s8\[1\]
+.*: fc2f 7837 vfmal.f16 d7, s30, s15
+.*: fe43 e8b7 vfmal.f16 d30, s7, s15\[0\]
+.*: fcaf 7837 vfmsl.f16 d7, s30, s15
+.*: fe53 e8bf vfmsl.f16 d30, s7, s15\[1\]
+.*: fc61 0810 vfmal.f16 d16, s2, s0
+.*: fe08 2810 vfmal.f16 d2, s16, s0\[0\]
+.*: fce1 0810 vfmsl.f16 d16, s2, s0
+.*: fe18 2818 vfmsl.f16 d2, s16, s0\[1\]
+.*: fc61 0814 vfmal.f16 d16, s2, s8
+.*: fe08 2814 vfmal.f16 d2, s16, s8\[0\]
+.*: fce1 0814 vfmsl.f16 d16, s2, s8
+.*: fe18 281c vfmsl.f16 d2, s16, s8\[1\]
+.*: fc61 0837 vfmal.f16 d16, s2, s15
+.*: fe08 2837 vfmal.f16 d2, s16, s15\[0\]
+.*: fce1 0837 vfmsl.f16 d16, s2, s15
+.*: fe18 283f vfmsl.f16 d2, s16, s15\[1\]
+.*: fc67 0890 vfmal.f16 d16, s15, s0
+.*: fe08 f810 vfmal.f16 d15, s16, s0\[0\]
+.*: fce7 0890 vfmsl.f16 d16, s15, s0
+.*: fe18 f818 vfmsl.f16 d15, s16, s0\[1\]
+.*: fc67 0894 vfmal.f16 d16, s15, s8
+.*: fe08 f814 vfmal.f16 d15, s16, s8\[0\]
+.*: fce7 0894 vfmsl.f16 d16, s15, s8
+.*: fe18 f81c vfmsl.f16 d15, s16, s8\[1\]
+.*: fc67 08b7 vfmal.f16 d16, s15, s15
+.*: fe08 f837 vfmal.f16 d15, s16, s15\[0\]
+.*: fce7 08b7 vfmsl.f16 d16, s15, s15
+.*: fe18 f83f vfmsl.f16 d15, s16, s15\[1\]
+.*: fc6f 0810 vfmal.f16 d16, s30, s0
+.*: fe48 e810 vfmal.f16 d30, s16, s0\[0\]
+.*: fcef 0810 vfmsl.f16 d16, s30, s0
+.*: fe58 e818 vfmsl.f16 d30, s16, s0\[1\]
+.*: fc6f 0814 vfmal.f16 d16, s30, s8
+.*: fe48 e814 vfmal.f16 d30, s16, s8\[0\]
+.*: fcef 0814 vfmsl.f16 d16, s30, s8
+.*: fe58 e81c vfmsl.f16 d30, s16, s8\[1\]
+.*: fc6f 0837 vfmal.f16 d16, s30, s15
+.*: fe48 e837 vfmal.f16 d30, s16, s15\[0\]
+.*: fcef 0837 vfmsl.f16 d16, s30, s15
+.*: fe58 e83f vfmsl.f16 d30, s16, s15\[1\]
+.*: fc61 f810 vfmal.f16 d31, s2, s0
+.*: fe0f 2890 vfmal.f16 d2, s31, s0\[0\]
+.*: fce1 f810 vfmsl.f16 d31, s2, s0
+.*: fe1f 2898 vfmsl.f16 d2, s31, s0\[1\]
+.*: fc61 f814 vfmal.f16 d31, s2, s8
+.*: fe0f 2894 vfmal.f16 d2, s31, s8\[0\]
+.*: fce1 f814 vfmsl.f16 d31, s2, s8
+.*: fe1f 289c vfmsl.f16 d2, s31, s8\[1\]
+.*: fc61 f837 vfmal.f16 d31, s2, s15
+.*: fe0f 28b7 vfmal.f16 d2, s31, s15\[0\]
+.*: fce1 f837 vfmsl.f16 d31, s2, s15
+.*: fe1f 28bf vfmsl.f16 d2, s31, s15\[1\]
+.*: fc67 f890 vfmal.f16 d31, s15, s0
+.*: fe0f f890 vfmal.f16 d15, s31, s0\[0\]
+.*: fce7 f890 vfmsl.f16 d31, s15, s0
+.*: fe1f f898 vfmsl.f16 d15, s31, s0\[1\]
+.*: fc67 f894 vfmal.f16 d31, s15, s8
+.*: fe0f f894 vfmal.f16 d15, s31, s8\[0\]
+.*: fce7 f894 vfmsl.f16 d31, s15, s8
+.*: fe1f f89c vfmsl.f16 d15, s31, s8\[1\]
+.*: fc67 f8b7 vfmal.f16 d31, s15, s15
+.*: fe0f f8b7 vfmal.f16 d15, s31, s15\[0\]
+.*: fce7 f8b7 vfmsl.f16 d31, s15, s15
+.*: fe1f f8bf vfmsl.f16 d15, s31, s15\[1\]
+.*: fc6f f810 vfmal.f16 d31, s30, s0
+.*: fe4f e890 vfmal.f16 d30, s31, s0\[0\]
+.*: fcef f810 vfmsl.f16 d31, s30, s0
+.*: fe5f e898 vfmsl.f16 d30, s31, s0\[1\]
+.*: fc6f f814 vfmal.f16 d31, s30, s8
+.*: fe4f e894 vfmal.f16 d30, s31, s8\[0\]
+.*: fcef f814 vfmsl.f16 d31, s30, s8
+.*: fe5f e89c vfmsl.f16 d30, s31, s8\[1\]
+.*: fc6f f837 vfmal.f16 d31, s30, s15
+.*: fe4f e8b7 vfmal.f16 d30, s31, s15\[0\]
+.*: fcef f837 vfmsl.f16 d31, s30, s15
+.*: fe5f e8bf vfmsl.f16 d30, s31, s15\[1\]
+.*: fc20 4850 vfmal.f16 q2, d0, d0
+.*: fe02 0850 vfmal.f16 q0, d2, d0\[0\]
+.*: fca0 4850 vfmsl.f16 q2, d0, d0
+.*: fe12 0878 vfmsl.f16 q0, d2, d0\[3\]
+.*: fc20 4857 vfmal.f16 q2, d0, d7
+.*: fe02 0857 vfmal.f16 q0, d2, d7\[0\]
+.*: fca0 4857 vfmsl.f16 q2, d0, d7
+.*: fe12 087f vfmsl.f16 q0, d2, d7\[3\]
+.*: fc20 6850 vfmal.f16 q3, d0, d0
+.*: fe03 0850 vfmal.f16 q0, d3, d0\[0\]
+.*: fca0 6850 vfmsl.f16 q3, d0, d0
+.*: fe13 0878 vfmsl.f16 q0, d3, d0\[3\]
+.*: fc20 6857 vfmal.f16 q3, d0, d7
+.*: fe03 0857 vfmal.f16 q0, d3, d7\[0\]
+.*: fca0 6857 vfmsl.f16 q3, d0, d7
+.*: fe13 087f vfmsl.f16 q0, d3, d7\[3\]
+.*: fc60 a850 vfmal.f16 q13, d0, d0
+.*: fe0d 0850 vfmal.f16 q0, d13, d0\[0\]
+.*: fce0 a850 vfmsl.f16 q13, d0, d0
+.*: fe1d 0878 vfmsl.f16 q0, d13, d0\[3\]
+.*: fc60 a857 vfmal.f16 q13, d0, d7
+.*: fe0d 0857 vfmal.f16 q0, d13, d7\[0\]
+.*: fce0 a857 vfmsl.f16 q13, d0, d7
+.*: fe1d 087f vfmsl.f16 q0, d13, d7\[3\]
+.*: fc21 4850 vfmal.f16 q2, d1, d0
+.*: fe02 2850 vfmal.f16 q1, d2, d0\[0\]
+.*: fca1 4850 vfmsl.f16 q2, d1, d0
+.*: fe12 2878 vfmsl.f16 q1, d2, d0\[3\]
+.*: fc21 4857 vfmal.f16 q2, d1, d7
+.*: fe02 2857 vfmal.f16 q1, d2, d7\[0\]
+.*: fca1 4857 vfmsl.f16 q2, d1, d7
+.*: fe12 287f vfmsl.f16 q1, d2, d7\[3\]
+.*: fc21 6850 vfmal.f16 q3, d1, d0
+.*: fe03 2850 vfmal.f16 q1, d3, d0\[0\]
+.*: fca1 6850 vfmsl.f16 q3, d1, d0
+.*: fe13 2878 vfmsl.f16 q1, d3, d0\[3\]
+.*: fc21 6857 vfmal.f16 q3, d1, d7
+.*: fe03 2857 vfmal.f16 q1, d3, d7\[0\]
+.*: fca1 6857 vfmsl.f16 q3, d1, d7
+.*: fe13 287f vfmsl.f16 q1, d3, d7\[3\]
+.*: fc61 a850 vfmal.f16 q13, d1, d0
+.*: fe0d 2850 vfmal.f16 q1, d13, d0\[0\]
+.*: fce1 a850 vfmsl.f16 q13, d1, d0
+.*: fe1d 2878 vfmsl.f16 q1, d13, d0\[3\]
+.*: fc61 a857 vfmal.f16 q13, d1, d7
+.*: fe0d 2857 vfmal.f16 q1, d13, d7\[0\]
+.*: fce1 a857 vfmsl.f16 q13, d1, d7
+.*: fe1d 287f vfmsl.f16 q1, d13, d7\[3\]
+.*: fc26 4850 vfmal.f16 q2, d6, d0
+.*: fe02 c850 vfmal.f16 q6, d2, d0\[0\]
+.*: fca6 4850 vfmsl.f16 q2, d6, d0
+.*: fe12 c878 vfmsl.f16 q6, d2, d0\[3\]
+.*: fc26 4857 vfmal.f16 q2, d6, d7
+.*: fe02 c857 vfmal.f16 q6, d2, d7\[0\]
+.*: fca6 4857 vfmsl.f16 q2, d6, d7
+.*: fe12 c87f vfmsl.f16 q6, d2, d7\[3\]
+.*: fc26 6850 vfmal.f16 q3, d6, d0
+.*: fe03 c850 vfmal.f16 q6, d3, d0\[0\]
+.*: fca6 6850 vfmsl.f16 q3, d6, d0
+.*: fe13 c878 vfmsl.f16 q6, d3, d0\[3\]
+.*: fc26 6857 vfmal.f16 q3, d6, d7
+.*: fe03 c857 vfmal.f16 q6, d3, d7\[0\]
+.*: fca6 6857 vfmsl.f16 q3, d6, d7
+.*: fe13 c87f vfmsl.f16 q6, d3, d7\[3\]
+.*: fc66 a850 vfmal.f16 q13, d6, d0
+.*: fe0d c850 vfmal.f16 q6, d13, d0\[0\]
+.*: fce6 a850 vfmsl.f16 q13, d6, d0
+.*: fe1d c878 vfmsl.f16 q6, d13, d0\[3\]
+.*: fc66 a857 vfmal.f16 q13, d6, d7
+.*: fe0d c857 vfmal.f16 q6, d13, d7\[0\]
+.*: fce6 a857 vfmsl.f16 q13, d6, d7
+.*: fe1d c87f vfmsl.f16 q6, d13, d7\[3\]
+.*: fc2f 4850 vfmal.f16 q2, d15, d0
+.*: fe42 e850 vfmal.f16 q15, d2, d0\[0\]
+.*: fcaf 4850 vfmsl.f16 q2, d15, d0
+.*: fe52 e878 vfmsl.f16 q15, d2, d0\[3\]
+.*: fc2f 4857 vfmal.f16 q2, d15, d7
+.*: fe42 e857 vfmal.f16 q15, d2, d7\[0\]
+.*: fcaf 4857 vfmsl.f16 q2, d15, d7
+.*: fe52 e87f vfmsl.f16 q15, d2, d7\[3\]
+.*: fc2f 6850 vfmal.f16 q3, d15, d0
+.*: fe43 e850 vfmal.f16 q15, d3, d0\[0\]
+.*: fcaf 6850 vfmsl.f16 q3, d15, d0
+.*: fe53 e878 vfmsl.f16 q15, d3, d0\[3\]
+.*: fc2f 6857 vfmal.f16 q3, d15, d7
+.*: fe43 e857 vfmal.f16 q15, d3, d7\[0\]
+.*: fcaf 6857 vfmsl.f16 q3, d15, d7
+.*: fe53 e87f vfmsl.f16 q15, d3, d7\[3\]
+.*: fc6f a850 vfmal.f16 q13, d15, d0
+.*: fe4d e850 vfmal.f16 q15, d13, d0\[0\]
+.*: fcef a850 vfmsl.f16 q13, d15, d0
+.*: fe5d e878 vfmsl.f16 q15, d13, d0\[3\]
+.*: fc6f a857 vfmal.f16 q13, d15, d7
+.*: fe4d e857 vfmal.f16 q15, d13, d7\[0\]
+.*: fcef a857 vfmsl.f16 q13, d15, d7
+.*: fe5d e87f vfmsl.f16 q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8_2-a-fp16.d b/gas/testsuite/gas/arm/armv8_2-a-fp16.d
new file mode 100644
index 0000000..9f99828
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a-fp16.d
@@ -0,0 +1,249 @@
+#as: -march=armv8.2-a+fp16 -mfpu=neon-fp-armv8
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*: fc210810 vfmal.f16 d0, s2, s0
+.*: fe002810 vfmal.f16 d2, s0, s0\[0\]
+.*: fca10810 vfmsl.f16 d0, s2, s0
+.*: fe102818 vfmsl.f16 d2, s0, s0\[1\]
+.*: fc210814 vfmal.f16 d0, s2, s8
+.*: fe002814 vfmal.f16 d2, s0, s8\[0\]
+.*: fca10814 vfmsl.f16 d0, s2, s8
+.*: fe10281c vfmsl.f16 d2, s0, s8\[1\]
+.*: fc210837 vfmal.f16 d0, s2, s15
+.*: fe002837 vfmal.f16 d2, s0, s15\[0\]
+.*: fca10837 vfmsl.f16 d0, s2, s15
+.*: fe10283f vfmsl.f16 d2, s0, s15\[1\]
+.*: fc270890 vfmal.f16 d0, s15, s0
+.*: fe00f810 vfmal.f16 d15, s0, s0\[0\]
+.*: fca70890 vfmsl.f16 d0, s15, s0
+.*: fe10f818 vfmsl.f16 d15, s0, s0\[1\]
+.*: fc270894 vfmal.f16 d0, s15, s8
+.*: fe00f814 vfmal.f16 d15, s0, s8\[0\]
+.*: fca70894 vfmsl.f16 d0, s15, s8
+.*: fe10f81c vfmsl.f16 d15, s0, s8\[1\]
+.*: fc2708b7 vfmal.f16 d0, s15, s15
+.*: fe00f837 vfmal.f16 d15, s0, s15\[0\]
+.*: fca708b7 vfmsl.f16 d0, s15, s15
+.*: fe10f83f vfmsl.f16 d15, s0, s15\[1\]
+.*: fc2f0810 vfmal.f16 d0, s30, s0
+.*: fe40e810 vfmal.f16 d30, s0, s0\[0\]
+.*: fcaf0810 vfmsl.f16 d0, s30, s0
+.*: fe50e818 vfmsl.f16 d30, s0, s0\[1\]
+.*: fc2f0814 vfmal.f16 d0, s30, s8
+.*: fe40e814 vfmal.f16 d30, s0, s8\[0\]
+.*: fcaf0814 vfmsl.f16 d0, s30, s8
+.*: fe50e81c vfmsl.f16 d30, s0, s8\[1\]
+.*: fc2f0837 vfmal.f16 d0, s30, s15
+.*: fe40e837 vfmal.f16 d30, s0, s15\[0\]
+.*: fcaf0837 vfmsl.f16 d0, s30, s15
+.*: fe50e83f vfmsl.f16 d30, s0, s15\[1\]
+.*: fc217810 vfmal.f16 d7, s2, s0
+.*: fe032890 vfmal.f16 d2, s7, s0\[0\]
+.*: fca17810 vfmsl.f16 d7, s2, s0
+.*: fe132898 vfmsl.f16 d2, s7, s0\[1\]
+.*: fc217814 vfmal.f16 d7, s2, s8
+.*: fe032894 vfmal.f16 d2, s7, s8\[0\]
+.*: fca17814 vfmsl.f16 d7, s2, s8
+.*: fe13289c vfmsl.f16 d2, s7, s8\[1\]
+.*: fc217837 vfmal.f16 d7, s2, s15
+.*: fe0328b7 vfmal.f16 d2, s7, s15\[0\]
+.*: fca17837 vfmsl.f16 d7, s2, s15
+.*: fe1328bf vfmsl.f16 d2, s7, s15\[1\]
+.*: fc277890 vfmal.f16 d7, s15, s0
+.*: fe03f890 vfmal.f16 d15, s7, s0\[0\]
+.*: fca77890 vfmsl.f16 d7, s15, s0
+.*: fe13f898 vfmsl.f16 d15, s7, s0\[1\]
+.*: fc277894 vfmal.f16 d7, s15, s8
+.*: fe03f894 vfmal.f16 d15, s7, s8\[0\]
+.*: fca77894 vfmsl.f16 d7, s15, s8
+.*: fe13f89c vfmsl.f16 d15, s7, s8\[1\]
+.*: fc2778b7 vfmal.f16 d7, s15, s15
+.*: fe03f8b7 vfmal.f16 d15, s7, s15\[0\]
+.*: fca778b7 vfmsl.f16 d7, s15, s15
+.*: fe13f8bf vfmsl.f16 d15, s7, s15\[1\]
+.*: fc2f7810 vfmal.f16 d7, s30, s0
+.*: fe43e890 vfmal.f16 d30, s7, s0\[0\]
+.*: fcaf7810 vfmsl.f16 d7, s30, s0
+.*: fe53e898 vfmsl.f16 d30, s7, s0\[1\]
+.*: fc2f7814 vfmal.f16 d7, s30, s8
+.*: fe43e894 vfmal.f16 d30, s7, s8\[0\]
+.*: fcaf7814 vfmsl.f16 d7, s30, s8
+.*: fe53e89c vfmsl.f16 d30, s7, s8\[1\]
+.*: fc2f7837 vfmal.f16 d7, s30, s15
+.*: fe43e8b7 vfmal.f16 d30, s7, s15\[0\]
+.*: fcaf7837 vfmsl.f16 d7, s30, s15
+.*: fe53e8bf vfmsl.f16 d30, s7, s15\[1\]
+.*: fc610810 vfmal.f16 d16, s2, s0
+.*: fe082810 vfmal.f16 d2, s16, s0\[0\]
+.*: fce10810 vfmsl.f16 d16, s2, s0
+.*: fe182818 vfmsl.f16 d2, s16, s0\[1\]
+.*: fc610814 vfmal.f16 d16, s2, s8
+.*: fe082814 vfmal.f16 d2, s16, s8\[0\]
+.*: fce10814 vfmsl.f16 d16, s2, s8
+.*: fe18281c vfmsl.f16 d2, s16, s8\[1\]
+.*: fc610837 vfmal.f16 d16, s2, s15
+.*: fe082837 vfmal.f16 d2, s16, s15\[0\]
+.*: fce10837 vfmsl.f16 d16, s2, s15
+.*: fe18283f vfmsl.f16 d2, s16, s15\[1\]
+.*: fc670890 vfmal.f16 d16, s15, s0
+.*: fe08f810 vfmal.f16 d15, s16, s0\[0\]
+.*: fce70890 vfmsl.f16 d16, s15, s0
+.*: fe18f818 vfmsl.f16 d15, s16, s0\[1\]
+.*: fc670894 vfmal.f16 d16, s15, s8
+.*: fe08f814 vfmal.f16 d15, s16, s8\[0\]
+.*: fce70894 vfmsl.f16 d16, s15, s8
+.*: fe18f81c vfmsl.f16 d15, s16, s8\[1\]
+.*: fc6708b7 vfmal.f16 d16, s15, s15
+.*: fe08f837 vfmal.f16 d15, s16, s15\[0\]
+.*: fce708b7 vfmsl.f16 d16, s15, s15
+.*: fe18f83f vfmsl.f16 d15, s16, s15\[1\]
+.*: fc6f0810 vfmal.f16 d16, s30, s0
+.*: fe48e810 vfmal.f16 d30, s16, s0\[0\]
+.*: fcef0810 vfmsl.f16 d16, s30, s0
+.*: fe58e818 vfmsl.f16 d30, s16, s0\[1\]
+.*: fc6f0814 vfmal.f16 d16, s30, s8
+.*: fe48e814 vfmal.f16 d30, s16, s8\[0\]
+.*: fcef0814 vfmsl.f16 d16, s30, s8
+.*: fe58e81c vfmsl.f16 d30, s16, s8\[1\]
+.*: fc6f0837 vfmal.f16 d16, s30, s15
+.*: fe48e837 vfmal.f16 d30, s16, s15\[0\]
+.*: fcef0837 vfmsl.f16 d16, s30, s15
+.*: fe58e83f vfmsl.f16 d30, s16, s15\[1\]
+.*: fc61f810 vfmal.f16 d31, s2, s0
+.*: fe0f2890 vfmal.f16 d2, s31, s0\[0\]
+.*: fce1f810 vfmsl.f16 d31, s2, s0
+.*: fe1f2898 vfmsl.f16 d2, s31, s0\[1\]
+.*: fc61f814 vfmal.f16 d31, s2, s8
+.*: fe0f2894 vfmal.f16 d2, s31, s8\[0\]
+.*: fce1f814 vfmsl.f16 d31, s2, s8
+.*: fe1f289c vfmsl.f16 d2, s31, s8\[1\]
+.*: fc61f837 vfmal.f16 d31, s2, s15
+.*: fe0f28b7 vfmal.f16 d2, s31, s15\[0\]
+.*: fce1f837 vfmsl.f16 d31, s2, s15
+.*: fe1f28bf vfmsl.f16 d2, s31, s15\[1\]
+.*: fc67f890 vfmal.f16 d31, s15, s0
+.*: fe0ff890 vfmal.f16 d15, s31, s0\[0\]
+.*: fce7f890 vfmsl.f16 d31, s15, s0
+.*: fe1ff898 vfmsl.f16 d15, s31, s0\[1\]
+.*: fc67f894 vfmal.f16 d31, s15, s8
+.*: fe0ff894 vfmal.f16 d15, s31, s8\[0\]
+.*: fce7f894 vfmsl.f16 d31, s15, s8
+.*: fe1ff89c vfmsl.f16 d15, s31, s8\[1\]
+.*: fc67f8b7 vfmal.f16 d31, s15, s15
+.*: fe0ff8b7 vfmal.f16 d15, s31, s15\[0\]
+.*: fce7f8b7 vfmsl.f16 d31, s15, s15
+.*: fe1ff8bf vfmsl.f16 d15, s31, s15\[1\]
+.*: fc6ff810 vfmal.f16 d31, s30, s0
+.*: fe4fe890 vfmal.f16 d30, s31, s0\[0\]
+.*: fceff810 vfmsl.f16 d31, s30, s0
+.*: fe5fe898 vfmsl.f16 d30, s31, s0\[1\]
+.*: fc6ff814 vfmal.f16 d31, s30, s8
+.*: fe4fe894 vfmal.f16 d30, s31, s8\[0\]
+.*: fceff814 vfmsl.f16 d31, s30, s8
+.*: fe5fe89c vfmsl.f16 d30, s31, s8\[1\]
+.*: fc6ff837 vfmal.f16 d31, s30, s15
+.*: fe4fe8b7 vfmal.f16 d30, s31, s15\[0\]
+.*: fceff837 vfmsl.f16 d31, s30, s15
+.*: fe5fe8bf vfmsl.f16 d30, s31, s15\[1\]
+.*: fc204850 vfmal.f16 q2, d0, d0
+.*: fe020850 vfmal.f16 q0, d2, d0\[0\]
+.*: fca04850 vfmsl.f16 q2, d0, d0
+.*: fe120878 vfmsl.f16 q0, d2, d0\[3\]
+.*: fc204857 vfmal.f16 q2, d0, d7
+.*: fe020857 vfmal.f16 q0, d2, d7\[0\]
+.*: fca04857 vfmsl.f16 q2, d0, d7
+.*: fe12087f vfmsl.f16 q0, d2, d7\[3\]
+.*: fc206850 vfmal.f16 q3, d0, d0
+.*: fe030850 vfmal.f16 q0, d3, d0\[0\]
+.*: fca06850 vfmsl.f16 q3, d0, d0
+.*: fe130878 vfmsl.f16 q0, d3, d0\[3\]
+.*: fc206857 vfmal.f16 q3, d0, d7
+.*: fe030857 vfmal.f16 q0, d3, d7\[0\]
+.*: fca06857 vfmsl.f16 q3, d0, d7
+.*: fe13087f vfmsl.f16 q0, d3, d7\[3\]
+.*: fc60a850 vfmal.f16 q13, d0, d0
+.*: fe0d0850 vfmal.f16 q0, d13, d0\[0\]
+.*: fce0a850 vfmsl.f16 q13, d0, d0
+.*: fe1d0878 vfmsl.f16 q0, d13, d0\[3\]
+.*: fc60a857 vfmal.f16 q13, d0, d7
+.*: fe0d0857 vfmal.f16 q0, d13, d7\[0\]
+.*: fce0a857 vfmsl.f16 q13, d0, d7
+.*: fe1d087f vfmsl.f16 q0, d13, d7\[3\]
+.*: fc214850 vfmal.f16 q2, d1, d0
+.*: fe022850 vfmal.f16 q1, d2, d0\[0\]
+.*: fca14850 vfmsl.f16 q2, d1, d0
+.*: fe122878 vfmsl.f16 q1, d2, d0\[3\]
+.*: fc214857 vfmal.f16 q2, d1, d7
+.*: fe022857 vfmal.f16 q1, d2, d7\[0\]
+.*: fca14857 vfmsl.f16 q2, d1, d7
+.*: fe12287f vfmsl.f16 q1, d2, d7\[3\]
+.*: fc216850 vfmal.f16 q3, d1, d0
+.*: fe032850 vfmal.f16 q1, d3, d0\[0\]
+.*: fca16850 vfmsl.f16 q3, d1, d0
+.*: fe132878 vfmsl.f16 q1, d3, d0\[3\]
+.*: fc216857 vfmal.f16 q3, d1, d7
+.*: fe032857 vfmal.f16 q1, d3, d7\[0\]
+.*: fca16857 vfmsl.f16 q3, d1, d7
+.*: fe13287f vfmsl.f16 q1, d3, d7\[3\]
+.*: fc61a850 vfmal.f16 q13, d1, d0
+.*: fe0d2850 vfmal.f16 q1, d13, d0\[0\]
+.*: fce1a850 vfmsl.f16 q13, d1, d0
+.*: fe1d2878 vfmsl.f16 q1, d13, d0\[3\]
+.*: fc61a857 vfmal.f16 q13, d1, d7
+.*: fe0d2857 vfmal.f16 q1, d13, d7\[0\]
+.*: fce1a857 vfmsl.f16 q13, d1, d7
+.*: fe1d287f vfmsl.f16 q1, d13, d7\[3\]
+.*: fc264850 vfmal.f16 q2, d6, d0
+.*: fe02c850 vfmal.f16 q6, d2, d0\[0\]
+.*: fca64850 vfmsl.f16 q2, d6, d0
+.*: fe12c878 vfmsl.f16 q6, d2, d0\[3\]
+.*: fc264857 vfmal.f16 q2, d6, d7
+.*: fe02c857 vfmal.f16 q6, d2, d7\[0\]
+.*: fca64857 vfmsl.f16 q2, d6, d7
+.*: fe12c87f vfmsl.f16 q6, d2, d7\[3\]
+.*: fc266850 vfmal.f16 q3, d6, d0
+.*: fe03c850 vfmal.f16 q6, d3, d0\[0\]
+.*: fca66850 vfmsl.f16 q3, d6, d0
+.*: fe13c878 vfmsl.f16 q6, d3, d0\[3\]
+.*: fc266857 vfmal.f16 q3, d6, d7
+.*: fe03c857 vfmal.f16 q6, d3, d7\[0\]
+.*: fca66857 vfmsl.f16 q3, d6, d7
+.*: fe13c87f vfmsl.f16 q6, d3, d7\[3\]
+.*: fc66a850 vfmal.f16 q13, d6, d0
+.*: fe0dc850 vfmal.f16 q6, d13, d0\[0\]
+.*: fce6a850 vfmsl.f16 q13, d6, d0
+.*: fe1dc878 vfmsl.f16 q6, d13, d0\[3\]
+.*: fc66a857 vfmal.f16 q13, d6, d7
+.*: fe0dc857 vfmal.f16 q6, d13, d7\[0\]
+.*: fce6a857 vfmsl.f16 q13, d6, d7
+.*: fe1dc87f vfmsl.f16 q6, d13, d7\[3\]
+.*: fc2f4850 vfmal.f16 q2, d15, d0
+.*: fe42e850 vfmal.f16 q15, d2, d0\[0\]
+.*: fcaf4850 vfmsl.f16 q2, d15, d0
+.*: fe52e878 vfmsl.f16 q15, d2, d0\[3\]
+.*: fc2f4857 vfmal.f16 q2, d15, d7
+.*: fe42e857 vfmal.f16 q15, d2, d7\[0\]
+.*: fcaf4857 vfmsl.f16 q2, d15, d7
+.*: fe52e87f vfmsl.f16 q15, d2, d7\[3\]
+.*: fc2f6850 vfmal.f16 q3, d15, d0
+.*: fe43e850 vfmal.f16 q15, d3, d0\[0\]
+.*: fcaf6850 vfmsl.f16 q3, d15, d0
+.*: fe53e878 vfmsl.f16 q15, d3, d0\[3\]
+.*: fc2f6857 vfmal.f16 q3, d15, d7
+.*: fe43e857 vfmal.f16 q15, d3, d7\[0\]
+.*: fcaf6857 vfmsl.f16 q3, d15, d7
+.*: fe53e87f vfmsl.f16 q15, d3, d7\[3\]
+.*: fc6fa850 vfmal.f16 q13, d15, d0
+.*: fe4de850 vfmal.f16 q15, d13, d0\[0\]
+.*: fcefa850 vfmsl.f16 q13, d15, d0
+.*: fe5de878 vfmsl.f16 q15, d13, d0\[3\]
+.*: fc6fa857 vfmal.f16 q13, d15, d7
+.*: fe4de857 vfmal.f16 q15, d13, d7\[0\]
+.*: fcefa857 vfmsl.f16 q13, d15, d7
+.*: fe5de87f vfmsl.f16 q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8_2-a-fp16.s b/gas/testsuite/gas/arm/armv8_2-a-fp16.s
new file mode 100644
index 0000000..0adbd42
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a-fp16.s
@@ -0,0 +1,46 @@
+ .macro fmac_iter_d_n op, d, n
+ .irp m, 0, 8, 15
+ vfmal.f16 d\d, s\n, s\m
+ vfmal.f16 d\n, s\d, s\m[0]
+ vfmsl.f16 d\d, s\n, s\m
+ vfmsl.f16 d\n, s\d, s\m[1]
+ .endr
+ .endm
+
+ .macro fmac_iter_d op, d
+ .irp n, 2, 15, 30
+ fmac_iter_d_n \op, \d, \n
+ .endr
+ .endm
+
+ .macro iter
+ .irp d, 0, 7, 16, 31
+ fmac_iter_d \op, \d
+ .endr
+ .endm
+
+ .macro fmac_q_iter_d_n op, d, n
+ .irp m, 0, 7
+ vfmal.f16 q\n, d\d, d\m
+ vfmal.f16 q\d, d\n, d\m[0]
+ vfmsl.f16 q\n, d\d, d\m
+ vfmsl.f16 q\d, d\n, d\m[3]
+ .endr
+ .endm
+
+ .macro fmac_q_iter_d op, d
+ .irp n, 2, 3, 13
+ fmac_q_iter_d_n \op, \d, \n
+ .endr
+ .endm
+
+ .macro q_iter
+ .irp d, 0, 1, 6, 15
+ fmac_q_iter_d \op, \d
+ .endr
+ .endm
+
+ .text
+func:
+ iter
+ q_iter
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp16.d b/gas/testsuite/gas/arm/armv8_3-a-fp16.d
new file mode 100644
index 0000000..545275a
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp16.d
@@ -0,0 +1,249 @@
+#as: -march=armv8.3-a+fp16 -mfpu=neon-fp-armv8
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*: fc210810 vfmal.f16 d0, s2, s0
+.*: fe002810 vfmal.f16 d2, s0, s0\[0\]
+.*: fca10810 vfmsl.f16 d0, s2, s0
+.*: fe102818 vfmsl.f16 d2, s0, s0\[1\]
+.*: fc210814 vfmal.f16 d0, s2, s8
+.*: fe002814 vfmal.f16 d2, s0, s8\[0\]
+.*: fca10814 vfmsl.f16 d0, s2, s8
+.*: fe10281c vfmsl.f16 d2, s0, s8\[1\]
+.*: fc210837 vfmal.f16 d0, s2, s15
+.*: fe002837 vfmal.f16 d2, s0, s15\[0\]
+.*: fca10837 vfmsl.f16 d0, s2, s15
+.*: fe10283f vfmsl.f16 d2, s0, s15\[1\]
+.*: fc270890 vfmal.f16 d0, s15, s0
+.*: fe00f810 vfmal.f16 d15, s0, s0\[0\]
+.*: fca70890 vfmsl.f16 d0, s15, s0
+.*: fe10f818 vfmsl.f16 d15, s0, s0\[1\]
+.*: fc270894 vfmal.f16 d0, s15, s8
+.*: fe00f814 vfmal.f16 d15, s0, s8\[0\]
+.*: fca70894 vfmsl.f16 d0, s15, s8
+.*: fe10f81c vfmsl.f16 d15, s0, s8\[1\]
+.*: fc2708b7 vfmal.f16 d0, s15, s15
+.*: fe00f837 vfmal.f16 d15, s0, s15\[0\]
+.*: fca708b7 vfmsl.f16 d0, s15, s15
+.*: fe10f83f vfmsl.f16 d15, s0, s15\[1\]
+.*: fc2f0810 vfmal.f16 d0, s30, s0
+.*: fe40e810 vfmal.f16 d30, s0, s0\[0\]
+.*: fcaf0810 vfmsl.f16 d0, s30, s0
+.*: fe50e818 vfmsl.f16 d30, s0, s0\[1\]
+.*: fc2f0814 vfmal.f16 d0, s30, s8
+.*: fe40e814 vfmal.f16 d30, s0, s8\[0\]
+.*: fcaf0814 vfmsl.f16 d0, s30, s8
+.*: fe50e81c vfmsl.f16 d30, s0, s8\[1\]
+.*: fc2f0837 vfmal.f16 d0, s30, s15
+.*: fe40e837 vfmal.f16 d30, s0, s15\[0\]
+.*: fcaf0837 vfmsl.f16 d0, s30, s15
+.*: fe50e83f vfmsl.f16 d30, s0, s15\[1\]
+.*: fc217810 vfmal.f16 d7, s2, s0
+.*: fe032890 vfmal.f16 d2, s7, s0\[0\]
+.*: fca17810 vfmsl.f16 d7, s2, s0
+.*: fe132898 vfmsl.f16 d2, s7, s0\[1\]
+.*: fc217814 vfmal.f16 d7, s2, s8
+.*: fe032894 vfmal.f16 d2, s7, s8\[0\]
+.*: fca17814 vfmsl.f16 d7, s2, s8
+.*: fe13289c vfmsl.f16 d2, s7, s8\[1\]
+.*: fc217837 vfmal.f16 d7, s2, s15
+.*: fe0328b7 vfmal.f16 d2, s7, s15\[0\]
+.*: fca17837 vfmsl.f16 d7, s2, s15
+.*: fe1328bf vfmsl.f16 d2, s7, s15\[1\]
+.*: fc277890 vfmal.f16 d7, s15, s0
+.*: fe03f890 vfmal.f16 d15, s7, s0\[0\]
+.*: fca77890 vfmsl.f16 d7, s15, s0
+.*: fe13f898 vfmsl.f16 d15, s7, s0\[1\]
+.*: fc277894 vfmal.f16 d7, s15, s8
+.*: fe03f894 vfmal.f16 d15, s7, s8\[0\]
+.*: fca77894 vfmsl.f16 d7, s15, s8
+.*: fe13f89c vfmsl.f16 d15, s7, s8\[1\]
+.*: fc2778b7 vfmal.f16 d7, s15, s15
+.*: fe03f8b7 vfmal.f16 d15, s7, s15\[0\]
+.*: fca778b7 vfmsl.f16 d7, s15, s15
+.*: fe13f8bf vfmsl.f16 d15, s7, s15\[1\]
+.*: fc2f7810 vfmal.f16 d7, s30, s0
+.*: fe43e890 vfmal.f16 d30, s7, s0\[0\]
+.*: fcaf7810 vfmsl.f16 d7, s30, s0
+.*: fe53e898 vfmsl.f16 d30, s7, s0\[1\]
+.*: fc2f7814 vfmal.f16 d7, s30, s8
+.*: fe43e894 vfmal.f16 d30, s7, s8\[0\]
+.*: fcaf7814 vfmsl.f16 d7, s30, s8
+.*: fe53e89c vfmsl.f16 d30, s7, s8\[1\]
+.*: fc2f7837 vfmal.f16 d7, s30, s15
+.*: fe43e8b7 vfmal.f16 d30, s7, s15\[0\]
+.*: fcaf7837 vfmsl.f16 d7, s30, s15
+.*: fe53e8bf vfmsl.f16 d30, s7, s15\[1\]
+.*: fc610810 vfmal.f16 d16, s2, s0
+.*: fe082810 vfmal.f16 d2, s16, s0\[0\]
+.*: fce10810 vfmsl.f16 d16, s2, s0
+.*: fe182818 vfmsl.f16 d2, s16, s0\[1\]
+.*: fc610814 vfmal.f16 d16, s2, s8
+.*: fe082814 vfmal.f16 d2, s16, s8\[0\]
+.*: fce10814 vfmsl.f16 d16, s2, s8
+.*: fe18281c vfmsl.f16 d2, s16, s8\[1\]
+.*: fc610837 vfmal.f16 d16, s2, s15
+.*: fe082837 vfmal.f16 d2, s16, s15\[0\]
+.*: fce10837 vfmsl.f16 d16, s2, s15
+.*: fe18283f vfmsl.f16 d2, s16, s15\[1\]
+.*: fc670890 vfmal.f16 d16, s15, s0
+.*: fe08f810 vfmal.f16 d15, s16, s0\[0\]
+.*: fce70890 vfmsl.f16 d16, s15, s0
+.*: fe18f818 vfmsl.f16 d15, s16, s0\[1\]
+.*: fc670894 vfmal.f16 d16, s15, s8
+.*: fe08f814 vfmal.f16 d15, s16, s8\[0\]
+.*: fce70894 vfmsl.f16 d16, s15, s8
+.*: fe18f81c vfmsl.f16 d15, s16, s8\[1\]
+.*: fc6708b7 vfmal.f16 d16, s15, s15
+.*: fe08f837 vfmal.f16 d15, s16, s15\[0\]
+.*: fce708b7 vfmsl.f16 d16, s15, s15
+.*: fe18f83f vfmsl.f16 d15, s16, s15\[1\]
+.*: fc6f0810 vfmal.f16 d16, s30, s0
+.*: fe48e810 vfmal.f16 d30, s16, s0\[0\]
+.*: fcef0810 vfmsl.f16 d16, s30, s0
+.*: fe58e818 vfmsl.f16 d30, s16, s0\[1\]
+.*: fc6f0814 vfmal.f16 d16, s30, s8
+.*: fe48e814 vfmal.f16 d30, s16, s8\[0\]
+.*: fcef0814 vfmsl.f16 d16, s30, s8
+.*: fe58e81c vfmsl.f16 d30, s16, s8\[1\]
+.*: fc6f0837 vfmal.f16 d16, s30, s15
+.*: fe48e837 vfmal.f16 d30, s16, s15\[0\]
+.*: fcef0837 vfmsl.f16 d16, s30, s15
+.*: fe58e83f vfmsl.f16 d30, s16, s15\[1\]
+.*: fc61f810 vfmal.f16 d31, s2, s0
+.*: fe0f2890 vfmal.f16 d2, s31, s0\[0\]
+.*: fce1f810 vfmsl.f16 d31, s2, s0
+.*: fe1f2898 vfmsl.f16 d2, s31, s0\[1\]
+.*: fc61f814 vfmal.f16 d31, s2, s8
+.*: fe0f2894 vfmal.f16 d2, s31, s8\[0\]
+.*: fce1f814 vfmsl.f16 d31, s2, s8
+.*: fe1f289c vfmsl.f16 d2, s31, s8\[1\]
+.*: fc61f837 vfmal.f16 d31, s2, s15
+.*: fe0f28b7 vfmal.f16 d2, s31, s15\[0\]
+.*: fce1f837 vfmsl.f16 d31, s2, s15
+.*: fe1f28bf vfmsl.f16 d2, s31, s15\[1\]
+.*: fc67f890 vfmal.f16 d31, s15, s0
+.*: fe0ff890 vfmal.f16 d15, s31, s0\[0\]
+.*: fce7f890 vfmsl.f16 d31, s15, s0
+.*: fe1ff898 vfmsl.f16 d15, s31, s0\[1\]
+.*: fc67f894 vfmal.f16 d31, s15, s8
+.*: fe0ff894 vfmal.f16 d15, s31, s8\[0\]
+.*: fce7f894 vfmsl.f16 d31, s15, s8
+.*: fe1ff89c vfmsl.f16 d15, s31, s8\[1\]
+.*: fc67f8b7 vfmal.f16 d31, s15, s15
+.*: fe0ff8b7 vfmal.f16 d15, s31, s15\[0\]
+.*: fce7f8b7 vfmsl.f16 d31, s15, s15
+.*: fe1ff8bf vfmsl.f16 d15, s31, s15\[1\]
+.*: fc6ff810 vfmal.f16 d31, s30, s0
+.*: fe4fe890 vfmal.f16 d30, s31, s0\[0\]
+.*: fceff810 vfmsl.f16 d31, s30, s0
+.*: fe5fe898 vfmsl.f16 d30, s31, s0\[1\]
+.*: fc6ff814 vfmal.f16 d31, s30, s8
+.*: fe4fe894 vfmal.f16 d30, s31, s8\[0\]
+.*: fceff814 vfmsl.f16 d31, s30, s8
+.*: fe5fe89c vfmsl.f16 d30, s31, s8\[1\]
+.*: fc6ff837 vfmal.f16 d31, s30, s15
+.*: fe4fe8b7 vfmal.f16 d30, s31, s15\[0\]
+.*: fceff837 vfmsl.f16 d31, s30, s15
+.*: fe5fe8bf vfmsl.f16 d30, s31, s15\[1\]
+.*: fc204850 vfmal.f16 q2, d0, d0
+.*: fe020850 vfmal.f16 q0, d2, d0\[0\]
+.*: fca04850 vfmsl.f16 q2, d0, d0
+.*: fe120878 vfmsl.f16 q0, d2, d0\[3\]
+.*: fc204857 vfmal.f16 q2, d0, d7
+.*: fe020857 vfmal.f16 q0, d2, d7\[0\]
+.*: fca04857 vfmsl.f16 q2, d0, d7
+.*: fe12087f vfmsl.f16 q0, d2, d7\[3\]
+.*: fc206850 vfmal.f16 q3, d0, d0
+.*: fe030850 vfmal.f16 q0, d3, d0\[0\]
+.*: fca06850 vfmsl.f16 q3, d0, d0
+.*: fe130878 vfmsl.f16 q0, d3, d0\[3\]
+.*: fc206857 vfmal.f16 q3, d0, d7
+.*: fe030857 vfmal.f16 q0, d3, d7\[0\]
+.*: fca06857 vfmsl.f16 q3, d0, d7
+.*: fe13087f vfmsl.f16 q0, d3, d7\[3\]
+.*: fc60a850 vfmal.f16 q13, d0, d0
+.*: fe0d0850 vfmal.f16 q0, d13, d0\[0\]
+.*: fce0a850 vfmsl.f16 q13, d0, d0
+.*: fe1d0878 vfmsl.f16 q0, d13, d0\[3\]
+.*: fc60a857 vfmal.f16 q13, d0, d7
+.*: fe0d0857 vfmal.f16 q0, d13, d7\[0\]
+.*: fce0a857 vfmsl.f16 q13, d0, d7
+.*: fe1d087f vfmsl.f16 q0, d13, d7\[3\]
+.*: fc214850 vfmal.f16 q2, d1, d0
+.*: fe022850 vfmal.f16 q1, d2, d0\[0\]
+.*: fca14850 vfmsl.f16 q2, d1, d0
+.*: fe122878 vfmsl.f16 q1, d2, d0\[3\]
+.*: fc214857 vfmal.f16 q2, d1, d7
+.*: fe022857 vfmal.f16 q1, d2, d7\[0\]
+.*: fca14857 vfmsl.f16 q2, d1, d7
+.*: fe12287f vfmsl.f16 q1, d2, d7\[3\]
+.*: fc216850 vfmal.f16 q3, d1, d0
+.*: fe032850 vfmal.f16 q1, d3, d0\[0\]
+.*: fca16850 vfmsl.f16 q3, d1, d0
+.*: fe132878 vfmsl.f16 q1, d3, d0\[3\]
+.*: fc216857 vfmal.f16 q3, d1, d7
+.*: fe032857 vfmal.f16 q1, d3, d7\[0\]
+.*: fca16857 vfmsl.f16 q3, d1, d7
+.*: fe13287f vfmsl.f16 q1, d3, d7\[3\]
+.*: fc61a850 vfmal.f16 q13, d1, d0
+.*: fe0d2850 vfmal.f16 q1, d13, d0\[0\]
+.*: fce1a850 vfmsl.f16 q13, d1, d0
+.*: fe1d2878 vfmsl.f16 q1, d13, d0\[3\]
+.*: fc61a857 vfmal.f16 q13, d1, d7
+.*: fe0d2857 vfmal.f16 q1, d13, d7\[0\]
+.*: fce1a857 vfmsl.f16 q13, d1, d7
+.*: fe1d287f vfmsl.f16 q1, d13, d7\[3\]
+.*: fc264850 vfmal.f16 q2, d6, d0
+.*: fe02c850 vfmal.f16 q6, d2, d0\[0\]
+.*: fca64850 vfmsl.f16 q2, d6, d0
+.*: fe12c878 vfmsl.f16 q6, d2, d0\[3\]
+.*: fc264857 vfmal.f16 q2, d6, d7
+.*: fe02c857 vfmal.f16 q6, d2, d7\[0\]
+.*: fca64857 vfmsl.f16 q2, d6, d7
+.*: fe12c87f vfmsl.f16 q6, d2, d7\[3\]
+.*: fc266850 vfmal.f16 q3, d6, d0
+.*: fe03c850 vfmal.f16 q6, d3, d0\[0\]
+.*: fca66850 vfmsl.f16 q3, d6, d0
+.*: fe13c878 vfmsl.f16 q6, d3, d0\[3\]
+.*: fc266857 vfmal.f16 q3, d6, d7
+.*: fe03c857 vfmal.f16 q6, d3, d7\[0\]
+.*: fca66857 vfmsl.f16 q3, d6, d7
+.*: fe13c87f vfmsl.f16 q6, d3, d7\[3\]
+.*: fc66a850 vfmal.f16 q13, d6, d0
+.*: fe0dc850 vfmal.f16 q6, d13, d0\[0\]
+.*: fce6a850 vfmsl.f16 q13, d6, d0
+.*: fe1dc878 vfmsl.f16 q6, d13, d0\[3\]
+.*: fc66a857 vfmal.f16 q13, d6, d7
+.*: fe0dc857 vfmal.f16 q6, d13, d7\[0\]
+.*: fce6a857 vfmsl.f16 q13, d6, d7
+.*: fe1dc87f vfmsl.f16 q6, d13, d7\[3\]
+.*: fc2f4850 vfmal.f16 q2, d15, d0
+.*: fe42e850 vfmal.f16 q15, d2, d0\[0\]
+.*: fcaf4850 vfmsl.f16 q2, d15, d0
+.*: fe52e878 vfmsl.f16 q15, d2, d0\[3\]
+.*: fc2f4857 vfmal.f16 q2, d15, d7
+.*: fe42e857 vfmal.f16 q15, d2, d7\[0\]
+.*: fcaf4857 vfmsl.f16 q2, d15, d7
+.*: fe52e87f vfmsl.f16 q15, d2, d7\[3\]
+.*: fc2f6850 vfmal.f16 q3, d15, d0
+.*: fe43e850 vfmal.f16 q15, d3, d0\[0\]
+.*: fcaf6850 vfmsl.f16 q3, d15, d0
+.*: fe53e878 vfmsl.f16 q15, d3, d0\[3\]
+.*: fc2f6857 vfmal.f16 q3, d15, d7
+.*: fe43e857 vfmal.f16 q15, d3, d7\[0\]
+.*: fcaf6857 vfmsl.f16 q3, d15, d7
+.*: fe53e87f vfmsl.f16 q15, d3, d7\[3\]
+.*: fc6fa850 vfmal.f16 q13, d15, d0
+.*: fe4de850 vfmal.f16 q15, d13, d0\[0\]
+.*: fcefa850 vfmsl.f16 q13, d15, d0
+.*: fe5de878 vfmsl.f16 q15, d13, d0\[3\]
+.*: fc6fa857 vfmal.f16 q13, d15, d7
+.*: fe4de857 vfmal.f16 q15, d13, d7\[0\]
+.*: fcefa857 vfmsl.f16 q13, d15, d7
+.*: fe5de87f vfmsl.f16 q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8_4-a-fp16.d b/gas/testsuite/gas/arm/armv8_4-a-fp16.d
new file mode 100644
index 0000000..efc8dcf
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_4-a-fp16.d
@@ -0,0 +1,249 @@
+#as: -march=armv8.4-a+fp16 -mfpu=neon-fp-armv8
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*: fc210810 vfmal.f16 d0, s2, s0
+.*: fe002810 vfmal.f16 d2, s0, s0\[0\]
+.*: fca10810 vfmsl.f16 d0, s2, s0
+.*: fe102818 vfmsl.f16 d2, s0, s0\[1\]
+.*: fc210814 vfmal.f16 d0, s2, s8
+.*: fe002814 vfmal.f16 d2, s0, s8\[0\]
+.*: fca10814 vfmsl.f16 d0, s2, s8
+.*: fe10281c vfmsl.f16 d2, s0, s8\[1\]
+.*: fc210837 vfmal.f16 d0, s2, s15
+.*: fe002837 vfmal.f16 d2, s0, s15\[0\]
+.*: fca10837 vfmsl.f16 d0, s2, s15
+.*: fe10283f vfmsl.f16 d2, s0, s15\[1\]
+.*: fc270890 vfmal.f16 d0, s15, s0
+.*: fe00f810 vfmal.f16 d15, s0, s0\[0\]
+.*: fca70890 vfmsl.f16 d0, s15, s0
+.*: fe10f818 vfmsl.f16 d15, s0, s0\[1\]
+.*: fc270894 vfmal.f16 d0, s15, s8
+.*: fe00f814 vfmal.f16 d15, s0, s8\[0\]
+.*: fca70894 vfmsl.f16 d0, s15, s8
+.*: fe10f81c vfmsl.f16 d15, s0, s8\[1\]
+.*: fc2708b7 vfmal.f16 d0, s15, s15
+.*: fe00f837 vfmal.f16 d15, s0, s15\[0\]
+.*: fca708b7 vfmsl.f16 d0, s15, s15
+.*: fe10f83f vfmsl.f16 d15, s0, s15\[1\]
+.*: fc2f0810 vfmal.f16 d0, s30, s0
+.*: fe40e810 vfmal.f16 d30, s0, s0\[0\]
+.*: fcaf0810 vfmsl.f16 d0, s30, s0
+.*: fe50e818 vfmsl.f16 d30, s0, s0\[1\]
+.*: fc2f0814 vfmal.f16 d0, s30, s8
+.*: fe40e814 vfmal.f16 d30, s0, s8\[0\]
+.*: fcaf0814 vfmsl.f16 d0, s30, s8
+.*: fe50e81c vfmsl.f16 d30, s0, s8\[1\]
+.*: fc2f0837 vfmal.f16 d0, s30, s15
+.*: fe40e837 vfmal.f16 d30, s0, s15\[0\]
+.*: fcaf0837 vfmsl.f16 d0, s30, s15
+.*: fe50e83f vfmsl.f16 d30, s0, s15\[1\]
+.*: fc217810 vfmal.f16 d7, s2, s0
+.*: fe032890 vfmal.f16 d2, s7, s0\[0\]
+.*: fca17810 vfmsl.f16 d7, s2, s0
+.*: fe132898 vfmsl.f16 d2, s7, s0\[1\]
+.*: fc217814 vfmal.f16 d7, s2, s8
+.*: fe032894 vfmal.f16 d2, s7, s8\[0\]
+.*: fca17814 vfmsl.f16 d7, s2, s8
+.*: fe13289c vfmsl.f16 d2, s7, s8\[1\]
+.*: fc217837 vfmal.f16 d7, s2, s15
+.*: fe0328b7 vfmal.f16 d2, s7, s15\[0\]
+.*: fca17837 vfmsl.f16 d7, s2, s15
+.*: fe1328bf vfmsl.f16 d2, s7, s15\[1\]
+.*: fc277890 vfmal.f16 d7, s15, s0
+.*: fe03f890 vfmal.f16 d15, s7, s0\[0\]
+.*: fca77890 vfmsl.f16 d7, s15, s0
+.*: fe13f898 vfmsl.f16 d15, s7, s0\[1\]
+.*: fc277894 vfmal.f16 d7, s15, s8
+.*: fe03f894 vfmal.f16 d15, s7, s8\[0\]
+.*: fca77894 vfmsl.f16 d7, s15, s8
+.*: fe13f89c vfmsl.f16 d15, s7, s8\[1\]
+.*: fc2778b7 vfmal.f16 d7, s15, s15
+.*: fe03f8b7 vfmal.f16 d15, s7, s15\[0\]
+.*: fca778b7 vfmsl.f16 d7, s15, s15
+.*: fe13f8bf vfmsl.f16 d15, s7, s15\[1\]
+.*: fc2f7810 vfmal.f16 d7, s30, s0
+.*: fe43e890 vfmal.f16 d30, s7, s0\[0\]
+.*: fcaf7810 vfmsl.f16 d7, s30, s0
+.*: fe53e898 vfmsl.f16 d30, s7, s0\[1\]
+.*: fc2f7814 vfmal.f16 d7, s30, s8
+.*: fe43e894 vfmal.f16 d30, s7, s8\[0\]
+.*: fcaf7814 vfmsl.f16 d7, s30, s8
+.*: fe53e89c vfmsl.f16 d30, s7, s8\[1\]
+.*: fc2f7837 vfmal.f16 d7, s30, s15
+.*: fe43e8b7 vfmal.f16 d30, s7, s15\[0\]
+.*: fcaf7837 vfmsl.f16 d7, s30, s15
+.*: fe53e8bf vfmsl.f16 d30, s7, s15\[1\]
+.*: fc610810 vfmal.f16 d16, s2, s0
+.*: fe082810 vfmal.f16 d2, s16, s0\[0\]
+.*: fce10810 vfmsl.f16 d16, s2, s0
+.*: fe182818 vfmsl.f16 d2, s16, s0\[1\]
+.*: fc610814 vfmal.f16 d16, s2, s8
+.*: fe082814 vfmal.f16 d2, s16, s8\[0\]
+.*: fce10814 vfmsl.f16 d16, s2, s8
+.*: fe18281c vfmsl.f16 d2, s16, s8\[1\]
+.*: fc610837 vfmal.f16 d16, s2, s15
+.*: fe082837 vfmal.f16 d2, s16, s15\[0\]
+.*: fce10837 vfmsl.f16 d16, s2, s15
+.*: fe18283f vfmsl.f16 d2, s16, s15\[1\]
+.*: fc670890 vfmal.f16 d16, s15, s0
+.*: fe08f810 vfmal.f16 d15, s16, s0\[0\]
+.*: fce70890 vfmsl.f16 d16, s15, s0
+.*: fe18f818 vfmsl.f16 d15, s16, s0\[1\]
+.*: fc670894 vfmal.f16 d16, s15, s8
+.*: fe08f814 vfmal.f16 d15, s16, s8\[0\]
+.*: fce70894 vfmsl.f16 d16, s15, s8
+.*: fe18f81c vfmsl.f16 d15, s16, s8\[1\]
+.*: fc6708b7 vfmal.f16 d16, s15, s15
+.*: fe08f837 vfmal.f16 d15, s16, s15\[0\]
+.*: fce708b7 vfmsl.f16 d16, s15, s15
+.*: fe18f83f vfmsl.f16 d15, s16, s15\[1\]
+.*: fc6f0810 vfmal.f16 d16, s30, s0
+.*: fe48e810 vfmal.f16 d30, s16, s0\[0\]
+.*: fcef0810 vfmsl.f16 d16, s30, s0
+.*: fe58e818 vfmsl.f16 d30, s16, s0\[1\]
+.*: fc6f0814 vfmal.f16 d16, s30, s8
+.*: fe48e814 vfmal.f16 d30, s16, s8\[0\]
+.*: fcef0814 vfmsl.f16 d16, s30, s8
+.*: fe58e81c vfmsl.f16 d30, s16, s8\[1\]
+.*: fc6f0837 vfmal.f16 d16, s30, s15
+.*: fe48e837 vfmal.f16 d30, s16, s15\[0\]
+.*: fcef0837 vfmsl.f16 d16, s30, s15
+.*: fe58e83f vfmsl.f16 d30, s16, s15\[1\]
+.*: fc61f810 vfmal.f16 d31, s2, s0
+.*: fe0f2890 vfmal.f16 d2, s31, s0\[0\]
+.*: fce1f810 vfmsl.f16 d31, s2, s0
+.*: fe1f2898 vfmsl.f16 d2, s31, s0\[1\]
+.*: fc61f814 vfmal.f16 d31, s2, s8
+.*: fe0f2894 vfmal.f16 d2, s31, s8\[0\]
+.*: fce1f814 vfmsl.f16 d31, s2, s8
+.*: fe1f289c vfmsl.f16 d2, s31, s8\[1\]
+.*: fc61f837 vfmal.f16 d31, s2, s15
+.*: fe0f28b7 vfmal.f16 d2, s31, s15\[0\]
+.*: fce1f837 vfmsl.f16 d31, s2, s15
+.*: fe1f28bf vfmsl.f16 d2, s31, s15\[1\]
+.*: fc67f890 vfmal.f16 d31, s15, s0
+.*: fe0ff890 vfmal.f16 d15, s31, s0\[0\]
+.*: fce7f890 vfmsl.f16 d31, s15, s0
+.*: fe1ff898 vfmsl.f16 d15, s31, s0\[1\]
+.*: fc67f894 vfmal.f16 d31, s15, s8
+.*: fe0ff894 vfmal.f16 d15, s31, s8\[0\]
+.*: fce7f894 vfmsl.f16 d31, s15, s8
+.*: fe1ff89c vfmsl.f16 d15, s31, s8\[1\]
+.*: fc67f8b7 vfmal.f16 d31, s15, s15
+.*: fe0ff8b7 vfmal.f16 d15, s31, s15\[0\]
+.*: fce7f8b7 vfmsl.f16 d31, s15, s15
+.*: fe1ff8bf vfmsl.f16 d15, s31, s15\[1\]
+.*: fc6ff810 vfmal.f16 d31, s30, s0
+.*: fe4fe890 vfmal.f16 d30, s31, s0\[0\]
+.*: fceff810 vfmsl.f16 d31, s30, s0
+.*: fe5fe898 vfmsl.f16 d30, s31, s0\[1\]
+.*: fc6ff814 vfmal.f16 d31, s30, s8
+.*: fe4fe894 vfmal.f16 d30, s31, s8\[0\]
+.*: fceff814 vfmsl.f16 d31, s30, s8
+.*: fe5fe89c vfmsl.f16 d30, s31, s8\[1\]
+.*: fc6ff837 vfmal.f16 d31, s30, s15
+.*: fe4fe8b7 vfmal.f16 d30, s31, s15\[0\]
+.*: fceff837 vfmsl.f16 d31, s30, s15
+.*: fe5fe8bf vfmsl.f16 d30, s31, s15\[1\]
+.*: fc204850 vfmal.f16 q2, d0, d0
+.*: fe020850 vfmal.f16 q0, d2, d0\[0\]
+.*: fca04850 vfmsl.f16 q2, d0, d0
+.*: fe120878 vfmsl.f16 q0, d2, d0\[3\]
+.*: fc204857 vfmal.f16 q2, d0, d7
+.*: fe020857 vfmal.f16 q0, d2, d7\[0\]
+.*: fca04857 vfmsl.f16 q2, d0, d7
+.*: fe12087f vfmsl.f16 q0, d2, d7\[3\]
+.*: fc206850 vfmal.f16 q3, d0, d0
+.*: fe030850 vfmal.f16 q0, d3, d0\[0\]
+.*: fca06850 vfmsl.f16 q3, d0, d0
+.*: fe130878 vfmsl.f16 q0, d3, d0\[3\]
+.*: fc206857 vfmal.f16 q3, d0, d7
+.*: fe030857 vfmal.f16 q0, d3, d7\[0\]
+.*: fca06857 vfmsl.f16 q3, d0, d7
+.*: fe13087f vfmsl.f16 q0, d3, d7\[3\]
+.*: fc60a850 vfmal.f16 q13, d0, d0
+.*: fe0d0850 vfmal.f16 q0, d13, d0\[0\]
+.*: fce0a850 vfmsl.f16 q13, d0, d0
+.*: fe1d0878 vfmsl.f16 q0, d13, d0\[3\]
+.*: fc60a857 vfmal.f16 q13, d0, d7
+.*: fe0d0857 vfmal.f16 q0, d13, d7\[0\]
+.*: fce0a857 vfmsl.f16 q13, d0, d7
+.*: fe1d087f vfmsl.f16 q0, d13, d7\[3\]
+.*: fc214850 vfmal.f16 q2, d1, d0
+.*: fe022850 vfmal.f16 q1, d2, d0\[0\]
+.*: fca14850 vfmsl.f16 q2, d1, d0
+.*: fe122878 vfmsl.f16 q1, d2, d0\[3\]
+.*: fc214857 vfmal.f16 q2, d1, d7
+.*: fe022857 vfmal.f16 q1, d2, d7\[0\]
+.*: fca14857 vfmsl.f16 q2, d1, d7
+.*: fe12287f vfmsl.f16 q1, d2, d7\[3\]
+.*: fc216850 vfmal.f16 q3, d1, d0
+.*: fe032850 vfmal.f16 q1, d3, d0\[0\]
+.*: fca16850 vfmsl.f16 q3, d1, d0
+.*: fe132878 vfmsl.f16 q1, d3, d0\[3\]
+.*: fc216857 vfmal.f16 q3, d1, d7
+.*: fe032857 vfmal.f16 q1, d3, d7\[0\]
+.*: fca16857 vfmsl.f16 q3, d1, d7
+.*: fe13287f vfmsl.f16 q1, d3, d7\[3\]
+.*: fc61a850 vfmal.f16 q13, d1, d0
+.*: fe0d2850 vfmal.f16 q1, d13, d0\[0\]
+.*: fce1a850 vfmsl.f16 q13, d1, d0
+.*: fe1d2878 vfmsl.f16 q1, d13, d0\[3\]
+.*: fc61a857 vfmal.f16 q13, d1, d7
+.*: fe0d2857 vfmal.f16 q1, d13, d7\[0\]
+.*: fce1a857 vfmsl.f16 q13, d1, d7
+.*: fe1d287f vfmsl.f16 q1, d13, d7\[3\]
+.*: fc264850 vfmal.f16 q2, d6, d0
+.*: fe02c850 vfmal.f16 q6, d2, d0\[0\]
+.*: fca64850 vfmsl.f16 q2, d6, d0
+.*: fe12c878 vfmsl.f16 q6, d2, d0\[3\]
+.*: fc264857 vfmal.f16 q2, d6, d7
+.*: fe02c857 vfmal.f16 q6, d2, d7\[0\]
+.*: fca64857 vfmsl.f16 q2, d6, d7
+.*: fe12c87f vfmsl.f16 q6, d2, d7\[3\]
+.*: fc266850 vfmal.f16 q3, d6, d0
+.*: fe03c850 vfmal.f16 q6, d3, d0\[0\]
+.*: fca66850 vfmsl.f16 q3, d6, d0
+.*: fe13c878 vfmsl.f16 q6, d3, d0\[3\]
+.*: fc266857 vfmal.f16 q3, d6, d7
+.*: fe03c857 vfmal.f16 q6, d3, d7\[0\]
+.*: fca66857 vfmsl.f16 q3, d6, d7
+.*: fe13c87f vfmsl.f16 q6, d3, d7\[3\]
+.*: fc66a850 vfmal.f16 q13, d6, d0
+.*: fe0dc850 vfmal.f16 q6, d13, d0\[0\]
+.*: fce6a850 vfmsl.f16 q13, d6, d0
+.*: fe1dc878 vfmsl.f16 q6, d13, d0\[3\]
+.*: fc66a857 vfmal.f16 q13, d6, d7
+.*: fe0dc857 vfmal.f16 q6, d13, d7\[0\]
+.*: fce6a857 vfmsl.f16 q13, d6, d7
+.*: fe1dc87f vfmsl.f16 q6, d13, d7\[3\]
+.*: fc2f4850 vfmal.f16 q2, d15, d0
+.*: fe42e850 vfmal.f16 q15, d2, d0\[0\]
+.*: fcaf4850 vfmsl.f16 q2, d15, d0
+.*: fe52e878 vfmsl.f16 q15, d2, d0\[3\]
+.*: fc2f4857 vfmal.f16 q2, d15, d7
+.*: fe42e857 vfmal.f16 q15, d2, d7\[0\]
+.*: fcaf4857 vfmsl.f16 q2, d15, d7
+.*: fe52e87f vfmsl.f16 q15, d2, d7\[3\]
+.*: fc2f6850 vfmal.f16 q3, d15, d0
+.*: fe43e850 vfmal.f16 q15, d3, d0\[0\]
+.*: fcaf6850 vfmsl.f16 q3, d15, d0
+.*: fe53e878 vfmsl.f16 q15, d3, d0\[3\]
+.*: fc2f6857 vfmal.f16 q3, d15, d7
+.*: fe43e857 vfmal.f16 q15, d3, d7\[0\]
+.*: fcaf6857 vfmsl.f16 q3, d15, d7
+.*: fe53e87f vfmsl.f16 q15, d3, d7\[3\]
+.*: fc6fa850 vfmal.f16 q13, d15, d0
+.*: fe4de850 vfmal.f16 q15, d13, d0\[0\]
+.*: fcefa850 vfmsl.f16 q13, d15, d0
+.*: fe5de878 vfmsl.f16 q15, d13, d0\[3\]
+.*: fc6fa857 vfmal.f16 q13, d15, d7
+.*: fe4de857 vfmal.f16 q15, d13, d7\[0\]
+.*: fcefa857 vfmsl.f16 q13, d15, d7
+.*: fe5de87f vfmsl.f16 q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/dotprod-mandatory.d b/gas/testsuite/gas/arm/dotprod-mandatory.d
new file mode 100644
index 0000000..9f85e0e
--- /dev/null
+++ b/gas/testsuite/gas/arm/dotprod-mandatory.d
@@ -0,0 +1,297 @@
+#as: -march=armv8.4-a -mfpu=neon-fp-armv8
+#source: dotprod.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*: fc220d10 vudot.u8 d0, d2, d0
+.*: fe220d10 vudot.u8 d0, d2, d0\[0\]
+.*: fc220d18 vudot.u8 d0, d2, d8
+.*: fe220d18 vudot.u8 d0, d2, d8\[0\]
+.*: fc220d1f vudot.u8 d0, d2, d15
+.*: fe220d1f vudot.u8 d0, d2, d15\[0\]
+.*: fc2f0d10 vudot.u8 d0, d15, d0
+.*: fe2f0d10 vudot.u8 d0, d15, d0\[0\]
+.*: fc2f0d18 vudot.u8 d0, d15, d8
+.*: fe2f0d18 vudot.u8 d0, d15, d8\[0\]
+.*: fc2f0d1f vudot.u8 d0, d15, d15
+.*: fe2f0d1f vudot.u8 d0, d15, d15\[0\]
+.*: fc2e0d90 vudot.u8 d0, d30, d0
+.*: fe2e0d90 vudot.u8 d0, d30, d0\[0\]
+.*: fc2e0d98 vudot.u8 d0, d30, d8
+.*: fe2e0d98 vudot.u8 d0, d30, d8\[0\]
+.*: fc2e0d9f vudot.u8 d0, d30, d15
+.*: fe2e0d9f vudot.u8 d0, d30, d15\[0\]
+.*: fc227d10 vudot.u8 d7, d2, d0
+.*: fe227d10 vudot.u8 d7, d2, d0\[0\]
+.*: fc227d18 vudot.u8 d7, d2, d8
+.*: fe227d18 vudot.u8 d7, d2, d8\[0\]
+.*: fc227d1f vudot.u8 d7, d2, d15
+.*: fe227d1f vudot.u8 d7, d2, d15\[0\]
+.*: fc2f7d10 vudot.u8 d7, d15, d0
+.*: fe2f7d10 vudot.u8 d7, d15, d0\[0\]
+.*: fc2f7d18 vudot.u8 d7, d15, d8
+.*: fe2f7d18 vudot.u8 d7, d15, d8\[0\]
+.*: fc2f7d1f vudot.u8 d7, d15, d15
+.*: fe2f7d1f vudot.u8 d7, d15, d15\[0\]
+.*: fc2e7d90 vudot.u8 d7, d30, d0
+.*: fe2e7d90 vudot.u8 d7, d30, d0\[0\]
+.*: fc2e7d98 vudot.u8 d7, d30, d8
+.*: fe2e7d98 vudot.u8 d7, d30, d8\[0\]
+.*: fc2e7d9f vudot.u8 d7, d30, d15
+.*: fe2e7d9f vudot.u8 d7, d30, d15\[0\]
+.*: fc620d10 vudot.u8 d16, d2, d0
+.*: fe620d10 vudot.u8 d16, d2, d0\[0\]
+.*: fc620d18 vudot.u8 d16, d2, d8
+.*: fe620d18 vudot.u8 d16, d2, d8\[0\]
+.*: fc620d1f vudot.u8 d16, d2, d15
+.*: fe620d1f vudot.u8 d16, d2, d15\[0\]
+.*: fc6f0d10 vudot.u8 d16, d15, d0
+.*: fe6f0d10 vudot.u8 d16, d15, d0\[0\]
+.*: fc6f0d18 vudot.u8 d16, d15, d8
+.*: fe6f0d18 vudot.u8 d16, d15, d8\[0\]
+.*: fc6f0d1f vudot.u8 d16, d15, d15
+.*: fe6f0d1f vudot.u8 d16, d15, d15\[0\]
+.*: fc6e0d90 vudot.u8 d16, d30, d0
+.*: fe6e0d90 vudot.u8 d16, d30, d0\[0\]
+.*: fc6e0d98 vudot.u8 d16, d30, d8
+.*: fe6e0d98 vudot.u8 d16, d30, d8\[0\]
+.*: fc6e0d9f vudot.u8 d16, d30, d15
+.*: fe6e0d9f vudot.u8 d16, d30, d15\[0\]
+.*: fc62fd10 vudot.u8 d31, d2, d0
+.*: fe62fd10 vudot.u8 d31, d2, d0\[0\]
+.*: fc62fd18 vudot.u8 d31, d2, d8
+.*: fe62fd18 vudot.u8 d31, d2, d8\[0\]
+.*: fc62fd1f vudot.u8 d31, d2, d15
+.*: fe62fd1f vudot.u8 d31, d2, d15\[0\]
+.*: fc6ffd10 vudot.u8 d31, d15, d0
+.*: fe6ffd10 vudot.u8 d31, d15, d0\[0\]
+.*: fc6ffd18 vudot.u8 d31, d15, d8
+.*: fe6ffd18 vudot.u8 d31, d15, d8\[0\]
+.*: fc6ffd1f vudot.u8 d31, d15, d15
+.*: fe6ffd1f vudot.u8 d31, d15, d15\[0\]
+.*: fc6efd90 vudot.u8 d31, d30, d0
+.*: fe6efd90 vudot.u8 d31, d30, d0\[0\]
+.*: fc6efd98 vudot.u8 d31, d30, d8
+.*: fe6efd98 vudot.u8 d31, d30, d8\[0\]
+.*: fc6efd9f vudot.u8 d31, d30, d15
+.*: fe6efd9f vudot.u8 d31, d30, d15\[0\]
+.*: fc220d00 vsdot.s8 d0, d2, d0
+.*: fe220d00 vsdot.s8 d0, d2, d0\[0\]
+.*: fc220d08 vsdot.s8 d0, d2, d8
+.*: fe220d08 vsdot.s8 d0, d2, d8\[0\]
+.*: fc220d0f vsdot.s8 d0, d2, d15
+.*: fe220d0f vsdot.s8 d0, d2, d15\[0\]
+.*: fc2f0d00 vsdot.s8 d0, d15, d0
+.*: fe2f0d00 vsdot.s8 d0, d15, d0\[0\]
+.*: fc2f0d08 vsdot.s8 d0, d15, d8
+.*: fe2f0d08 vsdot.s8 d0, d15, d8\[0\]
+.*: fc2f0d0f vsdot.s8 d0, d15, d15
+.*: fe2f0d0f vsdot.s8 d0, d15, d15\[0\]
+.*: fc2e0d80 vsdot.s8 d0, d30, d0
+.*: fe2e0d80 vsdot.s8 d0, d30, d0\[0\]
+.*: fc2e0d88 vsdot.s8 d0, d30, d8
+.*: fe2e0d88 vsdot.s8 d0, d30, d8\[0\]
+.*: fc2e0d8f vsdot.s8 d0, d30, d15
+.*: fe2e0d8f vsdot.s8 d0, d30, d15\[0\]
+.*: fc227d00 vsdot.s8 d7, d2, d0
+.*: fe227d00 vsdot.s8 d7, d2, d0\[0\]
+.*: fc227d08 vsdot.s8 d7, d2, d8
+.*: fe227d08 vsdot.s8 d7, d2, d8\[0\]
+.*: fc227d0f vsdot.s8 d7, d2, d15
+.*: fe227d0f vsdot.s8 d7, d2, d15\[0\]
+.*: fc2f7d00 vsdot.s8 d7, d15, d0
+.*: fe2f7d00 vsdot.s8 d7, d15, d0\[0\]
+.*: fc2f7d08 vsdot.s8 d7, d15, d8
+.*: fe2f7d08 vsdot.s8 d7, d15, d8\[0\]
+.*: fc2f7d0f vsdot.s8 d7, d15, d15
+.*: fe2f7d0f vsdot.s8 d7, d15, d15\[0\]
+.*: fc2e7d80 vsdot.s8 d7, d30, d0
+.*: fe2e7d80 vsdot.s8 d7, d30, d0\[0\]
+.*: fc2e7d88 vsdot.s8 d7, d30, d8
+.*: fe2e7d88 vsdot.s8 d7, d30, d8\[0\]
+.*: fc2e7d8f vsdot.s8 d7, d30, d15
+.*: fe2e7d8f vsdot.s8 d7, d30, d15\[0\]
+.*: fc620d00 vsdot.s8 d16, d2, d0
+.*: fe620d00 vsdot.s8 d16, d2, d0\[0\]
+.*: fc620d08 vsdot.s8 d16, d2, d8
+.*: fe620d08 vsdot.s8 d16, d2, d8\[0\]
+.*: fc620d0f vsdot.s8 d16, d2, d15
+.*: fe620d0f vsdot.s8 d16, d2, d15\[0\]
+.*: fc6f0d00 vsdot.s8 d16, d15, d0
+.*: fe6f0d00 vsdot.s8 d16, d15, d0\[0\]
+.*: fc6f0d08 vsdot.s8 d16, d15, d8
+.*: fe6f0d08 vsdot.s8 d16, d15, d8\[0\]
+.*: fc6f0d0f vsdot.s8 d16, d15, d15
+.*: fe6f0d0f vsdot.s8 d16, d15, d15\[0\]
+.*: fc6e0d80 vsdot.s8 d16, d30, d0
+.*: fe6e0d80 vsdot.s8 d16, d30, d0\[0\]
+.*: fc6e0d88 vsdot.s8 d16, d30, d8
+.*: fe6e0d88 vsdot.s8 d16, d30, d8\[0\]
+.*: fc6e0d8f vsdot.s8 d16, d30, d15
+.*: fe6e0d8f vsdot.s8 d16, d30, d15\[0\]
+.*: fc62fd00 vsdot.s8 d31, d2, d0
+.*: fe62fd00 vsdot.s8 d31, d2, d0\[0\]
+.*: fc62fd08 vsdot.s8 d31, d2, d8
+.*: fe62fd08 vsdot.s8 d31, d2, d8\[0\]
+.*: fc62fd0f vsdot.s8 d31, d2, d15
+.*: fe62fd0f vsdot.s8 d31, d2, d15\[0\]
+.*: fc6ffd00 vsdot.s8 d31, d15, d0
+.*: fe6ffd00 vsdot.s8 d31, d15, d0\[0\]
+.*: fc6ffd08 vsdot.s8 d31, d15, d8
+.*: fe6ffd08 vsdot.s8 d31, d15, d8\[0\]
+.*: fc6ffd0f vsdot.s8 d31, d15, d15
+.*: fe6ffd0f vsdot.s8 d31, d15, d15\[0\]
+.*: fc6efd80 vsdot.s8 d31, d30, d0
+.*: fe6efd80 vsdot.s8 d31, d30, d0\[0\]
+.*: fc6efd88 vsdot.s8 d31, d30, d8
+.*: fe6efd88 vsdot.s8 d31, d30, d8\[0\]
+.*: fc6efd8f vsdot.s8 d31, d30, d15
+.*: fe6efd8f vsdot.s8 d31, d30, d15\[0\]
+.*: fc240d50 vudot.u8 q0, q2, q0
+.*: fe240d70 vudot.u8 q0, q2, d0\[1\]
+.*: fc240d5e vudot.u8 q0, q2, q7
+.*: fe240d77 vudot.u8 q0, q2, d7\[1\]
+.*: fc240d7e vudot.u8 q0, q2, q15
+.*: fe240d7f vudot.u8 q0, q2, d15\[1\]
+.*: fc260d50 vudot.u8 q0, q3, q0
+.*: fe260d70 vudot.u8 q0, q3, d0\[1\]
+.*: fc260d5e vudot.u8 q0, q3, q7
+.*: fe260d77 vudot.u8 q0, q3, d7\[1\]
+.*: fc260d7e vudot.u8 q0, q3, q15
+.*: fe260d7f vudot.u8 q0, q3, d15\[1\]
+.*: fc2c0dd0 vudot.u8 q0, q14, q0
+.*: fe2c0df0 vudot.u8 q0, q14, d0\[1\]
+.*: fc2c0dde vudot.u8 q0, q14, q7
+.*: fe2c0df7 vudot.u8 q0, q14, d7\[1\]
+.*: fc2c0dfe vudot.u8 q0, q14, q15
+.*: fe2c0dff vudot.u8 q0, q14, d15\[1\]
+.*: fc242d50 vudot.u8 q1, q2, q0
+.*: fe242d70 vudot.u8 q1, q2, d0\[1\]
+.*: fc242d5e vudot.u8 q1, q2, q7
+.*: fe242d77 vudot.u8 q1, q2, d7\[1\]
+.*: fc242d7e vudot.u8 q1, q2, q15
+.*: fe242d7f vudot.u8 q1, q2, d15\[1\]
+.*: fc262d50 vudot.u8 q1, q3, q0
+.*: fe262d70 vudot.u8 q1, q3, d0\[1\]
+.*: fc262d5e vudot.u8 q1, q3, q7
+.*: fe262d77 vudot.u8 q1, q3, d7\[1\]
+.*: fc262d7e vudot.u8 q1, q3, q15
+.*: fe262d7f vudot.u8 q1, q3, d15\[1\]
+.*: fc2c2dd0 vudot.u8 q1, q14, q0
+.*: fe2c2df0 vudot.u8 q1, q14, d0\[1\]
+.*: fc2c2dde vudot.u8 q1, q14, q7
+.*: fe2c2df7 vudot.u8 q1, q14, d7\[1\]
+.*: fc2c2dfe vudot.u8 q1, q14, q15
+.*: fe2c2dff vudot.u8 q1, q14, d15\[1\]
+.*: fc24cd50 vudot.u8 q6, q2, q0
+.*: fe24cd70 vudot.u8 q6, q2, d0\[1\]
+.*: fc24cd5e vudot.u8 q6, q2, q7
+.*: fe24cd77 vudot.u8 q6, q2, d7\[1\]
+.*: fc24cd7e vudot.u8 q6, q2, q15
+.*: fe24cd7f vudot.u8 q6, q2, d15\[1\]
+.*: fc26cd50 vudot.u8 q6, q3, q0
+.*: fe26cd70 vudot.u8 q6, q3, d0\[1\]
+.*: fc26cd5e vudot.u8 q6, q3, q7
+.*: fe26cd77 vudot.u8 q6, q3, d7\[1\]
+.*: fc26cd7e vudot.u8 q6, q3, q15
+.*: fe26cd7f vudot.u8 q6, q3, d15\[1\]
+.*: fc2ccdd0 vudot.u8 q6, q14, q0
+.*: fe2ccdf0 vudot.u8 q6, q14, d0\[1\]
+.*: fc2ccdde vudot.u8 q6, q14, q7
+.*: fe2ccdf7 vudot.u8 q6, q14, d7\[1\]
+.*: fc2ccdfe vudot.u8 q6, q14, q15
+.*: fe2ccdff vudot.u8 q6, q14, d15\[1\]
+.*: fc64ad50 vudot.u8 q13, q2, q0
+.*: fe64ad70 vudot.u8 q13, q2, d0\[1\]
+.*: fc64ad5e vudot.u8 q13, q2, q7
+.*: fe64ad77 vudot.u8 q13, q2, d7\[1\]
+.*: fc64ad7e vudot.u8 q13, q2, q15
+.*: fe64ad7f vudot.u8 q13, q2, d15\[1\]
+.*: fc66ad50 vudot.u8 q13, q3, q0
+.*: fe66ad70 vudot.u8 q13, q3, d0\[1\]
+.*: fc66ad5e vudot.u8 q13, q3, q7
+.*: fe66ad77 vudot.u8 q13, q3, d7\[1\]
+.*: fc66ad7e vudot.u8 q13, q3, q15
+.*: fe66ad7f vudot.u8 q13, q3, d15\[1\]
+.*: fc6cadd0 vudot.u8 q13, q14, q0
+.*: fe6cadf0 vudot.u8 q13, q14, d0\[1\]
+.*: fc6cadde vudot.u8 q13, q14, q7
+.*: fe6cadf7 vudot.u8 q13, q14, d7\[1\]
+.*: fc6cadfe vudot.u8 q13, q14, q15
+.*: fe6cadff vudot.u8 q13, q14, d15\[1\]
+.*: fc240d40 vsdot.s8 q0, q2, q0
+.*: fe240d60 vsdot.s8 q0, q2, d0\[1\]
+.*: fc240d4e vsdot.s8 q0, q2, q7
+.*: fe240d67 vsdot.s8 q0, q2, d7\[1\]
+.*: fc240d6e vsdot.s8 q0, q2, q15
+.*: fe240d6f vsdot.s8 q0, q2, d15\[1\]
+.*: fc260d40 vsdot.s8 q0, q3, q0
+.*: fe260d60 vsdot.s8 q0, q3, d0\[1\]
+.*: fc260d4e vsdot.s8 q0, q3, q7
+.*: fe260d67 vsdot.s8 q0, q3, d7\[1\]
+.*: fc260d6e vsdot.s8 q0, q3, q15
+.*: fe260d6f vsdot.s8 q0, q3, d15\[1\]
+.*: fc2c0dc0 vsdot.s8 q0, q14, q0
+.*: fe2c0de0 vsdot.s8 q0, q14, d0\[1\]
+.*: fc2c0dce vsdot.s8 q0, q14, q7
+.*: fe2c0de7 vsdot.s8 q0, q14, d7\[1\]
+.*: fc2c0dee vsdot.s8 q0, q14, q15
+.*: fe2c0def vsdot.s8 q0, q14, d15\[1\]
+.*: fc242d40 vsdot.s8 q1, q2, q0
+.*: fe242d60 vsdot.s8 q1, q2, d0\[1\]
+.*: fc242d4e vsdot.s8 q1, q2, q7
+.*: fe242d67 vsdot.s8 q1, q2, d7\[1\]
+.*: fc242d6e vsdot.s8 q1, q2, q15
+.*: fe242d6f vsdot.s8 q1, q2, d15\[1\]
+.*: fc262d40 vsdot.s8 q1, q3, q0
+.*: fe262d60 vsdot.s8 q1, q3, d0\[1\]
+.*: fc262d4e vsdot.s8 q1, q3, q7
+.*: fe262d67 vsdot.s8 q1, q3, d7\[1\]
+.*: fc262d6e vsdot.s8 q1, q3, q15
+.*: fe262d6f vsdot.s8 q1, q3, d15\[1\]
+.*: fc2c2dc0 vsdot.s8 q1, q14, q0
+.*: fe2c2de0 vsdot.s8 q1, q14, d0\[1\]
+.*: fc2c2dce vsdot.s8 q1, q14, q7
+.*: fe2c2de7 vsdot.s8 q1, q14, d7\[1\]
+.*: fc2c2dee vsdot.s8 q1, q14, q15
+.*: fe2c2def vsdot.s8 q1, q14, d15\[1\]
+.*: fc24cd40 vsdot.s8 q6, q2, q0
+.*: fe24cd60 vsdot.s8 q6, q2, d0\[1\]
+.*: fc24cd4e vsdot.s8 q6, q2, q7
+.*: fe24cd67 vsdot.s8 q6, q2, d7\[1\]
+.*: fc24cd6e vsdot.s8 q6, q2, q15
+.*: fe24cd6f vsdot.s8 q6, q2, d15\[1\]
+.*: fc26cd40 vsdot.s8 q6, q3, q0
+.*: fe26cd60 vsdot.s8 q6, q3, d0\[1\]
+.*: fc26cd4e vsdot.s8 q6, q3, q7
+.*: fe26cd67 vsdot.s8 q6, q3, d7\[1\]
+.*: fc26cd6e vsdot.s8 q6, q3, q15
+.*: fe26cd6f vsdot.s8 q6, q3, d15\[1\]
+.*: fc2ccdc0 vsdot.s8 q6, q14, q0
+.*: fe2ccde0 vsdot.s8 q6, q14, d0\[1\]
+.*: fc2ccdce vsdot.s8 q6, q14, q7
+.*: fe2ccde7 vsdot.s8 q6, q14, d7\[1\]
+.*: fc2ccdee vsdot.s8 q6, q14, q15
+.*: fe2ccdef vsdot.s8 q6, q14, d15\[1\]
+.*: fc64ad40 vsdot.s8 q13, q2, q0
+.*: fe64ad60 vsdot.s8 q13, q2, d0\[1\]
+.*: fc64ad4e vsdot.s8 q13, q2, q7
+.*: fe64ad67 vsdot.s8 q13, q2, d7\[1\]
+.*: fc64ad6e vsdot.s8 q13, q2, q15
+.*: fe64ad6f vsdot.s8 q13, q2, d15\[1\]
+.*: fc66ad40 vsdot.s8 q13, q3, q0
+.*: fe66ad60 vsdot.s8 q13, q3, d0\[1\]
+.*: fc66ad4e vsdot.s8 q13, q3, q7
+.*: fe66ad67 vsdot.s8 q13, q3, d7\[1\]
+.*: fc66ad6e vsdot.s8 q13, q3, q15
+.*: fe66ad6f vsdot.s8 q13, q3, d15\[1\]
+.*: fc6cadc0 vsdot.s8 q13, q14, q0
+.*: fe6cade0 vsdot.s8 q13, q14, d0\[1\]
+.*: fc6cadce vsdot.s8 q13, q14, q7
+.*: fe6cade7 vsdot.s8 q13, q14, d7\[1\]
+.*: fc6cadee vsdot.s8 q13, q14, q15
+.*: fe6cadef vsdot.s8 q13, q14, d15\[1\]
diff --git a/include/ChangeLog b/include/ChangeLog
index beb08bb..36b1732 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,10 @@
+2017-11-08 Jiong Wang <jiong.wang@arm.com>
+
+ * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature.
+ (ARM_EXT2_V8_4A): New macro.
+ (ARM_AEXT2_V8_4A): Likewise.
+ (ARM_ARCH_V8_4A): Likewise.
+
2017-11-07 Palmer Dabbelt <palmer@dabbelt.com>
* opcode/riscv-opc.h (sptbr): Rename to satp.
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 3b51aba..932bf63 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -66,6 +66,7 @@
#define ARM_EXT2_RAS 0x00000080 /* RAS extension. */
#define ARM_EXT2_V8_3A 0x00000100 /* ARM V8.3A. */
#define ARM_EXT2_V8A 0x00000200 /* ARMv8-A. */
+#define ARM_EXT2_V8_4A 0x00000400 /* ARM V8.4A. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
@@ -156,6 +157,7 @@
#define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN)
#define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A | ARM_EXT2_RAS)
#define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A | ARM_EXT2_V8_3A)
+#define ARM_AEXT2_V8_4A (ARM_AEXT2_V8_3A | ARM_EXT2_V8_4A)
#define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV)
#define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M
#define ARM_AEXT_V8M_MAIN_DSP ARM_AEXT_V7EM
@@ -228,8 +230,8 @@
#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD \
- ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 | \
- FPU_NEON_EXT_DOTPROD)
+ ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \
+ | FPU_NEON_EXT_DOTPROD)
#define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
#define FPU_ARCH_NEON_VFP_ARMV8_1 \
ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
@@ -287,6 +289,9 @@
CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA)
#define ARM_ARCH_V8_3A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_3A, \
CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA)
+#define ARM_ARCH_V8_4A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_4A, \
+ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
+ | FPU_NEON_EXT_DOTPROD)
#define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M)
#define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \
ARM_AEXT2_V8M_MAIN)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 70f146f..7dcc29e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2017-11-08 Jiong Wang <jiong.wang@arm.com>
+ Tamar Christina <tamar.christina@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
+ FP16 instructions, including vfmal.f16 and vfmsl.f16.
+
2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
* arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 59a5978..d5a20cb 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -912,6 +912,24 @@ static const struct opcode32 coprocessor_opcodes[] =
{ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
+ /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
+
/* V5 coprocessor instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},