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[binutils-gdb] RISC-V: Change CALL macro to use ra as the temporary address register
- From: Palmer Dabbelt <palmer at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 2 May 2017 22:20:19 -0000
- Subject: [binutils-gdb] RISC-V: Change CALL macro to use ra as the temporary address register
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=43e379d74c994fe431368b5f25f778bf601a2981
commit 43e379d74c994fe431368b5f25f778bf601a2981
Author: Michael Clark <michaeljclark@mac.com>
Date: Thu Apr 27 16:08:46 2017 +1200
RISC-V: Change CALL macro to use ra as the temporary address register
e.g.
1: auipc ra, %pcrel_hi(symbol)
jalr ra, %pcrel_lo(1b)(ra)
The use of ra instead of t1 for address construction provides an
opportunity for a microarchitecture to elide the write of the
destination address, and instead read the target address as an
immediate spread across the fused auipc+jalr pair. The link
register ra in the jalr overwrites the target address temporary.
2017-05-01 Michael Clark <michaeljclark@mac.com>
* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
register.
Diff:
---
opcodes/ChangeLog | 5 +++++
opcodes/riscv-opc.c | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index dcde282..355a162 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-05-01 Michael Clark <michaeljclark@mac.com>
+
+ * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
+ register.
+
2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
* mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c629d2f..0188a65 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -147,7 +147,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS },
{"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
{"call", "I", "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
-{"call", "I", "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
+{"call", "I", "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
{"tail", "I", "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
{"jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO },
{"nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },