This is the mail archive of the
binutils-cvs@sourceware.org
mailing list for the binutils project.
[binutils-gdb/binutils-2_28-branch] Add SFENCE.VMA instruction
- From: Palmer Dabbelt <palmer at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 27 Feb 2017 17:44:22 -0000
- Subject: [binutils-gdb/binutils-2_28-branch] Add SFENCE.VMA instruction
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=af5d20642554531c9a97be594dd8da9ea5e69a18
commit af5d20642554531c9a97be594dd8da9ea5e69a18
Author: Andrew Waterman <andrew@sifive.com>
Date: Tue Feb 14 15:37:04 2017 -0800
Add SFENCE.VMA instruction
include/ChangeLog:
2017-02-14 Andrew Waterman <andrew@sifive.com>
* opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
(MASK_SFENCE_VMA): Likewise.
(sfence_vma): Declare instruction.
opcodes/ChangeLog:
2017-02-14 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
pseudoinstructions.
Diff:
---
include/ChangeLog | 6 ++++++
include/opcode/riscv-opc.h | 3 +++
opcodes/ChangeLog | 5 +++++
opcodes/riscv-opc.c | 3 +++
4 files changed, 17 insertions(+)
diff --git a/include/ChangeLog b/include/ChangeLog
index 4ca5de9..b5015b5 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,9 @@
+2017-02-14 Andrew Waterman <andrew@sifive.com>
+
+ * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
+ (MASK_SFENCE_VMA): Likewise.
+ (sfence_vma): Declare instruction.
+
2017-02-27 Richard Sandiford <richard.sandiford@arm.com>
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index d10c7f8..cef2f3c 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -227,6 +227,8 @@
#define MASK_DRET 0xffffffff
#define MATCH_SFENCE_VM 0x10400073
#define MASK_SFENCE_VM 0xfff07fff
+#define MATCH_SFENCE_VMA 0x12000073
+#define MASK_SFENCE_VMA 0xfe007fff
#define MATCH_WFI 0x10500073
#define MASK_WFI 0xffffffff
#define MATCH_CSRRW 0x1073
@@ -815,6 +817,7 @@ DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5327356..cd7476e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-02-14 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
+ pseudoinstructions.
+
2017-02-27 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0a6f36f..867a026 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -618,6 +618,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 },
{"sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
{"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
+{"sfence.vma","I", "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS1 | MASK_RS2, match_opcode, INSN_ALIAS },
+{"sfence.vma","I", "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS2, match_opcode, INSN_ALIAS },
+{"sfence.vma","I", "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
/* Terminate the list. */