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[binutils-gdb] MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership
- From: Maciej W.Rozycki <macro at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 20 Dec 2016 12:08:37 -0000
- Subject: [binutils-gdb] MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c97dda72b905d5ba9b82004bf4e57dd4cf343147
commit c97dda72b905d5ba9b82004bf4e57dd4cf343147
Author: Maciej W. Rozycki <macro@imgtec.com>
Date: Tue Dec 20 01:50:24 2016 +0000
MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership
Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor
opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit
instruction requiring a 64-bit ISA. This bug has been there since
forever.
opcodes/
* mips16-opc.c (mips16_opcodes): Set membership to I3 rather
than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
opcode).
gas/
* testsuite/gas/mips/mips16-sdrasp.d: New test.
* testsuite/gas/mips/mips16-sdrasp.l: New stderr output.
* testsuite/gas/mips/mips16-sdrasp.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Diff:
---
gas/ChangeLog | 7 +++++++
gas/testsuite/gas/mips/mips.exp | 1 +
gas/testsuite/gas/mips/mips16-sdrasp.d | 3 +++
gas/testsuite/gas/mips/mips16-sdrasp.l | 2 ++
gas/testsuite/gas/mips/mips16-sdrasp.s | 7 +++++++
opcodes/ChangeLog | 6 ++++++
opcodes/mips16-opc.c | 2 +-
7 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 571c776..1038be9 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+ * testsuite/gas/mips/mips16-sdrasp.d: New test.
+ * testsuite/gas/mips/mips16-sdrasp.l: New stderr output.
+ * testsuite/gas/mips/mips16-sdrasp.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
* testsuite/gas/mips/mips.exp: Limit remaining tests that
require NewABI support to `has_newabi' targets.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index a51c2a7..8b80200 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1313,6 +1313,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "mips16-intermix"
run_dump_test "mips16-extend"
run_dump_test "mips16-sprel-swap"
+ run_dump_test "mips16-sdrasp"
run_dump_test "mips16-branch-unextended-1"
run_dump_test "mips16-branch-unextended-2"
diff --git a/gas/testsuite/gas/mips/mips16-sdrasp.d b/gas/testsuite/gas/mips/mips16-sdrasp.d
new file mode 100644
index 0000000..f82e2c6
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-sdrasp.d
@@ -0,0 +1,3 @@
+#name: MIPS16 SDRASP opcode with 32-bit ISA
+#as: -32 -march=mips1
+#error-output: mips16-sdrasp.l
diff --git a/gas/testsuite/gas/mips/mips16-sdrasp.l b/gas/testsuite/gas/mips/mips16-sdrasp.l
new file mode 100644
index 0000000..3e90bdd
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-sdrasp.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*:3: Error: opcode not supported on this processor: mips1 \(mips1\) `sd \$31,0\(\$29\)'
diff --git a/gas/testsuite/gas/mips/mips16-sdrasp.s b/gas/testsuite/gas/mips/mips16-sdrasp.s
new file mode 100644
index 0000000..306deed
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-sdrasp.s
@@ -0,0 +1,7 @@
+ .set mips16
+foo:
+ sd $31, 0($29)
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 34486c6..4d5fae6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
+ than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
+ opcode).
+
2016-12-20 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index 3c90147..14d82bf 100644
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -322,7 +322,7 @@ const struct mips_opcode mips16_opcodes[] =
{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 },
-{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 },
+{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 },
{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },