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[binutils-gdb] [ARC] Add checking for LP_COUNT reg usage, improve error reporting.
- From: Claudiu Zissulescu <claziss at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 29 Nov 2016 11:00:02 -0000
- Subject: [binutils-gdb] [ARC] Add checking for LP_COUNT reg usage, improve error reporting.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=abe7c33b45288b407e6d001aad713183d4bab5c6
commit abe7c33b45288b407e6d001aad713183d4bab5c6
Author: Claudiu Zissulescu <claziss@synopsys.com>
Date: Tue Nov 15 15:11:47 2016 +0100
[ARC] Add checking for LP_COUNT reg usage, improve error reporting.
gas/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (find_opcode_match): New function argument
errmsg.
(assemble_tokens): Collect and report the eventual error message
found during opcode matching process.
* testsuite/gas/arc/lpcount-err.s: New file.
* testsuite/gas/arc/add_s-err.s: Update error message.
opcode/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (insert_ra_chk): New function.
(insert_rb_chk): Likewise.
(insert_rad): Update text error message.
(insert_rcd): Likewise.
(insert_rhv2): Likewise.
(insert_r0): Likewise.
(insert_r1): Likewise.
(insert_r2): Likewise.
(insert_r3): Likewise.
(insert_sp): Likewise.
(insert_gp): Likewise.
(insert_pcl): Likewise.
(insert_blink): Likewise.
(insert_ilink1): Likewise.
(insert_ilink2): Likewise.
(insert_ras): Likewise.
(insert_rbs): Likewise.
(insert_rcs): Likewise.
(insert_simm3s): Likewise.
(insert_rrange): Likewise.
(insert_fpel): Likewise.
(insert_blinkel): Likewise.
(insert_pcel): Likewise.
(insert_nps_3bit_dst): Likewise.
(insert_nps_3bit_dst_short): Likewise.
(insert_nps_3bit_src2_short): Likewise.
(insert_nps_bitop_size_2b): Likewise.
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
(RA_CHK): Define.
(RB): Adjust.
(RB_CHK): Define.
(RC): Adjust.
* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
* arc-tbl.h (div, divu): All instructions are DIVREM class.
Change first insn argument to check for LP_COUNT usage.
(rem): Likewise.
(ld, ldd): All instructions are LOAD class. Change first insn
argument to check for LP_COUNT usage.
(st, std): All instructions are STORE class.
(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
Change first insn argument to check for LP_COUNT usage.
(mov): All instructions are MOVE class. Change first insn
argument to check for LP_COUNT usage.
include/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
instruction classes.
Diff:
---
gas/ChangeLog | 9 +
gas/config/tc-arc.c | 35 +-
gas/testsuite/gas/arc/add_s-err.s | 2 +-
gas/testsuite/gas/arc/lpcount-err.s | 9 +
include/ChangeLog | 5 +
include/opcode/arc.h | 5 +
opcodes/ChangeLog | 46 +
opcodes/arc-dis.c | 4 +-
opcodes/arc-opc.c | 83 +-
opcodes/arc-tbl.h | 4472 +++++++++++++++++------------------
10 files changed, 2390 insertions(+), 2280 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c88a5f3..e8912cd 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/tc-arc.c (find_opcode_match): New function argument
+ errmsg.
+ (assemble_tokens): Collect and report the eventual error message
+ found during opcode matching process.
+ * testsuite/gas/arc/lpcount-err.s: New file.
+ * testsuite/gas/arc/add_s-err.s: Update error message.
+
2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
Amit Pawar <amit.pawar@amd.com>
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 4eb6d6d..f5cbc8b 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -1710,7 +1710,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
int *pntok,
struct arc_flags *first_pflag,
int nflgs,
- int *pcpumatch)
+ int *pcpumatch,
+ const char **errmsg)
{
const struct arc_opcode *opcode;
struct arc_opcode_hash_entry_iterator iter;
@@ -1765,7 +1766,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
{
case ARC_OPERAND_ADDRTYPE:
{
- const char *errmsg = NULL;
+ *errmsg = NULL;
/* Check to be an address type. */
if (tok[tokidx].X_op != O_addrtype)
@@ -1776,8 +1777,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
address type. */
gas_assert (operand->insert != NULL);
(*operand->insert) (0, tok[tokidx].X_add_number,
- &errmsg);
- if (errmsg != NULL)
+ errmsg);
+ if (*errmsg != NULL)
goto match_failed;
}
break;
@@ -1803,11 +1804,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
/* Special handling? */
if (operand->insert)
{
- const char *errmsg = NULL;
+ *errmsg = NULL;
(*operand->insert)(0,
regno (tok[tokidx].X_add_number),
- &errmsg);
- if (errmsg)
+ errmsg);
+ if (*errmsg)
{
if (operand->flags & ARC_OPERAND_IGNORE)
{
@@ -1923,11 +1924,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
{
if (operand->insert)
{
- const char *errmsg = NULL;
+ *errmsg = NULL;
(*operand->insert)(0,
tok[tokidx].X_add_number,
- &errmsg);
- if (errmsg)
+ errmsg);
+ if (*errmsg)
goto match_failed;
}
else if (!(operand->flags & ARC_OPERAND_IGNORE))
@@ -1948,11 +1949,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
regs |= get_register (tok[tokidx].X_op_symbol);
if (operand->insert)
{
- const char *errmsg = NULL;
+ *errmsg = NULL;
(*operand->insert)(0,
regs,
- &errmsg);
- if (errmsg)
+ errmsg);
+ if (*errmsg)
goto match_failed;
}
else
@@ -2326,6 +2327,7 @@ assemble_tokens (const char *opname,
bfd_boolean found_something = FALSE;
const struct arc_opcode_hash_entry *entry;
int cpumatch = 1;
+ const char *errmsg = NULL;
/* Search opcodes. */
entry = arc_find_opcode (opname);
@@ -2342,7 +2344,7 @@ assemble_tokens (const char *opname,
frag_now->fr_file, frag_now->fr_line, opname);
found_something = TRUE;
opcode = find_opcode_match (entry, tok, &ntok, pflags,
- nflgs, &cpumatch);
+ nflgs, &cpumatch, &errmsg);
if (opcode != NULL)
{
struct arc_insn insn;
@@ -2356,7 +2358,10 @@ assemble_tokens (const char *opname,
if (found_something)
{
if (cpumatch)
- as_bad (_("inappropriate arguments for opcode '%s'"), opname);
+ if (errmsg)
+ as_bad (_("%s for instruction '%s'"), errmsg, opname);
+ else
+ as_bad (_("inappropriate arguments for opcode '%s'"), opname);
else
as_bad (_("opcode '%s' not supported for target %s"), opname,
selected_cpu.name);
diff --git a/gas/testsuite/gas/arc/add_s-err.s b/gas/testsuite/gas/arc/add_s-err.s
index 298f4ef..024bc43 100644
--- a/gas/testsuite/gas/arc/add_s-err.s
+++ b/gas/testsuite/gas/arc/add_s-err.s
@@ -4,7 +4,7 @@
; { dg-do assemble { target arc*-*-* } }
; { dg-options "--mcpu=arc700" }
;; The following insns are accepted by ARCv2 only
- add_s r4,r4,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
+ add_s r4,r4,-1 ; { dg-error "Error: Register must be either r0-r3 or r12-r15 for instruction." }
add_s 0,0xAAAA5555,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
add_s r0,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
add_s r1,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
diff --git a/gas/testsuite/gas/arc/lpcount-err.s b/gas/testsuite/gas/arc/lpcount-err.s
new file mode 100644
index 0000000..51d6f70
--- /dev/null
+++ b/gas/testsuite/gas/arc/lpcount-err.s
@@ -0,0 +1,9 @@
+;; LP_COUNT register cannot be used with multi-cycle instructions such as:
+;; load, lr, multiply and divide.
+; { dg-do assemble { target arc*-*-* } }
+
+ .cpu HS
+
+ mpy lp_count,r0,r1 ; { dg-error "Error: LP_COUNT register cannot be used as destination register." }
+ ld lp_count,[r2,1] ; { dg-error "Error: LP_COUNT register cannot be used as destination register." }
+ div lp_count,r12,r1 ; { dg-error "Error: LP_COUNT register cannot be used as destination register." }
diff --git a/include/ChangeLog b/include/ChangeLog
index ce86557..30c66c2 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
+ instruction classes.
+
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 2214b2f..b3b76d9 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -47,17 +47,22 @@ typedef enum
BMU,
BRANCH,
CONTROL,
+ DIVREM,
DPI,
DSP,
FLOAT,
INVALID,
JUMP,
KERNEL,
+ LOAD,
LOGICAL,
MEMORY,
+ MOVE,
+ MPY,
NET,
PROTOCOL_DECODE,
PMU,
+ STORE,
XY
} insn_class_t;
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ef016c2..299b750 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,51 @@
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
+ * arc-opc.c (insert_ra_chk): New function.
+ (insert_rb_chk): Likewise.
+ (insert_rad): Update text error message.
+ (insert_rcd): Likewise.
+ (insert_rhv2): Likewise.
+ (insert_r0): Likewise.
+ (insert_r1): Likewise.
+ (insert_r2): Likewise.
+ (insert_r3): Likewise.
+ (insert_sp): Likewise.
+ (insert_gp): Likewise.
+ (insert_pcl): Likewise.
+ (insert_blink): Likewise.
+ (insert_ilink1): Likewise.
+ (insert_ilink2): Likewise.
+ (insert_ras): Likewise.
+ (insert_rbs): Likewise.
+ (insert_rcs): Likewise.
+ (insert_simm3s): Likewise.
+ (insert_rrange): Likewise.
+ (insert_fpel): Likewise.
+ (insert_blinkel): Likewise.
+ (insert_pcel): Likewise.
+ (insert_nps_3bit_dst): Likewise.
+ (insert_nps_3bit_dst_short): Likewise.
+ (insert_nps_3bit_src2_short): Likewise.
+ (insert_nps_bitop_size_2b): Likewise.
+ (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
+ (RA_CHK): Define.
+ (RB): Adjust.
+ (RB_CHK): Define.
+ (RC): Adjust.
+ * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
+ * arc-tbl.h (div, divu): All instructions are DIVREM class.
+ Change first insn argument to check for LP_COUNT usage.
+ (rem): Likewise.
+ (ld, ldd): All instructions are LOAD class. Change first insn
+ argument to check for LP_COUNT usage.
+ (st, std): All instructions are STORE class.
+ (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
+ Change first insn argument to check for LP_COUNT usage.
+ (mov): All instructions are MOVE class. Change first insn
+ argument to check for LP_COUNT usage.
+
+2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
+
* arc-dis.c (is_compatible_p): Remove function.
(skip_this_opcode): Don't add any decoding class to decode list.
Remove warning.
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index bcba2c7..77cf867 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -750,8 +750,10 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode)
insn_type = dis_branch;
}
break;
+ case LOAD:
+ case STORE:
case MEMORY:
- insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
+ insn_type = dis_dref;
break;
default:
insn_type = dis_nonbranch;
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 0395345..eb335b1 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -30,6 +30,17 @@
instructions. All NPS400 features are built into all ARC target builds as
this reduces the chances that regressions might creep in. */
+/* Insert RA register into a 32-bit opcode, with checks. */
+static unsigned long long
+insert_ra_chk (unsigned long long insn,
+ long long int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | (value & 0x3F);
+}
/* Insert RB register into a 32-bit opcode. */
static unsigned long long
insert_rb (unsigned long long insn,
@@ -39,6 +50,18 @@ insert_rb (unsigned long long insn,
return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
}
+/* Insert RB register with checks. */
+static unsigned long long
+insert_rb_chk (unsigned long long insn,
+ long long int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
+
static long long int
extract_rb (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
@@ -58,7 +81,9 @@ insert_rad (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value & 0x01)
- *errmsg = _("Improper register value.");
+ *errmsg = _("cannot use odd number destination register");
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
return insn | (value & 0x3F);
}
@@ -69,7 +94,7 @@ insert_rcd (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value & 0x01)
- *errmsg = _("Improper register value.");
+ *errmsg = _("cannot use odd number source register");
return insn | ((value & 0x3F) << 6);
}
@@ -142,7 +167,7 @@ insert_rhv2 (unsigned long long insn,
{
if (value == 0x1E)
*errmsg =
- _("Register R30 is a limm indicator for this type of instruction.");
+ _("Register R30 is a limm indicator");
return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
}
@@ -161,7 +186,7 @@ insert_r0 (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value != 0)
- *errmsg = _("Register must be R0.");
+ *errmsg = _("Register must be R0");
return insn;
}
@@ -179,7 +204,7 @@ insert_r1 (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value != 1)
- *errmsg = _("Register must be R1.");
+ *errmsg = _("Register must be R1");
return insn;
}
@@ -196,7 +221,7 @@ insert_r2 (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value != 2)
- *errmsg = _("Register must be R2.");
+ *errmsg = _("Register must be R2");
return insn;
}
@@ -213,7 +238,7 @@ insert_r3 (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value != 3)
- *errmsg = _("Register must be R3.");
+ *errmsg = _("Register must be R3");
return insn;
}
@@ -230,7 +255,7 @@ insert_sp (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value != 28)
- *errmsg = _("Register must be SP.");
+ *errmsg = _("Register must be SP");
return insn;
}
@@ -247,7 +272,7 @@ insert_gp (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value != 26)
- *errmsg = _("Register must be GP.");
+ *errmsg = _("Register must be GP");
return insn;
}
@@ -264,7 +289,7 @@ insert_pcl (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value != 63)
- *errmsg = _("Register must be PCL.");
+ *errmsg = _("Register must be PCL");
return insn;
}
@@ -281,7 +306,7 @@ insert_blink (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value != 31)
- *errmsg = _("Register must be BLINK.");
+ *errmsg = _("Register must be BLINK");
return insn;
}
@@ -298,7 +323,7 @@ insert_ilink1 (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value != 29)
- *errmsg = _("Register must be ILINK1.");
+ *errmsg = _("Register must be ILINK1");
return insn;
}
@@ -315,7 +340,7 @@ insert_ilink2 (unsigned long long insn,
const char **errmsg ATTRIBUTE_UNUSED)
{
if (value != 30)
- *errmsg = _("Register must be ILINK2.");
+ *errmsg = _("Register must be ILINK2");
return insn;
}
@@ -346,7 +371,7 @@ insert_ras (unsigned long long insn,
insn |= (value - 8);
break;
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ *errmsg = _("Register must be either r0-r3 or r12-r15");
break;
}
return insn;
@@ -383,7 +408,7 @@ insert_rbs (unsigned long long insn,
insn |= ((value - 8)) << 8;
break;
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ *errmsg = _("Register must be either r0-r3 or r12-r15");
break;
}
return insn;
@@ -420,7 +445,7 @@ insert_rcs (unsigned long long insn,
insn |= ((value - 8)) << 5;
break;
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ *errmsg = _("Register must be either r0-r3 or r12-r15");
break;
}
return insn;
@@ -470,7 +495,7 @@ insert_simm3s (unsigned long long insn,
tmp = 0x06;
break;
default:
- *errmsg = _("Accepted values are from -1 to 6.");
+ *errmsg = _("Accepted values are from -1 to 6");
break;
}
@@ -498,12 +523,12 @@ insert_rrange (unsigned long long insn,
int reg2 = value & 0xFFFF;
if (reg1 != 13)
{
- *errmsg = _("First register of the range should be r13.");
+ *errmsg = _("First register of the range should be r13");
return insn;
}
if (reg2 < 13 || reg2 > 26)
{
- *errmsg = _("Last register of the range doesn't fit.");
+ *errmsg = _("Last register of the range doesn't fit");
return insn;
}
insn |= ((reg2 - 12) & 0x0F) << 1;
@@ -524,7 +549,7 @@ insert_fpel (unsigned long long insn,
{
if (value != 27)
{
- *errmsg = _("Invalid register number, should be fp.");
+ *errmsg = _("Invalid register number, should be fp");
return insn;
}
@@ -546,7 +571,7 @@ insert_blinkel (unsigned long long insn,
{
if (value != 31)
{
- *errmsg = _("Invalid register number, should be blink.");
+ *errmsg = _("Invalid register number, should be blink");
return insn;
}
@@ -568,7 +593,7 @@ insert_pclel (unsigned long long insn,
{
if (value != 63)
{
- *errmsg = _("Invalid register number, should be pcl.");
+ *errmsg = _("Invalid register number, should be pcl");
return insn;
}
@@ -664,7 +689,7 @@ insert_nps_3bit_reg_at_##OFFSET##_##NAME \
insn |= (value - 8) << (OFFSET); \
break; \
default: \
- *errmsg = _("Register must be either r0-r3 or r12-r15."); \
+ *errmsg = _("Register must be either r0-r3 or r12-r15"); \
break; \
} \
return insn; \
@@ -712,7 +737,7 @@ insert_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED,
break;
default:
value = 0;
- *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
+ *errmsg = _("Invalid size, should be 1, 2, 4, or 8");
break;
}
@@ -822,7 +847,7 @@ insert_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
value = value / 8; \
break; \
default: \
- *errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \
+ *errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \
value = 0; \
} \
insn |= (value << SHIFT); \
@@ -1529,9 +1554,13 @@ const struct arc_operand arc_operands[] =
instructions. */
#define RA (IGNORED + 1)
{ 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
-#define RB (RA + 1)
+#define RA_CHK (RA + 1)
+ { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
+#define RB (RA_CHK + 1)
{ 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
-#define RC (RB + 1)
+#define RB_CHK (RB + 1)
+ { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
+#define RC (RB_CHK + 1)
{ 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
#define RBdup (RC + 1)
{ 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index c6e246e..ab69bf5 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -56,19 +56,19 @@
{ "abss", 0x2E2F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM }, { C_F }},
/* abssh<.f> b,c 00101bbb00101111FBBBCCCCCC000100. */
-{ "abssh", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { C_F }},
+{ "abssh", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RC }, { C_F }},
/* abssh<.f> 0,c 0010111000101111F111CCCCCC000100. */
{ "abssh", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { C_F }},
/* abssh<.f> b,u6 00101bbb01101111FBBBuuuuuu000100. */
-{ "abssh", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { C_F }},
+{ "abssh", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, UIMM6_20 }, { C_F }},
/* abssh<.f> 0,u6 0010111001101111F111uuuuuu000100. */
{ "abssh", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
/* abssh<.f> b,limm 00101bbb00101111FBBB111110000100. */
-{ "abssh", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { C_F }},
+{ "abssh", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, LIMM }, { C_F }},
/* abssh<.f> 0,limm 0010111000101111F111111110000100. */
{ "abssh", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { C_F }},
@@ -614,31 +614,31 @@
{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA_S, LIMM_S, SIMM3_5_S }, { 0 }},
/* aex b,c 00100bbb00100111RBBBCCCCCCRRRRRR. */
-{ "aex", 0x20270000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
+{ "aex", 0x20270000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
/* aex<.cc> b,c 00100bbb11100111RBBBCCCCCC0QQQQQ. */
-{ "aex", 0x20E70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_CC }},
+{ "aex", 0x20E70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_CC }},
/* aex b,u6 00100bbb01100111RBBBuuuuuuRRRRRR. */
-{ "aex", 0x20670000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+{ "aex", 0x20670000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
/* aex<.cc> b,u6 00100bbb11100111RBBBuuuuuu1QQQQQ. */
-{ "aex", 0x20E70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+{ "aex", 0x20E70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
/* aex b,s12 00100bbb10100111RBBBssssssSSSSSS. */
-{ "aex", 0x20A70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+{ "aex", 0x20A70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
/* aex limm,c 0010011000100111R111CCCCCCRRRRRR. */
{ "aex", 0x26277000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }},
/* aex b,limm 00100bbb00100111RBBB111110RRRRRR. */
-{ "aex", 0x20270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }},
+{ "aex", 0x20270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
/* aex<.cc> limm,c 0010011011100111R111CCCCCC0QQQQQ. */
{ "aex", 0x26E77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_CC }},
/* aex<.cc> b,limm 00100bbb11100111RBBB1111100QQQQQ. */
-{ "aex", 0x20E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_CC }},
+{ "aex", 0x20E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_CC }},
/* aex limm,u6 0010011001100111R111uuuuuuRRRRRR. */
{ "aex", 0x26677000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
@@ -803,31 +803,31 @@
{ "aslacc", 0x286F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }},
/* asldw<.f> a,b,c 00101bbb00100001FBBBCCCCCCAAAAAA. */
-{ "asldw", 0x28210000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+{ "asldw", 0x28210000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
/* asldw<.f> 0,b,c 00101bbb00100001FBBBCCCCCC111110. */
{ "asldw", 0x2821003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
/* asldw<.f><.cc> b,b,c 00101bbb11100001FBBBCCCCCC0QQQQQ. */
-{ "asldw", 0x28E10000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "asldw", 0x28E10000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
/* asldw<.f> a,b,u6 00101bbb01100001FBBBuuuuuuAAAAAA. */
-{ "asldw", 0x28610000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "asldw", 0x28610000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
/* asldw<.f> 0,b,u6 00101bbb01100001FBBBuuuuuu111110. */
{ "asldw", 0x2861003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
/* asldw<.f><.cc> b,b,u6 00101bbb11100001FBBBuuuuuu1QQQQQ. */
-{ "asldw", 0x28E10020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "asldw", 0x28E10020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
/* asldw<.f> b,b,s12 00101bbb10100001FBBBssssssSSSSSS. */
-{ "asldw", 0x28A10000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "asldw", 0x28A10000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
/* asldw<.f> a,limm,c 0010111000100001F111CCCCCCAAAAAA. */
-{ "asldw", 0x2E217000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+{ "asldw", 0x2E217000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
/* asldw<.f> a,b,limm 00101bbb00100001FBBB111110AAAAAA. */
-{ "asldw", 0x28210F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+{ "asldw", 0x28210F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
/* asldw<.f> 0,limm,c 0010111000100001F111CCCCCC111110. */
{ "asldw", 0x2E21703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
@@ -839,10 +839,10 @@
{ "asldw", 0x2EE17000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
/* asldw<.f><.cc> b,b,limm 00101bbb11100001FBBB1111100QQQQQ. */
-{ "asldw", 0x28E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+{ "asldw", 0x28E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
/* asldw<.f> a,limm,u6 0010111001100001F111uuuuuuAAAAAA. */
-{ "asldw", 0x2E617000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "asldw", 0x2E617000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
/* asldw<.f> 0,limm,u6 0010111001100001F111uuuuuu111110. */
{ "asldw", 0x2E61703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
@@ -854,7 +854,7 @@
{ "asldw", 0x2EA17000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
/* asldw<.f> a,limm,limm 0010111000100001F111111110AAAAAA. */
-{ "asldw", 0x2E217F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "asldw", 0x2E217F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
/* asldw<.f> 0,limm,limm 0010111000100001F111111110111110. */
{ "asldw", 0x2E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
@@ -929,31 +929,31 @@
{ "aslsacc", 0x296F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }},
/* aslsdw<.f> a,b,c 00101bbb00100100FBBBCCCCCCAAAAAA. */
-{ "aslsdw", 0x28240000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+{ "aslsdw", 0x28240000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
/* aslsdw<.f> 0,b,c 00101bbb00100100FBBBCCCCCC111110. */
{ "aslsdw", 0x2824003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
/* aslsdw<.f><.cc> b,b,c 00101bbb11100100FBBBCCCCCC0QQQQQ. */
-{ "aslsdw", 0x28E40000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "aslsdw", 0x28E40000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
/* aslsdw<.f> a,b,u6 00101bbb01100100FBBBuuuuuuAAAAAA. */
-{ "aslsdw", 0x28640000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "aslsdw", 0x28640000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
/* aslsdw<.f> 0,b,u6 00101bbb01100100FBBBuuuuuu111110. */
{ "aslsdw", 0x2864003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
/* aslsdw<.f><.cc> b,b,u6 00101bbb11100100FBBBuuuuuu1QQQQQ. */
-{ "aslsdw", 0x28E40020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "aslsdw", 0x28E40020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
/* aslsdw<.f> b,b,s12 00101bbb10100100FBBBssssssSSSSSS. */
-{ "aslsdw", 0x28A40000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "aslsdw", 0x28A40000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
/* aslsdw<.f> a,limm,c 0010111000100100F111CCCCCCAAAAAA. */
-{ "aslsdw", 0x2E247000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+{ "aslsdw", 0x2E247000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
/* aslsdw<.f> a,b,limm 00101bbb00100100FBBB111110AAAAAA. */
-{ "aslsdw", 0x28240F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+{ "aslsdw", 0x28240F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
/* aslsdw<.f> 0,limm,c 0010111000100100F111CCCCCC111110. */
{ "aslsdw", 0x2E24703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
@@ -965,10 +965,10 @@
{ "aslsdw", 0x2EE47000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
/* aslsdw<.f><.cc> b,b,limm 00101bbb11100100FBBB1111100QQQQQ. */
-{ "aslsdw", 0x28E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+{ "aslsdw", 0x28E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
/* aslsdw<.f> a,limm,u6 0010111001100100F111uuuuuuAAAAAA. */
-{ "aslsdw", 0x2E647000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "aslsdw", 0x2E647000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
/* aslsdw<.f> 0,limm,u6 0010111001100100F111uuuuuu111110. */
{ "aslsdw", 0x2E64703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
@@ -980,7 +980,7 @@
{ "aslsdw", 0x2EA47000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
/* aslsdw<.f> a,limm,limm 0010111000100100F111111110AAAAAA. */
-{ "aslsdw", 0x2E247F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "aslsdw", 0x2E247F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
/* aslsdw<.f> 0,limm,limm 0010111000100100F111111110111110. */
{ "aslsdw", 0x2E247FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
@@ -1115,31 +1115,31 @@
{ "asr8", 0x2E2F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
/* asrdw<.f> a,b,c 00101bbb00100010FBBBCCCCCCAAAAAA. */
-{ "asrdw", 0x28220000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+{ "asrdw", 0x28220000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
/* asrdw<.f> 0,b,c 00101bbb00100010FBBBCCCCCC111110. */
{ "asrdw", 0x2822003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
/* asrdw<.f><.cc> b,b,c 00101bbb11100010FBBBCCCCCC0QQQQQ. */
-{ "asrdw", 0x28E20000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "asrdw", 0x28E20000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
/* asrdw<.f> a,b,u6 00101bbb01100010FBBBuuuuuuAAAAAA. */
-{ "asrdw", 0x28620000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "asrdw", 0x28620000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
/* asrdw<.f> 0,b,u6 00101bbb01100010FBBBuuuuuu111110. */
{ "asrdw", 0x2862003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
/* asrdw<.f><.cc> b,b,u6 00101bbb11100010FBBBuuuuuu1QQQQQ. */
-{ "asrdw", 0x28E20020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "asrdw", 0x28E20020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
/* asrdw<.f> b,b,s12 00101bbb10100010FBBBssssssSSSSSS. */
-{ "asrdw", 0x28A20000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "asrdw", 0x28A20000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
/* asrdw<.f> a,limm,c 0010111000100010F111CCCCCCAAAAAA. */
-{ "asrdw", 0x2E227000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+{ "asrdw", 0x2E227000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
/* asrdw<.f> a,b,limm 00101bbb00100010FBBB111110AAAAAA. */
-{ "asrdw", 0x28220F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+{ "asrdw", 0x28220F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
/* asrdw<.f> 0,limm,c 0010111000100010F111CCCCCC111110. */
{ "asrdw", 0x2E22703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
@@ -1151,10 +1151,10 @@
{ "asrdw", 0x2EE27000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
/* asrdw<.f><.cc> b,b,limm 00101bbb11100010FBBB1111100QQQQQ. */
-{ "asrdw", 0x28E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+{ "asrdw", 0x28E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
/* asrdw<.f> a,limm,u6 0010111001100010F111uuuuuuAAAAAA. */
-{ "asrdw", 0x2E627000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "asrdw", 0x2E627000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
/* asrdw<.f> 0,limm,u6 0010111001100010F111uuuuuu111110. */
{ "asrdw", 0x2E62703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
@@ -1166,7 +1166,7 @@
{ "asrdw", 0x2EA27000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
/* asrdw<.f> a,limm,limm 0010111000100010F111111110AAAAAA. */
-{ "asrdw", 0x2E227F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "asrdw", 0x2E227F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
/* asrdw<.f> 0,limm,limm 0010111000100010F111111110111110. */
{ "asrdw", 0x2E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
@@ -1235,31 +1235,31 @@
{ "asrs", 0x2ECB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
/* asrsdw<.f> a,b,c 00101bbb00100101FBBBCCCCCCAAAAAA. */
-{ "asrsdw", 0x28250000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }},
+{ "asrsdw", 0x28250000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
/* asrsdw<.f> 0,b,c 00101bbb00100101FBBBCCCCCC111110. */
{ "asrsdw", 0x2825003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }},
/* asrsdw<.f><.cc> b,b,c 00101bbb11100101FBBBCCCCCC0QQQQQ. */
-{ "asrsdw", 0x28E50000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "asrsdw", 0x28E50000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
/* asrsdw<.f> a,b,u6 00101bbb01100101FBBBuuuuuuAAAAAA. */
-{ "asrsdw", 0x28650000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "asrsdw", 0x28650000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
/* asrsdw<.f> 0,b,u6 00101bbb01100101FBBBuuuuuu111110. */
{ "asrsdw", 0x2865003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
/* asrsdw<.f><.cc> b,b,u6 00101bbb11100101FBBBuuuuuu1QQQQQ. */
-{ "asrsdw", 0x28E50020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "asrsdw", 0x28E50020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
/* asrsdw<.f> b,b,s12 00101bbb10100101FBBBssssssSSSSSS. */
-{ "asrsdw", 0x28A50000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "asrsdw", 0x28A50000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
/* asrsdw<.f> a,limm,c 0010111000100101F111CCCCCCAAAAAA. */
-{ "asrsdw", 0x2E257000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+{ "asrsdw", 0x2E257000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
/* asrsdw<.f> a,b,limm 00101bbb00100101FBBB111110AAAAAA. */
-{ "asrsdw", 0x28250F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+{ "asrsdw", 0x28250F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
/* asrsdw<.f> 0,limm,c 0010111000100101F111CCCCCC111110. */
{ "asrsdw", 0x2E25703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
@@ -1271,10 +1271,10 @@
{ "asrsdw", 0x2EE57000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
/* asrsdw<.f><.cc> b,b,limm 00101bbb11100101FBBB1111100QQQQQ. */
-{ "asrsdw", 0x28E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+{ "asrsdw", 0x28E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
/* asrsdw<.f> a,limm,u6 0010111001100101F111uuuuuuAAAAAA. */
-{ "asrsdw", 0x2E657000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "asrsdw", 0x2E657000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
/* asrsdw<.f> 0,limm,u6 0010111001100101F111uuuuuu111110. */
{ "asrsdw", 0x2E65703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
@@ -1286,7 +1286,7 @@
{ "asrsdw", 0x2EA57000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
/* asrsdw<.f> a,limm,limm 0010111000100101F111111110AAAAAA. */
-{ "asrsdw", 0x2E257F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "asrsdw", 0x2E257F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
/* asrsdw<.f> 0,limm,limm 0010111000100101F111111110111110. */
{ "asrsdw", 0x2E257FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
@@ -1295,31 +1295,31 @@
{ "asrsdw", 0x2EE57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
/* asrsr<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA. */
-{ "asrsr", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }},
+{ "asrsr", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
/* asrsr<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110. */
{ "asrsr", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }},
/* asrsr<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ. */
-{ "asrsr", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "asrsr", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
/* asrsr<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA. */
-{ "asrsr", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "asrsr", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
/* asrsr<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110. */
{ "asrsr", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
/* asrsr<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ. */
-{ "asrsr", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "asrsr", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
/* asrsr<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS. */
-{ "asrsr", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "asrsr", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
/* asrsr<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA. */
-{ "asrsr", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+{ "asrsr", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
/* asrsr<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA. */
-{ "asrsr", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+{ "asrsr", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
/* asrsr<.f> 0,limm,c 0010111000001100F111CCCCCC111110. */
{ "asrsr", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
@@ -1328,13 +1328,13 @@
{ "asrsr", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
/* asrsr<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ. */
-{ "asrsr", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+{ "asrsr", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
/* asrsr<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ. */
{ "asrsr", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
/* asrsr<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA. */
-{ "asrsr", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "asrsr", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
/* asrsr<.f> 0,limm,u6 0010111001001100F111uuuuuu111110. */
{ "asrsr", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
@@ -1346,7 +1346,7 @@
{ "asrsr", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
/* asrsr<.f> a,limm,limm 0010111000001100F111111110AAAAAA. */
-{ "asrsr", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "asrsr", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
/* asrsr<.f> 0,limm,limm 0010111000001100F111111110111110. */
{ "asrsr", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
@@ -2168,31 +2168,31 @@
{ "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }},
/* cbflyhf0r a,b,c 00110bbb000110111BBBCCCCCCAAAAAA. */
-{ "cbflyhf0r", 0x301B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+{ "cbflyhf0r", 0x301B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
/* cbflyhf0r 0,b,c 00110bbb000110111BBBCCCCCC111110. */
{ "cbflyhf0r", 0x301B803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
/* cbflyhf0r<.cc> b,b,c 00110bbb110110111BBBCCCCCC0QQQQQ. */
-{ "cbflyhf0r", 0x30DB8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+{ "cbflyhf0r", 0x30DB8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
/* cbflyhf0r a,b,u6 00110bbb010110111BBBuuuuuuAAAAAA. */
-{ "cbflyhf0r", 0x305B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "cbflyhf0r", 0x305B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
/* cbflyhf0r 0,b,u6 00110bbb010110111BBBuuuuuu111110. */
{ "cbflyhf0r", 0x305B803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
/* cbflyhf0r<.cc> b,b,u6 00110bbb110110111BBBuuuuuu1QQQQQ. */
-{ "cbflyhf0r", 0x30DB8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+{ "cbflyhf0r", 0x30DB8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
/* cbflyhf0r b,b,s12 00110bbb100110111BBBssssssSSSSSS. */
-{ "cbflyhf0r", 0x309B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+{ "cbflyhf0r", 0x309B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
/* cbflyhf0r a,limm,c 00110110000110111111CCCCCCAAAAAA. */
-{ "cbflyhf0r", 0x361BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "cbflyhf0r", 0x361BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
/* cbflyhf0r a,b,limm 00110bbb000110111BBB111110AAAAAA. */
-{ "cbflyhf0r", 0x301B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "cbflyhf0r", 0x301B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
/* cbflyhf0r 0,limm,c 00110110000110111111CCCCCC111110. */
{ "cbflyhf0r", 0x361BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -2201,13 +2201,13 @@
{ "cbflyhf0r", 0x301B8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
/* cbflyhf0r<.cc> b,b,limm 00110bbb110110111BBB1111100QQQQQ. */
-{ "cbflyhf0r", 0x30DB8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+{ "cbflyhf0r", 0x30DB8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
/* cbflyhf0r<.cc> 0,limm,c 00110110110110111111CCCCCC0QQQQQ. */
{ "cbflyhf0r", 0x36DBF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
/* cbflyhf0r a,limm,u6 00110110010110111111uuuuuuAAAAAA. */
-{ "cbflyhf0r", 0x365BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "cbflyhf0r", 0x365BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
/* cbflyhf0r 0,limm,u6 00110110010110111111uuuuuu111110. */
{ "cbflyhf0r", 0x365BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -2219,7 +2219,7 @@
{ "cbflyhf0r", 0x369BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
/* cbflyhf0r a,limm,limm 00110110000110111111111110AAAAAA. */
-{ "cbflyhf0r", 0x361BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "cbflyhf0r", 0x361BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
/* cbflyhf0r 0,limm,limm 00110110000110111111111110111110. */
{ "cbflyhf0r", 0x361BFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -2228,19 +2228,19 @@
{ "cbflyhf0r", 0x36DBFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
/* cbflyhf1r b,c 00110bbb001011110BBBCCCCCC111001. */
-{ "cbflyhf1r", 0x302F0039, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }},
+{ "cbflyhf1r", 0x302F0039, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RC }, { 0 }},
/* cbflyhf1r 0,c 00110110001011110111CCCCCC011001. */
{ "cbflyhf1r", 0x362F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }},
/* cbflyhf1r b,u6 00110bbb011011110BBBuuuuuu011001. */
-{ "cbflyhf1r", 0x306F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }},
+{ "cbflyhf1r", 0x306F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
/* cbflyhf1r 0,u6 00110110011011110111uuuuuu011001. */
{ "cbflyhf1r", 0x366F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
/* cbflyhf1r b,limm 00110bbb001011110BBB111110011001. */
-{ "cbflyhf1r", 0x302F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }},
+{ "cbflyhf1r", 0x302F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
/* cbflyhf1r 0,limm 00110110001011110111111110011001. */
{ "cbflyhf1r", 0x362F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }},
@@ -2279,31 +2279,31 @@
{ "clri", 0x276F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
/* cmacchfr a,b,c 00110bbb000010011BBBCCCCCCAAAAAA. */
-{ "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+{ "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
/* cmacchfr 0,b,c 00110bbb000010011BBBCCCCCC111110. */
{ "cmacchfr", 0x3009803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
/* cmacchfr<.cc> b,b,c 00110bbb110010011BBBCCCCCC0QQQQQ. */
-{ "cmacchfr", 0x30C98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+{ "cmacchfr", 0x30C98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
/* cmacchfr a,b,u6 00110bbb010010011BBBuuuuuuAAAAAA. */
-{ "cmacchfr", 0x30498000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "cmacchfr", 0x30498000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
/* cmacchfr 0,b,u6 00110bbb010010011BBBuuuuuu111110. */
{ "cmacchfr", 0x3049803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
/* cmacchfr<.cc> b,b,u6 00110bbb110010011BBBuuuuuu1QQQQQ. */
-{ "cmacchfr", 0x30C98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+{ "cmacchfr", 0x30C98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
/* cmacchfr b,b,s12 00110bbb100010011BBBssssssSSSSSS. */
-{ "cmacchfr", 0x30898000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+{ "cmacchfr", 0x30898000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
/* cmacchfr a,limm,c 00110110000010011111CCCCCCAAAAAA. */
-{ "cmacchfr", 0x3609F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "cmacchfr", 0x3609F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
/* cmacchfr a,b,limm 00110bbb000010011BBB111110AAAAAA. */
-{ "cmacchfr", 0x30098F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "cmacchfr", 0x30098F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
/* cmacchfr 0,limm,c 00110110000010011111CCCCCC111110. */
{ "cmacchfr", 0x3609F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -2315,10 +2315,10 @@
{ "cmacchfr", 0x30C98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
/* cmacchfr<.cc> b,b,limm 00110110110010011111CCCCCC0QQQQQ. */
-{ "cmacchfr", 0x36C9F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+{ "cmacchfr", 0x36C9F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
/* cmacchfr a,limm,u6 00110110010010011111uuuuuuAAAAAA. */
-{ "cmacchfr", 0x3649F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "cmacchfr", 0x3649F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
/* cmacchfr 0,limm,u6 00110110010010011111uuuuuu111110. */
{ "cmacchfr", 0x3649F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -2330,7 +2330,7 @@
{ "cmacchfr", 0x3689F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
/* cmacchfr a,limm,limm 00110110000010011111111110AAAAAA. */
-{ "cmacchfr", 0x3609FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "cmacchfr", 0x3609FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
/* cmacchfr 0,limm,limm 00110110000010011111111110111110. */
{ "cmacchfr", 0x3609FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -2339,31 +2339,31 @@
{ "cmacchfr", 0x36C9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
/* cmacchnfr a,b,c 00110bbb000010001BBBCCCCCCAAAAAA. */
-{ "cmacchnfr", 0x30088000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+{ "cmacchnfr", 0x30088000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
/* cmacchnfr 0,b,c 00110bbb000010001BBBCCCCCC111110. */
{ "cmacchnfr", 0x3008803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
/* cmacchnfr<.cc> b,b,c 00110bbb110010001BBBCCCCCC0QQQQQ. */
-{ "cmacchnfr", 0x30C88000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+{ "cmacchnfr", 0x30C88000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
/* cmacchnfr a,b,u6 00110bbb010010001BBBuuuuuuAAAAAA. */
-{ "cmacchnfr", 0x30488000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "cmacchnfr", 0x30488000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
/* cmacchnfr 0,b,u6 00110bbb010010001BBBuuuuuu111110. */
{ "cmacchnfr", 0x3048803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
/* cmacchnfr<.cc> b,b,u6 00110bbb110010001BBBuuuuuu1QQQQQ. */
-{ "cmacchnfr", 0x30C88020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+{ "cmacchnfr", 0x30C88020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
/* cmacchnfr b,b,s12 00110bbb100010001BBBssssssSSSSSS. */
-{ "cmacchnfr", 0x30888000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+{ "cmacchnfr", 0x30888000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
/* cmacchnfr a,limm,c 00110110000010001111CCCCCCAAAAAA. */
-{ "cmacchnfr", 0x3608F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "cmacchnfr", 0x3608F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
/* cmacchnfr a,b,limm 00110bbb000010001BBB111110AAAAAA. */
-{ "cmacchnfr", 0x30088F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "cmacchnfr", 0x30088F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
/* cmacchnfr 0,limm,c 00110110000010001111CCCCCC111110. */
{ "cmacchnfr", 0x3608F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -2375,10 +2375,10 @@
{ "cmacchnfr", 0x30C88F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
/* cmacchnfr<.cc> b,b,limm 00110110110010001111CCCCCC0QQQQQ. */
-{ "cmacchnfr", 0x36C8F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+{ "cmacchnfr", 0x36C8F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
/* cmacchnfr a,limm,u6 00110110010010001111uuuuuuAAAAAA. */
-{ "cmacchnfr", 0x3648F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "cmacchnfr", 0x3648F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
/* cmacchnfr 0,limm,u6 00110110010010001111uuuuuu111110. */
{ "cmacchnfr", 0x3648F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -2390,7 +2390,7 @@
{ "cmacchnfr", 0x3688F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
/* cmacchnfr a,limm,limm 00110110000010001111111110AAAAAA. */
-{ "cmacchnfr", 0x3608FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "cmacchnfr", 0x3608FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
/* cmacchnfr 0,limm,limm 00110110000010001111111110111110. */
{ "cmacchnfr", 0x3608FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -2399,31 +2399,31 @@
{ "cmacchnfr", 0x36C8FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
/* cmachfr a,b,c 00110bbb000001111BBBCCCCCCAAAAAA. */
-{ "cmachfr", 0x30078000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+{ "cmachfr", 0x30078000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
/* cmachfr 0,b,c 00110bbb000001111BBBCCCCCC111110. */
{ "cmachfr", 0x3007803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
/* cmachfr<.cc> b,b,c 00110bbb110001111BBBCCCCCC0QQQQQ. */
-{ "cmachfr", 0x30C78000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+{ "cmachfr", 0x30C78000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
/* cmachfr a,b,u6 00110bbb010001111BBBuuuuuuAAAAAA. */
-{ "cmachfr", 0x30478000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "cmachfr", 0x30478000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
/* cmachfr 0,b,u6 00110bbb010001111BBBuuuuuu111110. */
{ "cmachfr", 0x3047803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
/* cmachfr<.cc> b,b,u6 00110bbb110001111BBBuuuuuu1QQQQQ. */
-{ "cmachfr", 0x30C78020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+{ "cmachfr", 0x30C78020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
/* cmachfr b,b,s12 00110bbb100001111BBBssssssSSSSSS. */
-{ "cmachfr", 0x30878000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+{ "cmachfr", 0x30878000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
/* cmachfr a,limm,c 00110110000001111111CCCCCCAAAAAA. */
-{ "cmachfr", 0x3607F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "cmachfr", 0x3607F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
/* cmachfr a,b,limm 00110bbb000001111BBB111110AAAAAA. */
-{ "cmachfr", 0x30078F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "cmachfr", 0x30078F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
/* cmachfr 0,limm,c 00110110000001111111CCCCCC111110. */
{ "cmachfr", 0x3607F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -2435,10 +2435,10 @@
{ "cmachfr", 0x30C78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
/* cmachfr<.cc> b,b,limm 00110110110001111111CCCCCC0QQQQQ. */
-{ "cmachfr", 0x36C7F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+{ "cmachfr", 0x36C7F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
/* cmachfr a,limm,u6 00110110010001111111uuuuuuAAAAAA. */
-{ "cmachfr", 0x3647F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "cmachfr", 0x3647F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
/* cmachfr 0,limm,u6 00110110010001111111uuuuuu111110. */
{ "cmachfr", 0x3647F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -2450,7 +2450,7 @@
{ "cmachfr", 0x3687F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
/* cmachfr a,limm,limm 00110110000001111111111110AAAAAA. */
-{ "cmachfr", 0x3607FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "cmachfr", 0x3607FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
/* cmachfr 0,limm,limm 00110110000001111111111110111110. */
{ "cmachfr", 0x3607FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -2459,31 +2459,31 @@
{ "cmachfr", 0x36C7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
/* cmachnfr a,b,c 00110bbb000001101BBBCCCCCCAAAAAA. */
-{ "cmachnfr", 0x30068000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+{ "cmachnfr", 0x30068000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
/* cmachnfr 0,b,c 00110bbb000001101BBBCCCCCC111110. */
{ "cmachnfr", 0x3006803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
/* cmachnfr<.cc> b,b,c 00110bbb110001101BBBCCCCCC0QQQQQ. */
-{ "cmachnfr", 0x30C68000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+{ "cmachnfr", 0x30C68000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
/* cmachnfr a,b,u6 00110bbb010001101BBBuuuuuuAAAAAA. */
-{ "cmachnfr", 0x30468000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "cmachnfr", 0x30468000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
/* cmachnfr 0,b,u6 00110bbb010001101BBBuuuuuu111110. */
{ "cmachnfr", 0x3046803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
/* cmachnfr<.cc> b,b,u6 00110bbb110001101BBBuuuuuu1QQQQQ. */
-{ "cmachnfr", 0x30C68020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+{ "cmachnfr", 0x30C68020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
/* cmachnfr b,b,s12 00110bbb100001101BBBssssssSSSSSS. */
-{ "cmachnfr", 0x30868000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+{ "cmachnfr", 0x30868000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
/* cmachnfr a,limm,c 00110110000001101111CCCCCCAAAAAA. */
-{ "cmachnfr", 0x3606F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "cmachnfr", 0x3606F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
/* cmachnfr a,b,limm 00110bbb000001101BBB111110AAAAAA. */
-{ "cmachnfr", 0x30068F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "cmachnfr", 0x30068F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
/* cmachnfr 0,limm,c 00110110000001101111CCCCCC111110. */
{ "cmachnfr", 0x3606F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -2495,10 +2495,10 @@
{ "cmachnfr", 0x30C68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
/* cmachnfr<.cc> b,b,limm 00110110110001101111CCCCCC0QQQQQ. */
-{ "cmachnfr", 0x36C6F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+{ "cmachnfr", 0x36C6F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
/* cmachnfr a,limm,u6 00110110010001101111uuuuuuAAAAAA. */
-{ "cmachnfr", 0x3646F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "cmachnfr", 0x3646F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
/* cmachnfr 0,limm,u6 00110110010001101111uuuuuu111110. */
{ "cmachnfr", 0x3646F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -2510,7 +2510,7 @@
{ "cmachnfr", 0x3686F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
/* cmachnfr a,limm,limm 00110110000001101111111110AAAAAA. */
-{ "cmachnfr", 0x3606FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "cmachnfr", 0x3606FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
/* cmachnfr 0,limm,limm 00110110000001101111111110111110. */
{ "cmachnfr", 0x3606FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -2519,31 +2519,31 @@
{ "cmachnfr", 0x36C6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
/* cmacrdw<.f> a,b,c 00101bbb00100110FBBBCCCCCCAAAAAA. */
-{ "cmacrdw", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+{ "cmacrdw", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
/* cmacrdw<.f> 0,b,c 00101bbb00100110FBBBCCCCCC111110. */
{ "cmacrdw", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
/* cmacrdw<.f><.cc> b,b,c 00101bbb11100110FBBBCCCCCC0QQQQQ. */
-{ "cmacrdw", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "cmacrdw", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
/* cmacrdw<.f> a,b,u6 00101bbb01100110FBBBuuuuuuAAAAAA. */
-{ "cmacrdw", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "cmacrdw", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
/* cmacrdw<.f> 0,b,u6 00101bbb01100110FBBBuuuuuu111110. */
{ "cmacrdw", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
/* cmacrdw<.f><.cc> b,b,u6 00101bbb11100110FBBBuuuuuu1QQQQQ. */
-{ "cmacrdw", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "cmacrdw", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
/* cmacrdw<.f> b,b,s12 00101bbb10100110FBBBssssssSSSSSS. */
-{ "cmacrdw", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "cmacrdw", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
/* cmacrdw<.f> a,limm,c 0010111000100110F111CCCCCCAAAAAA. */
-{ "cmacrdw", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+{ "cmacrdw", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
/* cmacrdw<.f> a,b,limm 00101bbb00100110FBBB111110AAAAAA. */
-{ "cmacrdw", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+{ "cmacrdw", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
/* cmacrdw<.f> 0,limm,c 0010111000100110F111CCCCCC111110. */
{ "cmacrdw", 0x2E26703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
@@ -2555,10 +2555,10 @@
{ "cmacrdw", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
/* cmacrdw<.f><.cc> b,b,limm 00101bbb11100110FBBB1111100QQQQQ. */
-{ "cmacrdw", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+{ "cmacrdw", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
/* cmacrdw<.f> a,limm,u6 0010111001100110F111uuuuuuAAAAAA. */
-{ "cmacrdw", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "cmacrdw", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
/* cmacrdw<.f> 0,limm,u6 0010111001100110F111uuuuuu111110. */
{ "cmacrdw", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
@@ -2570,7 +2570,7 @@
{ "cmacrdw", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
/* cmacrdw<.f> a,limm,limm 0010111000100110F111111110AAAAAA. */
-{ "cmacrdw", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "cmacrdw", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
/* cmacrdw<.f> 0,limm,limm 0010111000100110F111111110111110. */
{ "cmacrdw", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
@@ -2639,31 +2639,31 @@
{ "cmp", 0x26CCFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }},
/* cmpychfr a,b,c 00110bbb000001011BBBCCCCCCAAAAAA. */
-{ "cmpychfr", 0x30058000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+{ "cmpychfr", 0x30058000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
/* cmpychfr 0,b,c 00110bbb000001011BBBCCCCCC111110. */
{ "cmpychfr", 0x3005803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
/* cmpychfr<.cc> b,b,c 00110bbb110001011BBBCCCCCC0QQQQQ. */
-{ "cmpychfr", 0x30C58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+{ "cmpychfr", 0x30C58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
/* cmpychfr a,b,u6 00110bbb010001011BBBuuuuuuAAAAAA. */
-{ "cmpychfr", 0x30458000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "cmpychfr", 0x30458000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
/* cmpychfr 0,b,u6 00110bbb010001011BBBuuuuuu111110. */
{ "cmpychfr", 0x3045803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
/* cmpychfr<.cc> b,b,u6 00110bbb110001011BBBuuuuuu1QQQQQ. */
-{ "cmpychfr", 0x30C58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+{ "cmpychfr", 0x30C58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
/* cmpychfr b,b,s12 00110bbb100001011BBBssssssSSSSSS. */
-{ "cmpychfr", 0x30858000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+{ "cmpychfr", 0x30858000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
/* cmpychfr a,limm,c 00110110000001011111CCCCCCAAAAAA. */
-{ "cmpychfr", 0x3605F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "cmpychfr", 0x3605F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
/* cmpychfr a,b,limm 00110bbb000001011BBB111110AAAAAA. */
-{ "cmpychfr", 0x30058F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "cmpychfr", 0x30058F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
/* cmpychfr 0,limm,c 00110110000001011111CCCCCC111110. */
{ "cmpychfr", 0x3605F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -2675,10 +2675,10 @@
{ "cmpychfr", 0x30C58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
/* cmpychfr<.cc> b,b,limm 00110110110001011111CCCCCC0QQQQQ. */
-{ "cmpychfr", 0x36C5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+{ "cmpychfr", 0x36C5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
/* cmpychfr a,limm,u6 00110110010001011111uuuuuuAAAAAA. */
-{ "cmpychfr", 0x3645F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "cmpychfr", 0x3645F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
/* cmpychfr 0,limm,u6 00110110010001011111uuuuuu111110. */
{ "cmpychfr", 0x3645F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -2690,7 +2690,7 @@
{ "cmpychfr", 0x3685F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
/* cmpychfr a,limm,limm 00110110000001011111111110AAAAAA. */
-{ "cmpychfr", 0x3605FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "cmpychfr", 0x3605FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
/* cmpychfr 0,limm,limm 00110110000001011111111110111110. */
{ "cmpychfr", 0x3605FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -2699,31 +2699,31 @@
{ "cmpychfr", 0x36C5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
/* cmpychnfr a,b,c 00110bbb000000101BBBCCCCCCAAAAAA. */
-{ "cmpychnfr", 0x30028000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+{ "cmpychnfr", 0x30028000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
/* cmpychnfr 0,b,c 00110bbb000000001BBBCCCCCC111110. */
{ "cmpychnfr", 0x3000803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
/* cmpychnfr<.cc> b,b,c 00110bbb110000001BBBCCCCCC0QQQQQ. */
-{ "cmpychnfr", 0x30C08000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+{ "cmpychnfr", 0x30C08000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
/* cmpychnfr a,b,u6 00110bbb010000001BBBuuuuuuAAAAAA. */
-{ "cmpychnfr", 0x30408000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "cmpychnfr", 0x30408000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
/* cmpychnfr 0,b,u6 00110bbb010000001BBBuuuuuu111110. */
{ "cmpychnfr", 0x3040803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
/* cmpychnfr<.cc> b,b,u6 00110bbb110000001BBBuuuuuu1QQQQQ. */
-{ "cmpychnfr", 0x30C08020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+{ "cmpychnfr", 0x30C08020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
/* cmpychnfr b,b,s12 00110bbb100000001BBBssssssSSSSSS. */
-{ "cmpychnfr", 0x30808000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+{ "cmpychnfr", 0x30808000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
/* cmpychnfr a,limm,c 00110110000000001111CCCCCCAAAAAA. */
-{ "cmpychnfr", 0x3600F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "cmpychnfr", 0x3600F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
/* cmpychnfr a,b,limm 00110bbb000000001BBB111110AAAAAA. */
-{ "cmpychnfr", 0x30008F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "cmpychnfr", 0x30008F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
/* cmpychnfr 0,limm,c 00110110000000001111CCCCCC111110. */
{ "cmpychnfr", 0x3600F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -2735,10 +2735,10 @@
{ "cmpychnfr", 0x30C08F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
/* cmpychnfr<.cc> b,b,limm 00110110110000001111CCCCCC0QQQQQ. */
-{ "cmpychnfr", 0x36C0F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+{ "cmpychnfr", 0x36C0F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
/* cmpychnfr a,limm,u6 00110110010000001111uuuuuuAAAAAA. */
-{ "cmpychnfr", 0x3640F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "cmpychnfr", 0x3640F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
/* cmpychnfr 0,limm,u6 00110110010000001111uuuuuu111110. */
{ "cmpychnfr", 0x3640F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -2750,7 +2750,7 @@
{ "cmpychnfr", 0x3680F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
/* cmpychnfr a,limm,limm 00110110000000001111111110AAAAAA. */
-{ "cmpychnfr", 0x3600FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "cmpychnfr", 0x3600FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
/* cmpychnfr 0,limm,limm 00110110000000001111111110111110. */
{ "cmpychnfr", 0x3600FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -2759,31 +2759,31 @@
{ "cmpychnfr", 0x36C0FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
/* cmpyhfmr a,b,c 00110bbb000110110BBBCCCCCCAAAAAA. */
-{ "cmpyhfmr", 0x301B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+{ "cmpyhfmr", 0x301B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
/* cmpyhfmr 0,b,c 00110bbb000110110BBBCCCCCC111110. */
{ "cmpyhfmr", 0x301B003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
/* cmpyhfmr<.cc> b,b,c 00110bbb110110110BBBCCCCCC0QQQQQ. */
-{ "cmpyhfmr", 0x30DB0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+{ "cmpyhfmr", 0x30DB0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
/* cmpyhfmr a,b,u6 00110bbb010110110BBBuuuuuuAAAAAA. */
-{ "cmpyhfmr", 0x305B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "cmpyhfmr", 0x305B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
/* cmpyhfmr 0,b,u6 00110bbb010110110BBBuuuuuu111110. */
{ "cmpyhfmr", 0x305B003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
/* cmpyhfmr<.cc> b,b,u6 00110bbb110110110BBBuuuuuu1QQQQQ. */
-{ "cmpyhfmr", 0x30DB0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+{ "cmpyhfmr", 0x30DB0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
/* cmpyhfmr b,b,s12 00110bbb100110110BBBssssssSSSSSS. */
-{ "cmpyhfmr", 0x309B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+{ "cmpyhfmr", 0x309B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
/* cmpyhfmr a,limm,c 00110110000110110111CCCCCCAAAAAA. */
-{ "cmpyhfmr", 0x361B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "cmpyhfmr", 0x361B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
/* cmpyhfmr a,b,limm 00110bbb000110110BBB111110AAAAAA. */
-{ "cmpyhfmr", 0x301B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "cmpyhfmr", 0x301B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
/* cmpyhfmr 0,limm,c 00110110000110110111CCCCCC111110. */
{ "cmpyhfmr", 0x361B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -2795,10 +2795,10 @@
{ "cmpyhfmr", 0x30DB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
/* cmpyhfmr<.cc> b,b,limm 00110110110110110111CCCCCC0QQQQQ. */
-{ "cmpyhfmr", 0x36DB7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+{ "cmpyhfmr", 0x36DB7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
/* cmpyhfmr a,limm,u6 00110110010110110111uuuuuuAAAAAA. */
-{ "cmpyhfmr", 0x365B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "cmpyhfmr", 0x365B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
/* cmpyhfmr 0,limm,u6 00110110010110110111uuuuuu111110. */
{ "cmpyhfmr", 0x365B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -2810,7 +2810,7 @@
{ "cmpyhfmr", 0x369B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
/* cmpyhfmr a,limm,limm 00110110000110110111111110AAAAAA. */
-{ "cmpyhfmr", 0x361B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "cmpyhfmr", 0x361B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
/* cmpyhfmr 0,limm,limm 00110110000110110111111110111110. */
{ "cmpyhfmr", 0x361B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -2819,31 +2819,31 @@
{ "cmpyhfmr", 0x36DB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
/* cmpyhfr a,b,c 00110bbb000000011BBBCCCCCCAAAAAA. */
-{ "cmpyhfr", 0x30018000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+{ "cmpyhfr", 0x30018000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
/* cmpyhfr 0,b,c 00110bbb000000011BBBCCCCCC111110. */
{ "cmpyhfr", 0x3001803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
/* cmpyhfr<.cc> b,b,c 00110bbb110000011BBBCCCCCC0QQQQQ. */
-{ "cmpyhfr", 0x30C18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+{ "cmpyhfr", 0x30C18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
/* cmpyhfr a,b,u6 00110bbb010000011BBBuuuuuuAAAAAA. */
-{ "cmpyhfr", 0x30418000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "cmpyhfr", 0x30418000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
/* cmpyhfr 0,b,u6 00110bbb010000011BBBuuuuuu111110. */
{ "cmpyhfr", 0x3041803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
/* cmpyhfr<.cc> b,b,u6 00110bbb110000011BBBuuuuuu1QQQQQ. */
-{ "cmpyhfr", 0x30C18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+{ "cmpyhfr", 0x30C18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
/* cmpyhfr b,b,s12 00110bbb100000011BBBssssssSSSSSS. */
-{ "cmpyhfr", 0x30818000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+{ "cmpyhfr", 0x30818000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
/* cmpyhfr a,limm,c 00110110000000011111CCCCCCAAAAAA. */
-{ "cmpyhfr", 0x3601F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "cmpyhfr", 0x3601F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
/* cmpyhfr a,b,limm 00110bbb000000011BBB111110AAAAAA. */
-{ "cmpyhfr", 0x30018F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "cmpyhfr", 0x30018F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
/* cmpyhfr 0,limm,c 00110110000000011111CCCCCC111110. */
{ "cmpyhfr", 0x3601F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -2855,10 +2855,10 @@
{ "cmpyhfr", 0x30C18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
/* cmpyhfr<.cc> b,b,limm 00110110110000011111CCCCCC0QQQQQ. */
-{ "cmpyhfr", 0x36C1F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+{ "cmpyhfr", 0x36C1F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
/* cmpyhfr a,limm,u6 00110110010000011111uuuuuuAAAAAA. */
-{ "cmpyhfr", 0x3641F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "cmpyhfr", 0x3641F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
/* cmpyhfr 0,limm,u6 00110110010000011111uuuuuu111110. */
{ "cmpyhfr", 0x3641F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -2870,7 +2870,7 @@
{ "cmpyhfr", 0x3681F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
/* cmpyhfr a,limm,limm 00110110000000011111111110AAAAAA. */
-{ "cmpyhfr", 0x3601FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "cmpyhfr", 0x3601FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
/* cmpyhfr 0,limm,limm 00110110000000011111111110111110. */
{ "cmpyhfr", 0x3601FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -2879,31 +2879,31 @@
{ "cmpyhfr", 0x36C1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
/* cmpyhnfr a,b,c 00110bbb000000001BBBCCCCCCAAAAAA. */
-{ "cmpyhnfr", 0x30008000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
+{ "cmpyhnfr", 0x30008000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
/* cmpyhnfr 0,b,c 00110bbb000000101BBBCCCCCC111110. */
{ "cmpyhnfr", 0x3002803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }},
/* cmpyhnfr<.cc> b,b,c 00110bbb110000101BBBCCCCCC0QQQQQ. */
-{ "cmpyhnfr", 0x30C28000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }},
+{ "cmpyhnfr", 0x30C28000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
/* cmpyhnfr a,b,u6 00110bbb010000101BBBuuuuuuAAAAAA. */
-{ "cmpyhnfr", 0x30428000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "cmpyhnfr", 0x30428000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
/* cmpyhnfr 0,b,u6 00110bbb010000101BBBuuuuuu111110. */
{ "cmpyhnfr", 0x3042803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
/* cmpyhnfr<.cc> b,b,u6 00110bbb110000101BBBuuuuuu1QQQQQ. */
-{ "cmpyhnfr", 0x30C28020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+{ "cmpyhnfr", 0x30C28020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
/* cmpyhnfr b,b,s12 00110bbb100000101BBBssssssSSSSSS. */
-{ "cmpyhnfr", 0x30828000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+{ "cmpyhnfr", 0x30828000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
/* cmpyhnfr a,limm,c 00110110000000101111CCCCCCAAAAAA. */
-{ "cmpyhnfr", 0x3602F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "cmpyhnfr", 0x3602F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
/* cmpyhnfr a,b,limm 00110bbb000000101BBB111110AAAAAA. */
-{ "cmpyhnfr", 0x30028F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "cmpyhnfr", 0x30028F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
/* cmpyhnfr 0,limm,c 00110110000000101111CCCCCC111110. */
{ "cmpyhnfr", 0x3602F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
@@ -2915,10 +2915,10 @@
{ "cmpyhnfr", 0x30C28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
/* cmpyhnfr<.cc> b,b,limm 00110110110000101111CCCCCC0QQQQQ. */
-{ "cmpyhnfr", 0x36C2F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }},
+{ "cmpyhnfr", 0x36C2F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
/* cmpyhnfr a,limm,u6 00110110010000101111uuuuuuAAAAAA. */
-{ "cmpyhnfr", 0x3642F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "cmpyhnfr", 0x3642F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
/* cmpyhnfr 0,limm,u6 00110110010000101111uuuuuu111110. */
{ "cmpyhnfr", 0x3642F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
@@ -2930,7 +2930,7 @@
{ "cmpyhnfr", 0x3682F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
/* cmpyhnfr a,limm,limm 00110110000000101111111110AAAAAA. */
-{ "cmpyhnfr", 0x3602FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "cmpyhnfr", 0x3602FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
/* cmpyhnfr 0,limm,limm 00110110000000101111111110111110. */
{ "cmpyhnfr", 0x3602FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
@@ -2960,31 +2960,31 @@
{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM_S, SIMM3_5_S }, { 0 }},
/* crc<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA. */
-{ "crc", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }},
+{ "crc", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
/* crc<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110. */
{ "crc", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }},
/* crc<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ. */
-{ "crc", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "crc", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
/* crc<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA. */
-{ "crc", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "crc", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
/* crc<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110. */
{ "crc", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
/* crc<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ. */
-{ "crc", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "crc", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
/* crc<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS. */
-{ "crc", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "crc", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
/* crc<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA. */
-{ "crc", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }},
+{ "crc", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
/* crc<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA. */
-{ "crc", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }},
+{ "crc", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
/* crc<.f> 0,limm,c 0010111000101100F111CCCCCC111110. */
{ "crc", 0x2E2C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
@@ -2996,10 +2996,10 @@
{ "crc", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
/* crc<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ. */
-{ "crc", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+{ "crc", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
/* crc<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA. */
-{ "crc", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "crc", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
/* crc<.f> 0,limm,u6 0010111001101100F111uuuuuu111110. */
{ "crc", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
@@ -3011,7 +3011,7 @@
{ "crc", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
/* crc<.f> a,limm,limm 0010111000101100F111111110AAAAAA. */
-{ "crc", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "crc", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
/* crc<.f> 0,limm,limm 0010111000101100F111111110111110. */
{ "crc", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
@@ -3743,64 +3743,64 @@
{ "dexcl2", 0x36FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DPA, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
/* div<.f> a,b,c 00101bbb00000100FBBBCCCCCCAAAAAA. */
-{ "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, RC }, { C_F }},
+{ "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
/* div<.f> 0,b,c 00101bbb00000100FBBBCCCCCC111110. */
-{ "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, RC }, { C_F }},
+{ "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
/* div<.f><.cc> b,b,c 00101bbb11000100FBBBCCCCCC0QQQQQ. */
-{ "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
/* div<.f> a,b,u6 00101bbb01000100FBBBuuuuuuAAAAAA. */
-{ "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, UIMM6_20 }, { C_F }},
+{ "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
/* div<.f> 0,b,u6 00101bbb01000100FBBBuuuuuu111110. */
-{ "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+{ "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
/* div<.f><.cc> b,b,u6 00101bbb11000100FBBBuuuuuu1QQQQQ. */
-{ "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
/* div<.f> b,b,s12 00101bbb10000100FBBBssssssSSSSSS. */
-{ "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
/* div<.f> a,limm,c 0010111000000100F111CCCCCCAAAAAA. */
-{ "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, RC }, { C_F }},
+{ "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
/* div<.f> a,b,limm 00101bbb00000100FBBB111110AAAAAA. */
-{ "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, LIMM }, { C_F }},
+{ "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
/* div<.f> 0,limm,c 0010111000000100F111CCCCCC111110. */
-{ "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F }},
+{ "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }},
/* div<.f> 0,b,limm 00101bbb00000100FBBB111110111110. */
-{ "div", 0x28040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, LIMM }, { C_F }},
+{ "div", 0x28040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, LIMM }, { C_F }},
/* div<.f><.cc> b,b,limm 00101bbb11000100FBBB1111100QQQQQ. */
-{ "div", 0x28C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, LIMM }, { C_F, C_CC }},
+{ "div", 0x28C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
/* div<.f><.cc> 0,limm,c 0010111011000100F111CCCCCC0QQQQQ. */
-{ "div", 0x2EC47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+{ "div", 0x2EC47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
/* div<.f> a,limm,u6 0010111001000100F111uuuuuuAAAAAA. */
-{ "div", 0x2E447000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "div", 0x2E447000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
/* div<.f> 0,limm,u6 0010111001000100F111uuuuuu111110. */
-{ "div", 0x2E44703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+{ "div", 0x2E44703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
/* div<.f><.cc> 0,limm,u6 0010111011000100F111uuuuuu1QQQQQ. */
-{ "div", 0x2EC47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+{ "div", 0x2EC47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
/* div<.f> 0,limm,s12 0010111010000100F111ssssssSSSSSS. */
-{ "div", 0x2E847000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+{ "div", 0x2E847000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
/* div<.f> a,limm,limm 0010111000000100F111111110AAAAAA. */
-{ "div", 0x2E047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, LIMMdup }, { C_F }},
+{ "div", 0x2E047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
/* div<.f> 0,limm,limm 0010111000000100F111111110111110. */
-{ "div", 0x2E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+{ "div", 0x2E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
/* div<.f><.cc> 0,limm,limm 0010111011000100F1111111100QQQQQ. */
-{ "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+{ "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
/* divacc c 00101011001011110000CCCCCC111111. */
{ "divacc", 0x2B2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }},
@@ -3869,151 +3869,151 @@
{ "divaw", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
/* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA. */
-{ "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, RC }, { C_F }},
+{ "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
/* divu<.f> 0,b,c 00101bbb00000101FBBBCCCCCC111110. */
-{ "divu", 0x2805003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, RC }, { C_F }},
+{ "divu", 0x2805003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
/* divu<.f><.cc> b,b,c 00101bbb11000101FBBBCCCCCC0QQQQQ. */
-{ "divu", 0x28C50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "divu", 0x28C50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
/* divu<.f> a,b,u6 00101bbb01000101FBBBuuuuuuAAAAAA. */
-{ "divu", 0x28450000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, UIMM6_20 }, { C_F }},
+{ "divu", 0x28450000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
/* divu<.f> 0,b,u6 00101bbb01000101FBBBuuuuuu111110. */
-{ "divu", 0x2845003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+{ "divu", 0x2845003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
/* divu<.f><.cc> b,b,u6 00101bbb11000101FBBBuuuuuu1QQQQQ. */
-{ "divu", 0x28C50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "divu", 0x28C50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
/* divu<.f> b,b,s12 00101bbb10000101FBBBssssssSSSSSS. */
-{ "divu", 0x28850000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "divu", 0x28850000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
/* divu<.f> a,limm,c 0010111000000101F111CCCCCCAAAAAA. */
-{ "divu", 0x2E057000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, RC }, { C_F }},
+{ "divu", 0x2E057000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},[...]
[diff truncated at 100000 bytes]