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[binutils-gdb] [AArch64][SVE 29/32] Add new SVE core & FP register operands
- From: Richard Sandiford <rsandifo at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 21 Sep 2016 16:06:10 -0000
- Subject: [binutils-gdb] [AArch64][SVE 29/32] Add new SVE core & FP register operands
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=047cd301d40288d13e44f3322541ac28ebe06078
commit 047cd301d40288d13e44f3322541ac28ebe06078
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Wed Sep 21 16:57:43 2016 +0100
[AArch64][SVE 29/32] Add new SVE core & FP register operands
SVE uses some new fields to store W, X and scalar FP registers.
This patch adds corresponding operands.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
(AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
(AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
and FP register operands.
* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
(FLD_SVE_Vn): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(aarch64_print_operand): Handle the new SVE core and FP register
operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm-2.c: Likewise.
* aarch64-dis-2.c: Likewise.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE core
and FP register operands.
Diff:
---
gas/ChangeLog | 5 +++++
gas/config/tc-aarch64.c | 6 ++++++
include/ChangeLog | 6 ++++++
include/opcode/aarch64.h | 6 ++++++
opcodes/ChangeLog | 13 +++++++++++++
opcodes/aarch64-asm-2.c | 26 ++++++++++++++++----------
opcodes/aarch64-dis-2.c | 26 ++++++++++++++++----------
opcodes/aarch64-opc-2.c | 6 ++++++
opcodes/aarch64-opc.c | 11 +++++++++++
opcodes/aarch64-opc.h | 5 +++++
opcodes/aarch64-tbl.h | 8 ++++++++
11 files changed, 98 insertions(+), 20 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 53faa4e..7f5f484 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+ * config/tc-aarch64.c (parse_operands): Handle the new SVE core
+ and FP register operands.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
* config/tc-aarch64.c (double_precision_operand_p): New function.
(parse_operands): Use it to calculate the dp_p input to
parse_aarch64_imm_float. Handle the new SVE FP immediate operands.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 01c8000..b9a988b 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5292,11 +5292,13 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Ra:
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_PAIRREG:
+ case AARCH64_OPND_SVE_Rm:
po_int_reg_or_fail (REG_TYPE_R_Z);
break;
case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP:
+ case AARCH64_OPND_SVE_Rn_SP:
po_int_reg_or_fail (REG_TYPE_R_SP);
break;
@@ -5328,6 +5330,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Sd:
case AARCH64_OPND_Sn:
case AARCH64_OPND_Sm:
+ case AARCH64_OPND_SVE_VZn:
+ case AARCH64_OPND_SVE_Vd:
+ case AARCH64_OPND_SVE_Vm:
+ case AARCH64_OPND_SVE_Vn:
val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
if (val == PARSE_FAIL)
{
diff --git a/include/ChangeLog b/include/ChangeLog
index 80016dc..2bde162 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,11 @@
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+ * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
+ (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
+ (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
* opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
(AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
(AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9e7f5b5..8d3fb21 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -310,6 +310,8 @@ enum aarch64_opnd
AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
+ AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
+ AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
@@ -322,6 +324,10 @@ enum aarch64_opnd
AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
+ AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
+ AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
+ AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
+ AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c94752c..967de6f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,18 @@
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
+ and FP register operands.
+ * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
+ (FLD_SVE_Vn): New aarch64_field_kinds.
+ * aarch64-opc.c (fields): Add corresponding entries.
+ (aarch64_print_operand): Handle the new SVE core and FP register
+ operands.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-asm-2.c: Likewise.
+ * aarch64-dis-2.c: Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
immediate operands.
* aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index d9d1981..5dd6a81 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -488,13 +488,19 @@ aarch64_insert_operand (const aarch64_operand *self,
case 144:
case 145:
case 146:
- case 159:
- case 160:
+ case 147:
+ case 148:
case 161:
case 162:
case 163:
case 164:
+ case 165:
+ case 166:
case 167:
+ case 168:
+ case 169:
+ case 170:
+ case 173:
return aarch64_ins_regno (self, info, code, inst);
case 12:
return aarch64_ins_reg_extended (self, info, code, inst);
@@ -534,14 +540,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 71:
case 136:
case 138:
- case 151:
- case 152:
case 153:
case 154:
case 155:
case 156:
case 157:
case 158:
+ case 159:
+ case 160:
return aarch64_ins_imm (self, info, code, inst);
case 38:
case 39:
@@ -657,16 +663,16 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_limm_mov (self, info, code, inst);
case 137:
return aarch64_ins_sve_scale (self, info, code, inst);
- case 147:
- case 148:
- return aarch64_ins_sve_shlimm (self, info, code, inst);
case 149:
case 150:
+ return aarch64_ins_sve_shlimm (self, info, code, inst);
+ case 151:
+ case 152:
return aarch64_ins_sve_shrimm (self, info, code, inst);
- case 165:
+ case 171:
return aarch64_ins_sve_index (self, info, code, inst);
- case 166:
- case 168:
+ case 172:
+ case 174:
return aarch64_ins_sve_reglist (self, info, code, inst);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 110cf2e..c3bcfdb 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -10434,13 +10434,19 @@ aarch64_extract_operand (const aarch64_operand *self,
case 144:
case 145:
case 146:
- case 159:
- case 160:
+ case 147:
+ case 148:
case 161:
case 162:
case 163:
case 164:
+ case 165:
+ case 166:
case 167:
+ case 168:
+ case 169:
+ case 170:
+ case 173:
return aarch64_ext_regno (self, info, code, inst);
case 8:
return aarch64_ext_regrt_sysins (self, info, code, inst);
@@ -10485,14 +10491,14 @@ aarch64_extract_operand (const aarch64_operand *self,
case 71:
case 136:
case 138:
- case 151:
- case 152:
case 153:
case 154:
case 155:
case 156:
case 157:
case 158:
+ case 159:
+ case 160:
return aarch64_ext_imm (self, info, code, inst);
case 38:
case 39:
@@ -10610,16 +10616,16 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_sve_limm_mov (self, info, code, inst);
case 137:
return aarch64_ext_sve_scale (self, info, code, inst);
- case 147:
- case 148:
- return aarch64_ext_sve_shlimm (self, info, code, inst);
case 149:
case 150:
+ return aarch64_ext_sve_shlimm (self, info, code, inst);
+ case 151:
+ case 152:
return aarch64_ext_sve_shrimm (self, info, code, inst);
- case 165:
+ case 171:
return aarch64_ext_sve_index (self, info, code, inst);
- case 166:
- case 168:
+ case 172:
+ case 174:
return aarch64_ext_sve_reglist (self, info, code, inst);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 58c3aed..6028be4 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -171,6 +171,8 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pm}, "an SVE predicate register"},
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register"},
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rm}, "an integer register or zero"},
+ {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
@@ -183,6 +185,10 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3}, "an 8-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vn}, "a SIMD register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index db744af..47c5079 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -273,6 +273,11 @@ const aarch64_field fields[] =
{ 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
{ 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
{ 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
+ { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
+ { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
+ { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
+ { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
+ { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
{ 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
{ 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
{ 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
@@ -2949,6 +2954,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_Ra:
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_PAIRREG:
+ case AARCH64_OPND_SVE_Rm:
/* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
the <ic_op>, therefore we we use opnd->present to override the
generic optional-ness information. */
@@ -2966,6 +2972,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP:
+ case AARCH64_OPND_SVE_Rn_SP:
assert (opnd->qualifier == AARCH64_OPND_QLF_W
|| opnd->qualifier == AARCH64_OPND_QLF_WSP
|| opnd->qualifier == AARCH64_OPND_QLF_X
@@ -3028,6 +3035,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_Sd:
case AARCH64_OPND_Sn:
case AARCH64_OPND_Sm:
+ case AARCH64_OPND_SVE_VZn:
+ case AARCH64_OPND_SVE_Vd:
+ case AARCH64_OPND_SVE_Vm:
+ case AARCH64_OPND_SVE_Vn:
snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
opnd->reg.regno);
break;
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 6c67786..a7654d0 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -100,6 +100,11 @@ enum aarch64_field_kind
FLD_SVE_Pm,
FLD_SVE_Pn,
FLD_SVE_Pt,
+ FLD_SVE_Rm,
+ FLD_SVE_Rn,
+ FLD_SVE_Vd,
+ FLD_SVE_Vm,
+ FLD_SVE_Vn,
FLD_SVE_Za_5,
FLD_SVE_Za_16,
FLD_SVE_Zd,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 367e42b..f2d5a46 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2970,6 +2970,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
"an SVE predicate register") \
Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD_SVE_Pt), \
"an SVE predicate register") \
+ Y(INT_REG, regno, "SVE_Rm", 0, F(FLD_SVE_Rm), \
+ "an integer register or zero") \
+ Y(INT_REG, regno, "SVE_Rn_SP", OPD_F_MAYBE_SP, F(FLD_SVE_Rn), \
+ "an integer register or SP") \
Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_PRED", 0, \
F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \
Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \
@@ -2994,6 +2998,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
"an 8-bit unsigned immediate") \
Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3), \
"an 8-bit unsigned immediate") \
+ Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \
+ Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \
+ Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD_SVE_Vm), "a SIMD register") \
+ Y(SIMD_REG, regno, "SVE_Vn", 0, F(FLD_SVE_Vn), "a SIMD register") \
Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \
"an SVE vector register") \
Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \