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[binutils-gdb] [AArch64][2/6] LD support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC

From: Jiong Wang <jiwang at sourceware dot org>
To: bfd-cvs at sourceware dot org
Date: 19 Aug 2015 15:59:40 -0000
Subject: [binutils-gdb] [AArch64][2/6] LD support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=753999c1ec8fa76bd5ed5509d1e5909d010e80ee

commit 753999c1ec8fa76bd5ed5509d1e5909d010e80ee
Author: Jiong Wang <jiong.wang@arm.com>
Date:   Wed Aug 19 10:58:13 2015 +0100

    [AArch64][2/6] LD support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
    
    2015-08-19  Jiong Wang  <jiong.wang@arm.com>
    
    bfd/
      * elfnn-aarch64.c (IS_AARCH64_TLS_RELOC): Recognize
      BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC.
      (aarch64_reloc_got_type): Likewise.
      (elfNN_aarch64_final_link_relocate): Likewise.
      (elfNN_aarch64_relocate_section): Likewise.
      * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise.
      (_bfd_aarch64_elf_resolve_relocation): Likewise.
    
    ld/testsuite/
      * ld-aarch64/emit-relocs-530.s: New testcase.
      * ld-aarch64/emit-relocs-92.s: Likewise.
      * ld-aarch64/emit-relocs-530.d: New expectation file.
      * ld-aarch64/emit-relocs-92.d: Likewise.
      * ld-aarch64/aarch64-elf.exp: Run new testcases.

Diff:
---
 bfd/ChangeLog                             | 10 ++++++++++
 bfd/elfnn-aarch64.c                       |  2 ++
 bfd/elfxx-aarch64.c                       |  2 ++
 ld/testsuite/ChangeLog                    |  8 ++++++++
 ld/testsuite/ld-aarch64/aarch64-elf.exp   |  2 ++
 ld/testsuite/ld-aarch64/emit-relocs-530.d |  7 +++++++
 ld/testsuite/ld-aarch64/emit-relocs-530.s | 10 ++++++++++
 ld/testsuite/ld-aarch64/emit-relocs-92.d  |  8 ++++++++
 ld/testsuite/ld-aarch64/emit-relocs-92.s  | 10 ++++++++++
 9 files changed, 59 insertions(+)

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 772336f..a6491e1 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,5 +1,15 @@
 2015-08-19  Jiong Wang  <jiong.wang@arm.com>
 
+	* elfnn-aarch64.c (IS_AARCH64_TLS_RELOC): Recognize
+	BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC.
+	(aarch64_reloc_got_type): Likewise.
+	(elfNN_aarch64_final_link_relocate): Likewise.
+	(elfNN_aarch64_relocate_section): Likewise.
+	* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise.
+	(_bfd_aarch64_elf_resolve_relocation): Likewise.
+
+2015-08-19  Jiong Wang  <jiong.wang@arm.com>
+
 	* reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC): New entry.
 	* bfd-in2.h: Regenerate.
 	* libbfd.h: Regenerate.
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index 9277261..962a10e 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -175,6 +175,7 @@
    || (R_TYPE) == BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC	\
    || (R_TYPE) == BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1	\
    || (R_TYPE) == BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12	\
+   || (R_TYPE) == BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC	\
    || (R_TYPE) == BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC		\
    || (R_TYPE) == BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21		\
    || (R_TYPE) == BFD_RELOC_AARCH64_TLSLD_ADR_PREL21		\
@@ -5093,6 +5094,7 @@ elfNN_aarch64_final_link_relocate (reloc_howto_type *howto,
       break;
 
     case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
       value = _bfd_aarch64_elf_resolve_relocation (bfd_r_type, place, value,
 						   signed_addend - dtpoff_base (info),
 						   weak_undef_p);
diff --git a/bfd/elfxx-aarch64.c b/bfd/elfxx-aarch64.c
index 69dac6d..dbb134a 100644
--- a/bfd/elfxx-aarch64.c
+++ b/bfd/elfxx-aarch64.c
@@ -250,6 +250,7 @@ _bfd_aarch64_elf_put_addend (bfd *abfd,
     case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
     case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
     case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
     case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
@@ -400,6 +401,7 @@ _bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type,
     case BFD_RELOC_AARCH64_MOVW_G2_S:
     case BFD_RELOC_AARCH64_MOVW_G3:
     case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
       value = value + addend;
       break;
 
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index ce3b310..edf5b7a 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2015-08-19  Jiong Wang  <jiong.wang@arm.com>
+
+	* ld-aarch64/emit-relocs-530.s: New testcase.
+	* ld-aarch64/emit-relocs-92.s: Likewise.
+	* ld-aarch64/emit-relocs-530.d: New expectation file.
+	* ld-aarch64/emit-relocs-92.d: Likewise.
+	* ld-aarch64/aarch64-elf.exp: Run new testcases.
+
 2015-08-18  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR ld/18841
diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp
index 15247dc..bb8f4c2 100644
--- a/ld/testsuite/ld-aarch64/aarch64-elf.exp
+++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp
@@ -68,6 +68,7 @@ run_dump_test "weak-undefined"
 run_dump_test "emit-relocs-28"
 run_dump_test "emit-relocs-86"
 run_dump_test "emit-relocs-86-overflow"
+run_dump_test "emit-relocs-92"
 run_dump_test "emit-relocs-257"
 run_dump_test "emit-relocs-257-be"
 # 258 is tested in 257
@@ -120,6 +121,7 @@ run_dump_test "emit-relocs-312"
 run_dump_test "emit-relocs-313"
 run_dump_test "emit-relocs-529"
 run_dump_test "emit-relocs-529-overflow"
+run_dump_test "emit-relocs-530"
 
 # test addend correctness when --emit-relocs specified for non-relocatable obj.
 run_dump_test "emit-relocs-local-addend"
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-530.d b/ld/testsuite/ld-aarch64/emit-relocs-530.d
new file mode 100644
index 0000000..fc70bcc
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-530.d
@@ -0,0 +1,7 @@
+#source: emit-relocs-530.s
+#ld: -T relocs.ld -e0 --emit-relocs
+#objdump: -dr
+#...
+0000000000010000 <.text>:
+   10000:	91001134 	add	x20, x9, #0x4
+			10000: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC	v2
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-530.s b/ld/testsuite/ld-aarch64/emit-relocs-530.s
new file mode 100644
index 0000000..72af8b2
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-530.s
@@ -0,0 +1,10 @@
+	.global	v1
+	.global	v2
+	.section	.tdata,"awT",%progbits
+v1:
+	.word	0xdeaddead
+v2:
+	.word	0xcafecafe
+
+	.text
+	add	x20, x9, #:dtprel_lo12_nc:v2
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-92.d b/ld/testsuite/ld-aarch64/emit-relocs-92.d
new file mode 100644
index 0000000..0ff532b
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-92.d
@@ -0,0 +1,8 @@
+#source: emit-relocs-92.s
+#as: -mabi=ilp32
+#ld: -m [aarch64_choose_ilp32_emul] -e0 --emit-relocs
+#objdump: -dr
+#...
+.* <.text>:
+  .*:	11001134 	add	w20, w9, #0x4
+			.*: R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC	v2
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-92.s b/ld/testsuite/ld-aarch64/emit-relocs-92.s
new file mode 100644
index 0000000..14b6206
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/emit-relocs-92.s
@@ -0,0 +1,10 @@
+	.global	v1
+	.global	v2
+	.section	.tdata,"awT",%progbits
+v1:
+	.word	0xdeaddead
+v2:
+	.word	0xcafecafe
+
+	.text
+	add	w20, w9, #:dtprel_lo12_nc:v2
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