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[binutils-gdb] Remove trailing spaces in gas
- From: H.J.Lu <hjl at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 12 Aug 2015 11:47:23 -0000
- Subject: [binutils-gdb] Remove trailing spaces in gas
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3739860c11a9cfcdaa4d5d204ea3536784de7bb3
commit 3739860c11a9cfcdaa4d5d204ea3536784de7bb3
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Wed Aug 12 04:40:42 2015 -0700
Remove trailing spaces in gas
Diff:
---
gas/ChangeLog-2005 | 6 +-
gas/ChangeLog-2006 | 4 +-
gas/ChangeLog-2010 | 2 +-
gas/ChangeLog-9295 | 24 +++----
gas/README | 4 +-
gas/config/atof-ieee.c | 2 +-
gas/config/atof-vax.c | 2 +-
gas/config/m68k-parse.y | 18 ++---
gas/config/obj-coff.h | 8 +--
gas/config/obj-elf.c | 2 +-
gas/config/obj-evax.c | 6 +-
gas/config/obj-macho.c | 122 ++++++++++++++++----------------
gas/config/obj-macho.h | 2 +-
gas/config/rl78-defs.h | 2 +-
gas/config/rl78-parse.y | 2 +-
gas/config/rx-parse.y | 2 +-
gas/config/tc-alpha.c | 30 ++++----
gas/config/tc-arm.c | 8 +--
gas/config/tc-cr16.c | 12 ++--
gas/config/tc-cr16.h | 4 +-
gas/config/tc-cris.c | 4 +-
gas/config/tc-crx.c | 112 ++++++++++++++---------------
gas/config/tc-crx.h | 4 +-
gas/config/tc-dlx.c | 2 +-
gas/config/tc-frv.c | 68 +++++++++---------
gas/config/tc-h8300.c | 50 ++++++-------
gas/config/tc-i370.c | 2 +-
gas/config/tc-i386.c | 2 +-
gas/config/tc-i860.c | 10 +--
gas/config/tc-i960.c | 10 +--
gas/config/tc-ia64.c | 28 ++++----
gas/config/tc-ip2k.c | 12 ++--
gas/config/tc-m32c.c | 26 +++----
gas/config/tc-m32r.c | 12 ++--
gas/config/tc-m32r.h | 2 +-
gas/config/tc-m68hc11.c | 34 ++++-----
gas/config/tc-m68k.c | 80 ++++++++++-----------
gas/config/tc-mcore.c | 2 +-
gas/config/tc-mep.c | 38 +++++-----
gas/config/tc-mep.h | 2 +-
gas/config/tc-microblaze.h | 4 +-
gas/config/tc-mips.c | 22 +++---
gas/config/tc-mmix.c | 4 +-
gas/config/tc-mn10300.c | 14 ++--
gas/config/tc-moxie.c | 10 +--
gas/config/tc-msp430.c | 116 +++++++++++++++----------------
gas/config/tc-mt.c | 34 ++++-----
gas/config/tc-mt.h | 2 +-
gas/config/tc-nios2.c | 170 ++++++++++++++++++++++-----------------------
gas/config/tc-ns32k.c | 2 +-
gas/config/tc-ppc.c | 4 +-
gas/config/tc-rl78.c | 4 +-
gas/config/tc-rx.c | 2 +-
gas/config/tc-s390.c | 2 +-
gas/config/tc-score.h | 4 +-
gas/config/tc-sh.c | 8 +--
gas/config/tc-sparc.c | 2 +-
gas/config/tc-spu.c | 22 +++---
gas/config/tc-tic30.c | 2 +-
gas/config/tc-tic4x.c | 104 +++++++++++++--------------
gas/config/tc-tic4x.h | 2 +-
gas/config/tc-tic6x.c | 10 +--
gas/config/tc-v850.c | 2 +-
gas/config/tc-vax.c | 110 ++++++++++++++---------------
gas/config/tc-xc16x.c | 4 +-
gas/config/tc-xc16x.h | 2 +-
gas/config/tc-xstormy16.c | 6 +-
gas/config/tc-xtensa.c | 50 ++++++-------
gas/config/tc-xtensa.h | 4 +-
gas/config/tc-z80.c | 20 +++---
gas/config/tc-z80.h | 2 +-
gas/config/te-generic.h | 2 +-
gas/config/te-vms.c | 2 +-
gas/config/xtensa-relax.c | 10 +--
gas/configure.ac | 4 +-
gas/configure.com | 8 +--
gas/configure.tgt | 8 +--
gas/dwarf2dbg.c | 2 +-
gas/itbl-lex.l | 22 +++---
gas/itbl-parse.y | 56 +++++++--------
gas/makefile.vms | 4 +-
81 files changed, 812 insertions(+), 812 deletions(-)
diff --git a/gas/ChangeLog-2005 b/gas/ChangeLog-2005
index 9cac534..49ad117 100644
--- a/gas/ChangeLog-2005
+++ b/gas/ChangeLog-2005
@@ -177,9 +177,9 @@
* config/tc-z80.c (z80_start_line_hook): issue an error when
redefining a symbol with equ
- * doc/as.texinfo(equ<z80>): mention difference with .equiv
- * doc/as.texinfo(err): fix typo
- * doc/c-z80.texi(equ): redefining a symbol with equ is no longer
+ * doc/as.texinfo(equ<z80>): mention difference with .equiv
+ * doc/as.texinfo(err): fix typo
+ * doc/c-z80.texi(equ): redefining a symbol with equ is no longer
allowed
2005-11-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
diff --git a/gas/ChangeLog-2006 b/gas/ChangeLog-2006
index b29de41..049f465 100644
--- a/gas/ChangeLog-2006
+++ b/gas/ChangeLog-2006
@@ -56,9 +56,9 @@
Delete the code handling large constant for PIC.
Modify some comments.
(score_relax_frag): Decrease insn_addr in certain situation.
- (s_score_cprestore): Change .cprestore syntax from ".cprestore offset"
+ (s_score_cprestore): Change .cprestore syntax from ".cprestore offset"
to ".cprestore reg, offset".
-
+
2006-12-23 Kazu Hirata <kazu@codesourcery.com>
* configure.tgt: Recognize fido.
diff --git a/gas/ChangeLog-2010 b/gas/ChangeLog-2010
index fd2fc4f..4ca9833 100644
--- a/gas/ChangeLog-2010
+++ b/gas/ChangeLog-2010
@@ -115,7 +115,7 @@
* config/tc-mips.c (mips_ip) <'('>: Don't let '4', '5' or '-'
as a base register specifier.
-
+
2010-12-09 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (macro) <M_S_DOB>: Fix the placement of code.
diff --git a/gas/ChangeLog-9295 b/gas/ChangeLog-9295
index b8a25fe..c84475b 100644
--- a/gas/ChangeLog-9295
+++ b/gas/ChangeLog-9295
@@ -491,7 +491,7 @@ Tue Oct 24 14:50:38 1995 Michael Meissner <meissner@tiktok.cygnus.com>
(fixup_segment): Use MD_PCREL_FROM_SECTION instead of
md_pcrel_from, and TC_FORCE_RELOCATION_SECTION instead of
TC_FORCE_RELOCATION.
-
+
Mon Oct 23 16:20:04 1995 Ken Raeburn <raeburn@cygnus.com>
* input-scrub.c (as_where): Set name to null pointer if we don't
@@ -509,7 +509,7 @@ Mon Oct 23 11:15:44 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
accepting the 4100 as a MIPS architecture variant (md_begin,
macro_build, mips_ip, md_parse_option). Adding suitable
command-line OPTIONs, and updating the help text (md_show_usage).
-
+
Wed Oct 18 13:20:32 1995 Ken Raeburn <raeburn@cygnus.com>
* subsegs.c (subseg_begin): Only set absolute_frchain.fix_* when
@@ -774,7 +774,7 @@ Thu Sep 28 19:25:04 1995 Stan Shebs <shebs@andros.cygnus.com>
Thu Sep 28 15:43:15 1995 Kim Knuttila <krk@nellie>
- * config/tc-ppc.c (md_apply_fix3): Removed some TE_PE specific
+ * config/tc-ppc.c (md_apply_fix3): Removed some TE_PE specific
manipulations, since I can't prove they're needed.
(md_begin): Removed init_regtable, insert_reg, and the call points.
(register_name): New function. Parses a register name, if appropriate.
@@ -843,7 +843,7 @@ Wed Sep 27 10:29:13 1995 Kim Knuttila <krk@nellie>
Added support for more predefined sections
(ppc_frob_section): Removed some xcoff specific processing from TE_PE
(ppc_fix_adjustable): Removed from TE_PE mainline
- (md_apply_fix3): For TE_PE toc entries, we don't need to mess
+ (md_apply_fix3): For TE_PE toc entries, we don't need to mess
with fx_addnumber. Removed for the time being.
(lots): Put back missing assignments to ppc_current_csect.
@@ -871,7 +871,7 @@ Mon Sep 25 16:08:43 1995 Michael Meissner <meissner@tiktok.cygnus.com>
(md_assemble): Be more robust in terms of relocations.
(md_apply_fix3): Allow 14 bit relocs to be emitted for external
symbols in addition to 26 bit relocs. Properly insert 26/14 bit
- reloc value fields into the instruction stream.
+ reloc value fields into the instruction stream.
Mon Sep 25 00:23:16 1995 Ian Lance Taylor <ian@cygnus.com>
@@ -1618,7 +1618,7 @@ Thu Aug 10 00:38:11 1995 Ian Lance Taylor <ian@cygnus.com>
(build_Mytes, md_atof): Likewise.
(md_convert_frag, md_apply_fix): Likewise.
(md_number_to_chars): Likewise.
-
+
Wed Aug 9 10:51:48 1995 Ian Lance Taylor <ian@cygnus.com>
* config/tc-m68k.c (m68k_abspcadd): New static variable.
@@ -1946,7 +1946,7 @@ Mon Jul 31 18:19:26 1995 steve chamberlain <sac@slash.cygnus.com>
* gasp.c (main): Parse -I option.
(do_include): Look through include list.
- * gasp.c (change_base): Don't modify numbers in strings.
+ * gasp.c (change_base): Don't modify numbers in strings.
Mon Jul 31 12:16:21 1995 Ian Lance Taylor <ian@cygnus.com>
@@ -2253,7 +2253,7 @@ Fri Jul 7 11:17:27 1995 Ian Lance Taylor <ian@cygnus.com>
Add SPARC ELF PIC support.
* write.c (fixup_segment): Pass fixP to TC_RELOC_RTSYM_LOC_FIXUP,
not fixP->fx_r_type.
- * config/tc-sparc.c (sparc_pic_code): New global variable.
+ * config/tc-sparc.c (sparc_pic_code): New global variable.
(md_apply_fix): If generating PIC, adjust fx_addnumber for any non
PC relative reloc.
(tc_gen_reloc): If generating PIC, adjust various reloc types.
@@ -2392,7 +2392,7 @@ Wed Jul 5 12:01:49 1995 Ian Lance Taylor <ian@cygnus.com>
(s_stringer, s_mips_space): Remove unneeded declarations.
(md_parse_option): In case 'g', set mips_debug to debugging level.
(mips_local_label): New function.
- * config/tc-mips.h (LOCAL_LABEL): Call mips_local_label.
+ * config/tc-mips.h (LOCAL_LABEL): Call mips_local_label.
(mips_local_label): Declare.
Wed Jul 5 00:59:22 1995 Fred Fish (fnf@cygnus.com)
@@ -12364,7 +12364,7 @@ Tue Nov 10 09:49:24 1992 Ian Lance Taylor (ian@cygnus.com)
* config/atof-ieee.c, config/atof-ns32k.c, config/tc-*.c: made
EXP_CHARS, FLT_CHARS, comment_chars, line_comment_chars and
line_seperator_chars consistently const, and always
- initialized them. Included read.h.
+ initialized them. Included read.h.
Thu Nov 5 17:55:41 1992 Jim Wilson (wilson@sphagnum.cygnus.com)
@@ -12452,7 +12452,7 @@ Tue Sep 29 10:51:55 1992 Ian Lance Taylor (ian@cygnus.com)
* config/tc-i960.h, config/tc-i960.c: avoid the ANSI
preprocessor addition #elif, since it is not supported by old
- compilers.
+ compilers.
config/ho-rs6000.h, config/tc-m68k.c: the native RS/6000
compiler miscompiles a couple of expressions in tc-m68k.c.
@@ -12561,7 +12561,7 @@ Wed Sep 9 11:06:25 1992 Ian Lance Taylor (ian@cygnus.com)
file.
* config/tc-m68kmote.c, config/tc-m68kmote.h: removed now
superfluous files.
-
+
From Steve Chamberlain:
* config/m68kcoff.mt: for m68k COFF.
* config/obj-coffbfd.c: (fixup_mdeps) added
diff --git a/gas/README b/gas/README
index 248db73..cc48ce7 100644
--- a/gas/README
+++ b/gas/README
@@ -52,7 +52,7 @@ three pieces of information in the following pattern:
`sparc-sun-sunos4'.
The `configure' script accompanying GAS does not provide any query
-facility to list all supported host and target names or aliases.
+facility to list all supported host and target names or aliases.
`configure' calls the Bourne shell script `config.sub' to map
abbreviations to full names; you can read the script, if you wish, or
you can use it to test your guesses on abbreviations--for example:
@@ -108,7 +108,7 @@ prefer; but you may abbreviate option names if you use `--'.
targets.
`--enable-OPTION'
- These flags tell the program or library being configured to
+ These flags tell the program or library being configured to
configure itself differently from the default for the specified
host/target combination. See below for a list of `--enable'
options recognized in the gas distribution.
diff --git a/gas/config/atof-ieee.c b/gas/config/atof-ieee.c
index 33aae16..04d6e6b 100644
--- a/gas/config/atof-ieee.c
+++ b/gas/config/atof-ieee.c
@@ -701,7 +701,7 @@ extern const char FLT_CHARS[];
/* This is a utility function called from various tc-*.c files. It
is here in order to reduce code duplication.
-
+
Turn a string at input_line_pointer into a floating point constant
of type TYPE (a character found in the FLT_CHARS macro), and store
it as LITTLENUMS in the bytes buffer LITP. The number of chars
diff --git a/gas/config/atof-vax.c b/gas/config/atof-vax.c
index 37f5fcc..287c487 100644
--- a/gas/config/atof-vax.c
+++ b/gas/config/atof-vax.c
@@ -379,7 +379,7 @@ flonum_gen2vax (int format_letter, /* One of 'd' 'f' 'g' 'h'. */
Address of where to build floating point literal.
Assumed to be 'big enough'.
Address of where to return size of literal (in chars).
-
+
Out: Input_line_pointer->of next char after floating number.
Error message, or 0.
Floating point literal.
diff --git a/gas/config/m68k-parse.y b/gas/config/m68k-parse.y
index bdf57a2..43c7ee3 100644
--- a/gas/config/m68k-parse.y
+++ b/gas/config/m68k-parse.y
@@ -44,13 +44,13 @@
#define yylval m68k_lval
#define yychar m68k_char
#define yydebug m68k_debug
-#define yypact m68k_pact
-#define yyr1 m68k_r1
-#define yyr2 m68k_r2
-#define yydef m68k_def
-#define yychk m68k_chk
-#define yypgo m68k_pgo
-#define yyact m68k_act
+#define yypact m68k_pact
+#define yyr1 m68k_r1
+#define yyr2 m68k_r2
+#define yydef m68k_def
+#define yychk m68k_chk
+#define yypgo m68k_pgo
+#define yyact m68k_act
#define yyexca m68k_exca
#define yyerrflag m68k_errflag
#define yynerrs m68k_nerrs
@@ -1042,12 +1042,12 @@ yylex (void)
{
yylval.exp.pic_reloc = pic_tls_ie;
tail += 6;
- }
+ }
else if (strncmp (cp - 6, "@TLSLE", 6) == 0)
{
yylval.exp.pic_reloc = pic_tls_le;
tail += 6;
- }
+ }
}
else if (cp - 4 > str && cp[-4] == '@')
{
diff --git a/gas/config/obj-coff.h b/gas/config/obj-coff.h
index 82b618d..d99842d 100644
--- a/gas/config/obj-coff.h
+++ b/gas/config/obj-coff.h
@@ -235,16 +235,16 @@
#define SF_IS_SYSPROC 0x00000040 /* bit 6 marks symbols that are sysprocs. */
#define SF_BALNAME 0x00000080 /* bit 7 marks BALNAME symbols. */
#define SF_CALLNAME 0x00000100 /* bit 8 marks CALLNAME symbols. */
-
+
#define SF_NORMAL_MASK 0x0000ffff /* bits 12-15 are general purpose. */
-
+
#define SF_STATICS 0x00001000 /* Mark the .text & all symbols. */
#define SF_DEFINED 0x00002000 /* Symbol is defined in this file. */
#define SF_STRING 0x00004000 /* Symbol name length > 8. */
#define SF_LOCAL 0x00008000 /* Symbol must not be emitted. */
-
+
#define SF_DEBUG_MASK 0xffff0000 /* bits 16-31 are debug info. */
-
+
#define SF_FUNCTION 0x00010000 /* The symbol is a function. */
#define SF_PROCESS 0x00020000 /* Process symbol before write. */
#define SF_TAGGED 0x00040000 /* Is associated with a tag. */
diff --git a/gas/config/obj-elf.c b/gas/config/obj-elf.c
index 78dc6d9..08ae853 100644
--- a/gas/config/obj-elf.c
+++ b/gas/config/obj-elf.c
@@ -2321,7 +2321,7 @@ elf_adjust_symtab (void)
list.elt_count = NULL;
list.indexes = hash_new ();
bfd_map_over_sections (stdoutput, build_group_lists, &list);
-
+
/* Make the SHT_GROUP sections that describe each section group. We
can't set up the section contents here yet, because elf section
indices have yet to be calculated. elf.c:set_group_contents does
diff --git a/gas/config/obj-evax.c b/gas/config/obj-evax.c
index 07eea3f..b3702ef 100644
--- a/gas/config/obj-evax.c
+++ b/gas/config/obj-evax.c
@@ -332,7 +332,7 @@ evax_shorten_name (char *id)
which further designates that the name was truncated):
"original_identifier"_haaaaabbbccc
-
+
aaaaa = 32-bit CRC
bbb = length of original identifier
ccc = sum of 32-bit CRC characters
@@ -361,7 +361,7 @@ static char decodings[256];
/* Table used by the crc32 function to calcuate the checksum. */
static unsigned int crc32_table[256] = {0, 0};
-/* Given a string in BUF, calculate a 32-bit CRC for it.
+/* Given a string in BUF, calculate a 32-bit CRC for it.
This is used as a reasonably unique hash for the given string. */
@@ -499,7 +499,7 @@ is_truncated_identifier (char *id)
a truncated identifier. */
if (len != MAX_LABEL_LENGTH)
return 0;
-
+
/* Start scanning backwards for a _h. */
len = len - 3 - 3 - 5 - 2;
ptr = id + len;
diff --git a/gas/config/obj-macho.c b/gas/config/obj-macho.c
index 63c0b7e..10e8dbf 100644
--- a/gas/config/obj-macho.c
+++ b/gas/config/obj-macho.c
@@ -24,14 +24,14 @@
decorations. */
/* Mach-O supports multiple, named segments each of which may contain
- multiple named sections. Thus the concept of subsectioning is
+ multiple named sections. Thus the concept of subsectioning is
handled by (say) having a __TEXT segment with appropriate flags from
- which subsections are generated like __text, __const etc.
-
+ which subsections are generated like __text, __const etc.
+
The well-known as short-hand section switch directives like .text, .data
etc. are mapped onto predefined segment/section pairs using facilites
supplied by the mach-o port of bfd.
-
+
A number of additional mach-o short-hand section switch directives are
also defined. */
@@ -76,7 +76,7 @@ mach_o_begin (void)
subseg_set (text_section, 0);
if (obj_mach_o_is_static)
{
- bfd_mach_o_section *mo_sec
+ bfd_mach_o_section *mo_sec
= bfd_mach_o_get_mach_o_section (text_section);
mo_sec->flags &= ~BFD_MACH_O_S_ATTR_PURE_INSTRUCTIONS;
}
@@ -91,9 +91,9 @@ static int obj_mach_o_subsections_by_symbols;
/* This will put at most 16 characters (terminated by a ',' or newline) from
the input stream into dest. If there are more than 16 chars before the
delimiter, a warning is given and the string is truncated. On completion of
- this function, input_line_pointer will point to the char after the ',' or
- to the newline.
-
+ this function, input_line_pointer will point to the char after the ',' or
+ to the newline.
+
It trims leading and trailing space. */
static int
@@ -104,14 +104,14 @@ collect_16char_name (char *dest, const char *msg, int require_comma)
SKIP_WHITESPACE ();
namstart = input_line_pointer;
- while ( (c = *input_line_pointer) != ','
+ while ( (c = *input_line_pointer) != ','
&& !is_end_of_line[(unsigned char) c])
input_line_pointer++;
{
int len = input_line_pointer - namstart; /* could be zero. */
- /* lose any trailing space. */
- while (len > 0 && namstart[len-1] == ' ')
+ /* lose any trailing space. */
+ while (len > 0 && namstart[len-1] == ' ')
len--;
if (len > 16)
{
@@ -156,7 +156,7 @@ obj_mach_o_get_section_names (char *seg, char *sec,
/* Build (or get) a section from the mach-o description - which includes
optional definitions for type, attributes, alignment and stub size.
-
+
BFD supplies default values for sections which have a canonical name. */
#define SECT_TYPE_SPECIFIED 0x0001
@@ -166,7 +166,7 @@ obj_mach_o_get_section_names (char *seg, char *sec,
static segT
obj_mach_o_make_or_get_sect (char * segname, char * sectname,
- unsigned int specified_mask,
+ unsigned int specified_mask,
unsigned int usectype, unsigned int usecattr,
unsigned int ualign, offsetT stub_size)
{
@@ -247,7 +247,7 @@ obj_mach_o_make_or_get_sect (char * segname, char * sectname,
&& (specified_mask & SECT_ATTR_SPECIFIED)
&& (secattr & BFD_MACH_O_S_ATTR_PURE_INSTRUCTIONS))
flags |= SEC_CODE;
-
+
if (flags == SEC_NO_FLAGS
&& (specified_mask & SECT_ATTR_SPECIFIED)
&& (secattr & BFD_MACH_O_S_ATTR_DEBUG))
@@ -258,13 +258,13 @@ obj_mach_o_make_or_get_sect (char * segname, char * sectname,
as_warn (_("failed to set flags for \"%s\": %s"),
bfd_section_name (stdoutput, sec),
bfd_errmsg (bfd_get_error ()));
-
+
strncpy (msect->segname, segname, sizeof (msect->segname));
strncpy (msect->sectname, sectname, sizeof (msect->sectname));
msect->align = secalign;
msect->flags = sectype | secattr;
-
+
if (sectype == BFD_MACH_O_S_ZEROFILL
|| sectype == BFD_MACH_O_S_GB_ZEROFILL)
seg_info (sec)->bss = 1;
@@ -291,7 +291,7 @@ obj_mach_o_make_or_get_sect (char * segname, char * sectname,
White space is allowed everywhere between elements.
<segment> and <section> may be from 0 to 16 chars in length - they may
- contain spaces but leading and trailing space will be trimmed. It is
+ contain spaces but leading and trailing space will be trimmed. It is
mandatory that they be present (or that zero-length names are indicated
by ",,").
@@ -401,7 +401,7 @@ obj_mach_o_section (int ignore ATTRIBUTE_UNUSED)
while (*input_line_pointer == '+');
/* Parse sizeof_stub. */
- if ((specified_mask & SECT_ATTR_SPECIFIED)
+ if ((specified_mask & SECT_ATTR_SPECIFIED)
&& *input_line_pointer == ',')
{
if (sectype != BFD_MACH_O_S_SYMBOL_STUBS)
@@ -415,7 +415,7 @@ obj_mach_o_section (int ignore ATTRIBUTE_UNUSED)
sizeof_stub = get_absolute_expression ();
specified_mask |= SECT_STUB_SPECIFIED;
}
- else if ((specified_mask & SECT_ATTR_SPECIFIED)
+ else if ((specified_mask & SECT_ATTR_SPECIFIED)
&& sectype == BFD_MACH_O_S_SYMBOL_STUBS)
{
as_bad (_("missing sizeof_stub expression"));
@@ -425,7 +425,7 @@ obj_mach_o_section (int ignore ATTRIBUTE_UNUSED)
}
}
- new_seg = obj_mach_o_make_or_get_sect (segname, sectname, specified_mask,
+ new_seg = obj_mach_o_make_or_get_sect (segname, sectname, specified_mask,
sectype, secattr, 0 /*align */,
sizeof_stub);
if (new_seg != NULL)
@@ -465,14 +465,14 @@ obj_mach_o_zerofill (int ignore ATTRIBUTE_UNUSED)
/* Parse variable definition, if present. */
if (*input_line_pointer == ',')
{
- /* Parse symbol, size [.align]
+ /* Parse symbol, size [.align]
We follow the method of s_common_internal, with the difference
that the symbol cannot be a duplicate-common. */
char *name;
char c;
char *p;
expressionS exp;
-
+
input_line_pointer++; /* Skip ',' */
SKIP_WHITESPACE ();
name = input_line_pointer;
@@ -488,7 +488,7 @@ obj_mach_o_zerofill (int ignore ATTRIBUTE_UNUSED)
goto done;
}
- SKIP_WHITESPACE ();
+ SKIP_WHITESPACE ();
if (*input_line_pointer == ',')
input_line_pointer++;
@@ -535,8 +535,8 @@ obj_mach_o_zerofill (int ignore ATTRIBUTE_UNUSED)
name, (long) size, (long) exp.X_add_number);
*p = c; /* Restore the termination char. */
-
- SKIP_WHITESPACE ();
+
+ SKIP_WHITESPACE ();
if (*input_line_pointer == ',')
{
align = (unsigned int) parse_align (0);
@@ -557,7 +557,7 @@ obj_mach_o_zerofill (int ignore ATTRIBUTE_UNUSED)
/* else just a section definition. */
specified_mask |= SECT_TYPE_SPECIFIED;
- new_seg = obj_mach_o_make_or_get_sect (segname, sectname, specified_mask,
+ new_seg = obj_mach_o_make_or_get_sect (segname, sectname, specified_mask,
BFD_MACH_O_S_ZEROFILL,
BFD_MACH_O_S_ATTR_NONE,
align, (offsetT) 0 /*stub size*/);
@@ -600,7 +600,7 @@ done:
subseg_set (old_seg, 0);
}
-static segT
+static segT
obj_mach_o_segT_from_bfd_name (const char *nam, int must_succeed)
{
const mach_o_section_name_xlat *xlat;
@@ -630,7 +630,7 @@ obj_mach_o_segT_from_bfd_name (const char *nam, int must_succeed)
msect->flags = xlat->macho_sectype | xlat->macho_secattr;
msect->align = xlat->sectalign;
- if ((msect->flags & BFD_MACH_O_SECTION_TYPE_MASK)
+ if ((msect->flags & BFD_MACH_O_SECTION_TYPE_MASK)
== BFD_MACH_O_S_ZEROFILL)
seg_info (sec)->bss = 1;
}
@@ -714,7 +714,7 @@ static void
obj_mach_o_objc_section (int sect_index)
{
segT section;
-
+
#ifdef md_flush_pending_output
md_flush_pending_output ();
#endif
@@ -774,7 +774,7 @@ obj_mach_o_debug_section (int sect_index)
/* This could be moved to the tc-xx files, but there is so little dependency
there, that the code might as well be shared. */
-struct opt_tgt_sect
+struct opt_tgt_sect
{
const char *name;
unsigned x86_val;
@@ -898,7 +898,7 @@ obj_mach_o_common_parse (int is_local, symbolS *symbolP,
addressT align = 0;
bfd_mach_o_asymbol *s;
- SKIP_WHITESPACE ();
+ SKIP_WHITESPACE ();
/* Both comm and lcomm take an optional alignment, as a power
of two between 1 and 15. */
@@ -923,7 +923,7 @@ obj_mach_o_common_parse (int is_local, symbolS *symbolP,
if (bss_section == NULL)
{
bss_section = obj_mach_o_segT_from_bfd_name (BSS_SECTION_NAME, 1);
- seg_info (bss_section)->bss = 1;
+ seg_info (bss_section)->bss = 1;
}
bss_alloc (symbolP, size, align);
s->n_type = BFD_MACH_O_N_SECT;
@@ -962,17 +962,17 @@ typedef enum obj_mach_o_file_properties {
OBJ_MACH_O_FILE_PROP_MAX
} obj_mach_o_file_properties;
-static void
+static void
obj_mach_o_fileprop (int prop)
{
if (prop < 0 || prop >= OBJ_MACH_O_FILE_PROP_MAX)
as_fatal (_("internal error: bad file property ID %d"), prop);
-
+
switch ((obj_mach_o_file_properties) prop)
{
case OBJ_MACH_O_FILE_PROP_SUBSECTS_VIA_SYMS:
obj_mach_o_subsections_by_symbols = 1;
- if (!bfd_set_private_flags (stdoutput,
+ if (!bfd_set_private_flags (stdoutput,
BFD_MACH_O_MH_SUBSECTIONS_VIA_SYMBOLS))
as_bad (_("failed to set subsections by symbols"));
demand_empty_rest_of_line ();
@@ -982,7 +982,7 @@ obj_mach_o_fileprop (int prop)
}
}
-/* Temporary markers for symbol reference data.
+/* Temporary markers for symbol reference data.
Lazy will remain in place. */
#define LAZY 0x01
#define REFE 0x02
@@ -1015,9 +1015,9 @@ obj_mach_o_set_symbol_qualifier (symbolS *sym, int type)
int sectype = -1;
/* If the symbol is defined, then we can do more rigorous checking on
- the validity of the qualifiers. Otherwise, we are stuck with waiting
+ the validity of the qualifiers. Otherwise, we are stuck with waiting
until it's defined - or until write the file.
-
+
In certain cases (e.g. when a symbol qualifier is intended to introduce
an undefined symbol in a stubs section) we should check that the current
section is appropriate to the qualifier. */
@@ -1201,8 +1201,8 @@ obj_mach_o_indirect_symbol (int arg ATTRIBUTE_UNUSED)
}
*input_line_pointer = c;
- /* The indirect symbols are validated after the symbol table is
- frozen, we must make sure that if a local symbol is used as an
+ /* The indirect symbols are validated after the symbol table is
+ frozen, we must make sure that if a local symbol is used as an
indirect, it is promoted to a 'real' one. Fetching the bfd sym
achieves this. */
symbol_get_bfdsym (sym);
@@ -1295,7 +1295,7 @@ const pseudo_typeS mach_o_pseudo_table[] =
{ "debug_str", obj_mach_o_debug_section, 10}, /* extension. */
{ "debug_ranges", obj_mach_o_debug_section, 11}, /* extension. */
{ "debug_macro", obj_mach_o_debug_section, 12}, /* extension. */
-
+
{ "lazy_symbol_pointer", obj_mach_o_opt_tgt_section, 1},
{ "lazy_symbol_pointer2", obj_mach_o_opt_tgt_section, 2}, /* extension. */
{ "lazy_symbol_pointer3", obj_mach_o_opt_tgt_section, 3}, /* extension. */
@@ -1325,7 +1325,7 @@ const pseudo_typeS mach_o_pseudo_table[] =
{ "indirect_symbol", obj_mach_o_indirect_symbol, 0},
/* File flags. */
- { "subsections_via_symbols", obj_mach_o_fileprop,
+ { "subsections_via_symbols", obj_mach_o_fileprop,
OBJ_MACH_O_FILE_PROP_SUBSECTS_VIA_SYMS},
{NULL, NULL, 0}
@@ -1359,9 +1359,9 @@ obj_mach_o_frob_colon (const char *name)
/* We need to check the correspondence between some kinds of symbols and their
sections. Common and BSS vars will seen via the obj_macho_comm() function.
-
+
The earlier we can pick up a problem, the better the diagnostics will be.
-
+
However, when symbol type information is attached, the symbol section will
quite possibly be unknown. So we are stuck with checking (most of the)
validity at the time the file is written (unfortunately, then one doesn't
@@ -1399,7 +1399,7 @@ void obj_mach_o_frob_label (struct symbol *sp)
/* This is the base symbol type, that we mask in. */
base_type = obj_mach_o_type_for_symbol (s);
- sec = bfd_mach_o_get_mach_o_section (s->symbol.section);
+ sec = bfd_mach_o_get_mach_o_section (s->symbol.section);
if (sec != NULL)
sectype = sec->flags & BFD_MACH_O_SECTION_TYPE_MASK;
@@ -1447,7 +1447,7 @@ obj_mach_o_frob_symbol (struct symbol *sp)
return 0;
base_type = obj_mach_o_type_for_symbol (s);
- sec = bfd_mach_o_get_mach_o_section (s->symbol.section);
+ sec = bfd_mach_o_get_mach_o_section (s->symbol.section);
if (sec != NULL)
sectype = sec->flags & BFD_MACH_O_SECTION_TYPE_MASK;
@@ -1485,7 +1485,7 @@ obj_mach_o_frob_symbol (struct symbol *sp)
{
/* Anything here that should be added that is non-standard. */
s->n_desc &= ~BFD_MACH_O_REFERENCE_MASK;
- }
+ }
else if (s->symbol.udata.i == SYM_MACHO_FIELDS_NOT_VALIDATED)
{
/* Try to validate any combinations. */
@@ -1558,7 +1558,7 @@ obj_mach_o_process_stab (int what, const char *string,
/* It's a debug symbol. */
s->symbol.flags |= BSF_DEBUGGING;
-
+
/* We've set it - so check it, if you can, but don't try to create the
flags. */
s->symbol.udata.i = SYM_MACHO_FIELDS_NOT_VALIDATED;
@@ -1666,7 +1666,7 @@ obj_mach_o_set_subsections (bfd *abfd ATTRIBUTE_UNUSED,
}
}
-/* Handle mach-o subsections-via-symbols counting up frags belonging to each
+/* Handle mach-o subsections-via-symbols counting up frags belonging to each
sub-section. */
void
@@ -1680,7 +1680,7 @@ obj_mach_o_pre_relax_hook (void)
The native 'as' leaves the sections physically in the order they appear in
the source, and adjusts the section VMAs to meet the constraint.
-
+
We follow this for now - if nothing else, it makes comparison easier.
An alternative implementation would be to sort the sections as ld requires.
@@ -1699,7 +1699,7 @@ typedef struct obj_mach_o_set_vma_data
zerofill sections get VMAs after all others in their segment
GB zerofill get VMAs last.
-
+
As we go, we notice if we see any Zerofill or GB Zerofill sections, so that
we can skip the additional passes if there's nothing to do. */
@@ -1730,11 +1730,11 @@ obj_mach_o_set_section_vma (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *v_p
/* We know the section size now - so make a vma for the section just
based on order. */
ms->size = bfd_get_section_size (sec);
-
+
/* Make sure that the align agrees, and set to the largest value chosen. */
ms->align = ms->align > bfd_align ? ms->align : bfd_align;
bfd_set_section_alignment (abfd, sec, ms->align);
-
+
p->vma += (1 << ms->align) - 1;
p->vma &= ~((1 << ms->align) - 1);
ms->addr = p->vma;
@@ -1742,7 +1742,7 @@ obj_mach_o_set_section_vma (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *v_p
p->vma += ms->size;
}
-/* (potentially) three passes over the sections, setting VMA. We skip the
+/* (potentially) three passes over the sections, setting VMA. We skip the
{gb}zerofill passes if we didn't see any of the relevant sections. */
void obj_mach_o_post_relax_hook (void)
@@ -1750,7 +1750,7 @@ void obj_mach_o_post_relax_hook (void)
obj_mach_o_set_vma_data d;
memset (&d, 0, sizeof (d));
-
+
bfd_map_over_sections (stdoutput, obj_mach_o_set_section_vma, (char *) &d);
if ((d.vma_pass = d.zerofill_seen) != 0)
bfd_map_over_sections (stdoutput, obj_mach_o_set_section_vma, (char *) &d);
@@ -1787,7 +1787,7 @@ obj_mach_o_set_indirect_symbols (bfd *abfd, asection *sec,
obj_mach_o_indirect_sym *isym;
obj_mach_o_indirect_sym *list = NULL;
obj_mach_o_indirect_sym *list_tail = NULL;
- unsigned long eltsiz =
+ unsigned long eltsiz =
bfd_mach_o_section_get_entry_size (abfd, ms);
for (isym = indirect_syms; isym != NULL; isym = isym->next)
@@ -1829,14 +1829,14 @@ obj_mach_o_set_indirect_symbols (bfd *abfd, asection *sec,
as_fatal (_("internal error: failed to allocate %d indirect"
"symbol pointers"), nactual);
}
-
+
for (isym = list, n = 0; isym != NULL; isym = isym->next, n++)
{
sym = (bfd_mach_o_asymbol *)symbol_get_bfdsym (isym->sym);
/* Array is init to NULL & NULL signals a local symbol
If the section is lazy-bound, we need to keep the
reference to the symbol, since dyld can override.
-
+
Absolute symbols are handled specially. */
if (sym->symbol.section == bfd_abs_section_ptr)
ms->indirect_syms[n] = sym;
@@ -1854,8 +1854,8 @@ obj_mach_o_set_indirect_symbols (bfd *abfd, asection *sec,
{
sym->n_desc &= ~LAZY;
/* ... it can be lazy, if not defined or hidden. */
- if ((sym->n_type & BFD_MACH_O_N_TYPE)
- == BFD_MACH_O_N_UNDF
+ if ((sym->n_type & BFD_MACH_O_N_TYPE)
+ == BFD_MACH_O_N_UNDF
&& ! (sym->n_type & BFD_MACH_O_N_PEXT)
&& (sym->n_type & BFD_MACH_O_N_EXT))
sym->n_desc |= lazy;
@@ -1917,7 +1917,7 @@ obj_mach_o_is_frame_section (segT sec)
being made. */
int
-obj_mach_o_allow_local_subtract (expressionS * left ATTRIBUTE_UNUSED,
+obj_mach_o_allow_local_subtract (expressionS * left ATTRIBUTE_UNUSED,
expressionS * right ATTRIBUTE_UNUSED,
segT seg)
{
diff --git a/gas/config/obj-macho.h b/gas/config/obj-macho.h
index 5011b7e..e031e9e 100644
--- a/gas/config/obj-macho.h
+++ b/gas/config/obj-macho.h
@@ -84,7 +84,7 @@ struct obj_mach_o_frag_data
/* Symbol that corresponds to the subsection. */
symbolS *subsection;
};
-
+
#define OBJ_FRAG_TYPE struct obj_mach_o_frag_data
#define md_pre_output_hook obj_mach_o_pre_output_hook()
diff --git a/gas/config/rl78-defs.h b/gas/config/rl78-defs.h
index 67b1dbb..b41a732 100644
--- a/gas/config/rl78-defs.h
+++ b/gas/config/rl78-defs.h
@@ -19,7 +19,7 @@
02110-1301, USA. */
#ifndef RL78_DEFS_H
-#define RL78_DEFS_H
+#define RL78_DEFS_H
/* Third operand to rl78_op. */
#define RL78REL_DATA 0
diff --git a/gas/config/rl78-parse.y b/gas/config/rl78-parse.y
index f34903e..b879581 100644
--- a/gas/config/rl78-parse.y
+++ b/gas/config/rl78-parse.y
@@ -1551,7 +1551,7 @@ expr_is_word_aligned (expressionS exp)
if (v & 1)
return 0;
return 1;
-
+
}
static void
diff --git a/gas/config/rx-parse.y b/gas/config/rx-parse.y
index 5269d66..e155257 100644
--- a/gas/config/rx-parse.y
+++ b/gas/config/rx-parse.y
@@ -889,7 +889,7 @@ float2_op
;
float2_op_ni
- : { rx_check_float_support (); }
+ : { rx_check_float_support (); }
REG ',' REG
{ id24 (1, 0x83 + (sub_op << 2), 0); F ($2, 16, 4); F ($4, 20, 4); }
| { rx_check_float_support (); }
diff --git a/gas/config/tc-alpha.c b/gas/config/tc-alpha.c
index 2a7466a..a19fbc5 100644
--- a/gas/config/tc-alpha.c
+++ b/gas/config/tc-alpha.c
@@ -265,7 +265,7 @@ struct option md_longopts[] =
#define OPTION_REPLACE (OPTION_RELAX + 1)
#define OPTION_NOREPLACE (OPTION_REPLACE+1)
{ "replace", no_argument, NULL, OPTION_REPLACE },
- { "noreplace", no_argument, NULL, OPTION_NOREPLACE },
+ { "noreplace", no_argument, NULL, OPTION_NOREPLACE },
#endif
{ NULL, no_argument, NULL, 0 }
};
@@ -1798,7 +1798,7 @@ emit_insn (struct alpha_insn *insn)
default:
gas_assert (size >= 1 && size <= 4);
}
-
+
pcrel = reloc_howto->pc_relative;
}
@@ -2137,7 +2137,7 @@ assemble_insn (const struct alpha_opcode *opcode,
/* If this is a real relocation (as opposed to a lituse hint), then
the relocation width should match the operand width.
- Take care of -MDISP in operand table. */
+ Take care of -MDISP in operand table. */
else if (reloc < BFD_RELOC_UNUSED && reloc > 0)
{
reloc_howto_type *reloc_howto
@@ -2190,7 +2190,7 @@ emit_ir_load (const expressionS *tok,
if (basereg == alpha_gp_register &&
(symlen > 4 && strcmp (&symname [symlen - 4], "..lk") == 0))
return;
-
+
newtok[0] = tok[0];
set_tok_preg (newtok[2], basereg);
@@ -2231,7 +2231,7 @@ emit_loadstore (const expressionS *tok,
if (alpha_noat_on)
as_bad (_("macro requires $at register while noat in effect"));
- lituse = load_expression (AXP_REG_AT, &tok[1],
+ lituse = load_expression (AXP_REG_AT, &tok[1],
&basereg, &newtok[1], (const char *) opname);
}
else
@@ -3383,7 +3383,7 @@ add_to_link_pool (symbolS *sym, offsetT addend)
fixS *fixp;
symbolS *linksym, *expsym;
expressionS e;
-
+
basesym = alpha_evax_proc->symbol;
/* @@ This assumes all entries in a given section will be of the same
@@ -3556,7 +3556,7 @@ s_alpha_comm (int ignore ATTRIBUTE_UNUSED)
segT current_seg = now_seg;
subsegT current_subseg = now_subseg;
int cur_size;
-
+
input_line_pointer++;
SKIP_WHITESPACE ();
sec_name = s_alpha_section_name ();
@@ -3610,7 +3610,7 @@ s_alpha_comm (int ignore ATTRIBUTE_UNUSED)
subseg_set (current_seg, current_subseg);
}
#endif
-
+
if (S_GET_VALUE (symbolP))
{
if (S_GET_VALUE (symbolP) != (valueT) size)
@@ -3626,7 +3626,7 @@ s_alpha_comm (int ignore ATTRIBUTE_UNUSED)
#endif
S_SET_EXTERNAL (symbolP);
}
-
+
#ifndef OBJ_EVAX
know (symbolP->sy_frag == &zero_address_frag);
#endif
@@ -4240,7 +4240,7 @@ s_alpha_section_word (char *str, size_t len)
{
no = 1;
str += 2;
- len -= 2;
+ len -= 2;
}
if (len == 3)
@@ -4507,10 +4507,10 @@ s_alpha_pdesc (int ignore ATTRIBUTE_UNUSED)
as_bad (_(".pdesc directive has no entry symbol"));
return;
}
-
+
entry_sym = make_expr_symbol (&exp);
entry_sym_name = S_GET_NAME (entry_sym);
-
+
/* Strip "..en". */
len = strlen (entry_sym_name);
if (len < 4 || strcmp (entry_sym_name + len - 4, "..en") != 0)
@@ -4532,12 +4532,12 @@ s_alpha_pdesc (int ignore ATTRIBUTE_UNUSED)
/* Define pdesc symbol. */
symbol_set_value_now (alpha_evax_proc->symbol);
-
+
/* Save bfd symbol of proc entry in function symbol. */
((struct evax_private_udata_struct *)
symbol_get_bfdsym (alpha_evax_proc->symbol)->udata.p)->enbsym
= symbol_get_bfdsym (entry_sym);
-
+
SKIP_WHITESPACE ();
if (*input_line_pointer++ != ',')
{
@@ -4703,7 +4703,7 @@ s_alpha_linkage (int ignore ATTRIBUTE_UNUSED)
else
{
struct alpha_linkage_fixups *linkage_fixup;
-
+
p = frag_more (LKP_S_K_SIZE);
memset (p, 0, LKP_S_K_SIZE);
fixp = fix_new_exp
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index b7edb5e..fabcf80 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7767,7 +7767,7 @@ is_double_a_single (bfd_int64_t v)
&& (mantissa & 0x1FFFFFFFl) == 0;
}
-/* Returns a double precision value casted to single precision
+/* Returns a double precision value casted to single precision
(ignoring the least significant bits in exponent and mantissa). */
static int
@@ -7865,7 +7865,7 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
}
else
l = generic_bignum;
-
+
#if defined BFD_HOST_64_BIT
v =
((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
@@ -7922,7 +7922,7 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
return TRUE;
}
else if ((v & ~0xFFFF) == 0 || (v & ~0xFFFF0000) == 0)
- {
+ {
/* The number may be loaded with a movw/movt instruction. */
int imm;
@@ -21880,7 +21880,7 @@ arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
else
free (nbuf);
}
-
+
return FALSE;
}
diff --git a/gas/config/tc-cr16.c b/gas/config/tc-cr16.c
index 91c1fdf..0f2456e 100644
--- a/gas/config/tc-cr16.c
+++ b/gas/config/tc-cr16.c
@@ -335,7 +335,7 @@ get_register_pair (char *reg_name)
char tmp_rp[16]="\0";
/* Add '(' and ')' to the reg pair, if its not present. */
- if (reg_name[0] != '(')
+ if (reg_name[0] != '(')
{
tmp_rp[0] = '(';
strcat (tmp_rp, reg_name);
@@ -349,7 +349,7 @@ get_register_pair (char *reg_name)
return rreg->value.reg_val;
return nullregister;
-}
+}
/* Get the index register 'reg_name'. */
@@ -522,9 +522,9 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
arelent * reloc;
/* If symbols are local and resolved, then no relocation needed. */
- if ( ((fixP->fx_addsy)
+ if ( ((fixP->fx_addsy)
&& (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section))
- || ((fixP->fx_subsy)
+ || ((fixP->fx_subsy)
&& (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)))
return NULL;
@@ -932,7 +932,7 @@ process_label_constant (char *str, ins * cr16_ins)
else if (strneq (input_line_pointer, "@GOT", 4)
|| strneq (input_line_pointer, "@got", 4))
{
- if ((strneq (input_line_pointer, "+", 1))
+ if ((strneq (input_line_pointer, "+", 1))
|| (strneq (input_line_pointer, "-", 1)))
as_warn (_("GOT bad expression with %s."), input_line_pointer);
@@ -2457,7 +2457,7 @@ print_insn (ins *insn)
int size;
reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
-
+
if (!reloc_howto)
abort ();
diff --git a/gas/config/tc-cr16.h b/gas/config/tc-cr16.h
index 5d1154f..211846d 100644
--- a/gas/config/tc-cr16.h
+++ b/gas/config/tc-cr16.h
@@ -60,12 +60,12 @@ extern int cr16_force_relocation (struct fix *);
extern void cr16_cons_fix_new (struct frag *, int, int, struct expressionS *,
bfd_reloc_code_real_type);
/* This is called by emit_expr when creating a reloc for a cons.
- We could use the definition there, except that we want to handle
+ We could use the definition there, except that we want to handle
the CR16 reloc type specially, rather than the BFD_RELOC type. */
#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \
cr16_cons_fix_new (FRAG, OFF, LEN, EXP, RELOC)
-/* Give an error if a frag containing code is not aligned to a 2-byte
+/* Give an error if a frag containing code is not aligned to a 2-byte
boundary. */
#define md_frag_check(FRAGP) \
if ((FRAGP)->has_code \
diff --git a/gas/config/tc-cris.c b/gas/config/tc-cris.c
index 5b36da6..25c9ea5 100644
--- a/gas/config/tc-cris.c
+++ b/gas/config/tc-cris.c
@@ -1812,7 +1812,7 @@ cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp,
out_insnp->opcode |= regno << 12;
out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_8;
continue;
-
+
case 'O':
/* A BDAP expression for any size, "expr,R". */
if (! cris_get_expression (&s, &prefixp->expr))
@@ -4327,7 +4327,7 @@ cris_insn_ver_valid_for_arch (enum cris_insn_version_usage iver,
|| iver == cris_ver_v8_10
|| iver == cris_ver_v10
|| iver == cris_ver_v10p);
-
+
case arch_crisv32:
return
(iver == cris_ver_version_all
diff --git a/gas/config/tc-crx.c b/gas/config/tc-crx.c
index a2314b7..0acb05e 100644
--- a/gas/config/tc-crx.c
+++ b/gas/config/tc-crx.c
@@ -57,7 +57,7 @@ typedef enum
OP_NOT_EVEN, /* Operand is Odd number, should be even. */
OP_ILLEGAL_DISPU4, /* Operand is not within DISPU4 range. */
OP_ILLEGAL_CST4, /* Operand is not within CST4 range. */
- OP_NOT_UPPER_64KB /* Operand is not within the upper 64KB
+ OP_NOT_UPPER_64KB /* Operand is not within the upper 64KB
(0xFFFF0000-0xFFFFFFFF). */
}
op_err;
@@ -533,7 +533,7 @@ md_begin (void)
/* Set up a hash table for the instructions. */
if ((crx_inst_hash = hash_new ()) == NULL)
as_fatal (_("Virtual memory exhausted"));
-
+
while (crx_instruction[i].mnemonic != NULL)
{
const char *mnemonic = crx_instruction[i].mnemonic;
@@ -597,7 +597,7 @@ md_begin (void)
linkrelax = 1;
}
-/* Process constants (immediate/absolute)
+/* Process constants (immediate/absolute)
and labels (jump targets/Memory locations). */
static void
@@ -610,7 +610,7 @@ process_label_constant (char *str, ins * crx_ins)
input_line_pointer = str;
expression (&crx_ins->exp);
-
+
switch (crx_ins->exp.X_op)
{
case O_big:
@@ -651,7 +651,7 @@ process_label_constant (char *str, ins * crx_ins)
case arg_idxr:
crx_ins->rtype = BFD_RELOC_CRX_REGREL22;
break;
-
+
case arg_c:
if (IS_INSN_MNEMONIC ("bal") || IS_INSN_TYPE (DCR_BRANCH_INS))
crx_ins->rtype = BFD_RELOC_CRX_REL16;
@@ -665,7 +665,7 @@ process_label_constant (char *str, ins * crx_ins)
else if (IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
crx_ins->rtype = BFD_RELOC_CRX_REL8_CMP;
break;
-
+
case arg_ic:
if (IS_INSN_TYPE (ARITH_INS))
crx_ins->rtype = BFD_RELOC_CRX_IMM32;
@@ -733,7 +733,7 @@ set_operand (char *operand, ins * crx_ins)
case arg_c: /* Case 0x18. */
/* Set constant. */
process_label_constant (operandS, crx_ins);
-
+
if (cur_arg->type != arg_ic)
cur_arg->type = arg_c;
break;
@@ -746,7 +746,7 @@ set_operand (char *operand, ins * crx_ins)
operandE++;
*operandE = '\0';
process_label_constant (operandS, crx_ins);
- operandS = operandE;
+ operandS = operandE;
case arg_rbase: /* Case (r1). */
operandS++;
/* Set register base. */
@@ -768,7 +768,7 @@ set_operand (char *operand, ins * crx_ins)
*operandE = '\0';
process_label_constant (operandS, crx_ins);
operandS = ++operandE;
-
+
/* Set register base. */
while ((*operandE != ',') && (! ISSPACE (*operandE)))
operandE++;
@@ -885,7 +885,7 @@ parse_operand (char *operand, ins * crx_ins)
default:
break;
}
-
+
if (strchr (operand, '(') != NULL)
{
if (strchr (operand, ',') != NULL
@@ -904,7 +904,7 @@ set_params:
set_operand (operand, crx_ins);
}
-/* Parse the various operands. Each operand is then analyzed to fillup
+/* Parse the various operands. Each operand is then analyzed to fillup
the fields in the crx_ins data structure. */
static void
@@ -999,18 +999,18 @@ gettrap (const char *s)
return 0;
}
-/* Post-Increment instructions, as well as Store-Immediate instructions, are a
- sub-group within load/stor instruction groups.
- Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to
- advance the instruction pointer to the start of that sub-group (that is, up
+/* Post-Increment instructions, as well as Store-Immediate instructions, are a
+ sub-group within load/stor instruction groups.
+ Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to
+ advance the instruction pointer to the start of that sub-group (that is, up
to the first instruction of that type).
Otherwise, the insn will be mistakenly identified as of type LD_STOR_INS. */
static void
handle_LoadStor (const char *operands)
{
- /* Post-Increment instructions precede Store-Immediate instructions in
- CRX instruction table, hence they are handled before.
+ /* Post-Increment instructions precede Store-Immediate instructions in
+ CRX instruction table, hence they are handled before.
This synchronization should be kept. */
/* Assuming Post-Increment insn has the following format :
@@ -1220,8 +1220,8 @@ print_constant (int nbits, int shift, argument *arg)
break;
}
- /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
- always filling the upper part of output_opcode[1]. If we mistakenly
+ /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
+ always filling the upper part of output_opcode[1]. If we mistakenly
write it to output_opcode[0], the constant prefix (that is, 'match')
will be overridden.
0 1 2 3
@@ -1316,8 +1316,8 @@ get_number_of_operands (void)
return i;
}
-/* Verify that the number NUM can be represented in BITS bits (that is,
- within its permitted range), based on the instruction's FLAGS.
+/* Verify that the number NUM can be represented in BITS bits (that is,
+ within its permitted range), based on the instruction's FLAGS.
If UPDATE is nonzero, update the value of NUM if necessary.
Return OP_LEGAL upon success, actual error type upon failure. */
@@ -1379,11 +1379,11 @@ check_range (long *num, int bits, int unsigned flags, int update)
{
int is_dispu4 = 0;
- uint32_t mul = (instruction->flags & DISPUB4 ? 1
+ uint32_t mul = (instruction->flags & DISPUB4 ? 1
: instruction->flags & DISPUW4 ? 2
: instruction->flags & DISPUD4 ? 4
: 0);
-
+
for (bin = 0; bin < cst4_maps; bin++)
{
if (value == mul * bin)
@@ -1436,7 +1436,7 @@ check_range (long *num, int bits, int unsigned flags, int update)
/* Assemble a single instruction:
INSN is already parsed (that is, all operand values and types are set).
- For instruction to be assembled, we need to find an appropriate template in
+ For instruction to be assembled, we need to find an appropriate template in
the instruction table, meeting the following conditions:
1: Has the same number of operands.
2: Has the same operand types.
@@ -1489,7 +1489,7 @@ assemble_insn (char *mnemonic, ins *insn)
/* In some case, same mnemonic can appear with different instruction types.
For example, 'storb' is supported with 3 different types :
LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
- We assume that when reaching this point, the instruction type was
+ We assume that when reaching this point, the instruction type was
pre-determined. We need to make sure that the type stays the same
during a search for matching instruction. */
ins_type = CRX_INS_TYPE(instruction->flags);
@@ -1529,19 +1529,19 @@ assemble_insn (char *mnemonic, ins *insn)
{
/* Reverse the operand indices for certain opcodes:
Index 0 -->> 1
- Index 1 -->> 0
+ Index 1 -->> 0
Other index -->> stays the same. */
- int j = instruction->flags & REVERSE_MATCH ?
- i == 0 ? 1 :
- i == 1 ? 0 : i :
+ int j = instruction->flags & REVERSE_MATCH ?
+ i == 0 ? 1 :
+ i == 1 ? 0 : i :
i;
- /* Only check range - don't update the constant's value, since the
- current instruction may not be the last we try to match.
- The constant's value will be updated later, right before printing
+ /* Only check range - don't update the constant's value, since the
+ current instruction may not be the last we try to match.
+ The constant's value will be updated later, right before printing
it to the object file. */
- if ((insn->arg[j].X_op == O_constant)
- && (op_error = check_range (&insn->arg[j].constant, cur_size[j],
+ if ((insn->arg[j].X_op == O_constant)
+ && (op_error = check_range (&insn->arg[j].constant, cur_size[j],
cur_flags[j], 0)))
{
if (invalid_const == -1)
@@ -1551,10 +1551,10 @@ assemble_insn (char *mnemonic, ins *insn)
}
goto next_insn;
}
- /* For symbols, we make sure the relocation size (which was already
+ /* For symbols, we make sure the relocation size (which was already
determined) is sufficient. */
else if ((insn->arg[j].X_op == O_symbol)
- && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
+ && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
> cur_size[j]))
goto next_insn;
}
@@ -1593,7 +1593,7 @@ next_insn:
as_bad (_("Invalid CST4 operand value (arg %d)"), invalid_const);
break;
case OP_NOT_UPPER_64KB:
- as_bad (_("Operand value is not within upper 64 KB (arg %d)"),
+ as_bad (_("Operand value is not within upper 64 KB (arg %d)"),
invalid_const);
break;
default:
@@ -1601,7 +1601,7 @@ next_insn:
break;
}
}
-
+
return 0;
}
else
@@ -1610,23 +1610,23 @@ next_insn:
/* Make further checkings (such that couldn't be made earlier).
Warn the user if necessary. */
warn_if_needed (insn);
-
+
/* Check whether we need to adjust the instruction pointer. */
if (adjust_if_needed (insn))
- /* If instruction pointer was adjusted, we need to update
+ /* If instruction pointer was adjusted, we need to update
the size of the current template operands. */
GET_CURRENT_SIZE;
for (i = 0; i < insn->nargs; i++)
{
- int j = instruction->flags & REVERSE_MATCH ?
- i == 0 ? 1 :
- i == 1 ? 0 : i :
+ int j = instruction->flags & REVERSE_MATCH ?
+ i == 0 ? 1 :
+ i == 1 ? 0 : i :
i;
/* This time, update constant value before printing it. */
- if ((insn->arg[j].X_op == O_constant)
- && (check_range (&insn->arg[j].constant, cur_size[j],
+ if ((insn->arg[j].X_op == O_constant)
+ && (check_range (&insn->arg[j].constant, cur_size[j],
cur_flags[j], 1) != OP_LEGAL))
as_fatal (_("Illegal operand (arg %d)"), j+1);
}
@@ -1637,7 +1637,7 @@ next_insn:
for (i = 0; i < insn->nargs; i++)
{
cur_arg_num = i;
- print_operand (cur_size[i], instruction->operands[i].shift,
+ print_operand (cur_size[i], instruction->operands[i].shift,
&insn->arg[i]);
}
}
@@ -1651,15 +1651,15 @@ next_insn:
void
warn_if_needed (ins *insn)
{
- /* If the post-increment address mode is used and the load/store
- source register is the same as rbase, the result of the
+ /* If the post-increment address mode is used and the load/store
+ source register is the same as rbase, the result of the
instruction is undefined. */
if (IS_INSN_TYPE (LD_STOR_INS_INC))
{
/* Enough to verify that one of the arguments is a simple reg. */
if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
if (insn->arg[0].r == insn->arg[1].r)
- as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
+ as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
insn->arg[0].r);
}
@@ -1671,17 +1671,17 @@ warn_if_needed (ins *insn)
as_bad (_("`%s' has undefined result"), ins_parse);
}
- /* If the rptr register is specified as one of the registers to be loaded,
+ /* If the rptr register is specified as one of the registers to be loaded,
the final contents of rptr are undefined. Thus, we issue an error. */
if (instruction->flags & NO_RPTR)
{
if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
- as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
+ as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
getreg_image (insn->arg[0].r));
}
}
-/* In some cases, we need to adjust the instruction pointer although a
+/* In some cases, we need to adjust the instruction pointer although a
match was already found. Here, we gather all these cases.
Returns 1 if instruction pointer was adjusted, otherwise 0. */
@@ -1705,7 +1705,7 @@ adjust_if_needed (ins *insn)
}
}
- /* Optimization: Omit a zero displacement in bit operations,
+ /* Optimization: Omit a zero displacement in bit operations,
saving 2-byte encoding space (e.g., 'cbitw $8, 0(r1)'). */
if (IS_INSN_TYPE (CSTBIT_INS))
{
@@ -1792,7 +1792,7 @@ preprocess_reglist (char *param, int *allocated)
{
if (((cr = get_copregister (reg_name)) == nullcopregister)
|| (crx_copregtab[cr-MAX_REG].type != CRX_CS_REGTYPE))
- as_fatal (_("Illegal register `%s' in cop-special-register list"),
+ as_fatal (_("Illegal register `%s' in cop-special-register list"),
reg_name);
mask_reg (getreg_image (cr - cs0), &mask);
}
@@ -1812,8 +1812,8 @@ preprocess_reglist (char *param, int *allocated)
else if (((r = get_register (reg_name)) == nullregister)
|| (crx_regtab[r].type != CRX_U_REGTYPE))
as_fatal (_("Illegal register `%s' in user register list"), reg_name);
-
- mask_reg (getreg_image (r - u0), &mask);
+
+ mask_reg (getreg_image (r - u0), &mask);
}
/* General purpose register r<N>. */
else
diff --git a/gas/config/tc-crx.h b/gas/config/tc-crx.h
index 65f86bc..c1eaa6b 100644
--- a/gas/config/tc-crx.h
+++ b/gas/config/tc-crx.h
@@ -58,7 +58,7 @@ extern int crx_force_relocation (struct fix *);
#define DWARF2_LINE_MIN_INSN_LENGTH 2
/* This is called by emit_expr when creating a reloc for a cons.
- We could use the definition there, except that we want to handle
+ We could use the definition there, except that we want to handle
the CRX reloc type specially, rather than the BFD_RELOC type. */
#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \
(void) RELOC, \
@@ -68,7 +68,7 @@ extern int crx_force_relocation (struct fix *);
: LEN == 4 ? BFD_RELOC_CRX_NUM32 \
: BFD_RELOC_NONE);
-/* Give an error if a frag containing code is not aligned to a 2-byte
+/* Give an error if a frag containing code is not aligned to a 2-byte
boundary. */
#define md_frag_check(FRAGP) \
if ((FRAGP)->has_code \
diff --git a/gas/config/tc-dlx.c b/gas/config/tc-dlx.c
index da962db..a0a6021 100644
--- a/gas/config/tc-dlx.c
+++ b/gas/config/tc-dlx.c
@@ -803,7 +803,7 @@ machine_ip (char *str)
continue;
}
- the_insn.reloc = (the_insn.HI) ? RELOC_DLX_HI16
+ the_insn.reloc = (the_insn.HI) ? RELOC_DLX_HI16
: (the_insn.LO ? RELOC_DLX_LO16 : RELOC_DLX_16);
the_insn.reloc_offset = 2;
the_insn.size = 2;
diff --git a/gas/config/tc-frv.c b/gas/config/tc-frv.c
index 0bec232..0ca1a6e 100644
--- a/gas/config/tc-frv.c
+++ b/gas/config/tc-frv.c
@@ -19,7 +19,7 @@
Boston, MA 02110-1301, USA. */
#include "as.h"
-#include "subsegs.h"
+#include "subsegs.h"
#include "symcat.h"
#include "opcodes/frv-desc.h"
#include "opcodes/frv-opc.h"
@@ -60,7 +60,7 @@ enum vliw_insn_type
VLIW_BRANCH_HAS_NOPS /* A Branch that requires NOPS. */
};
-/* We're going to use these in the fr_subtype field to mark
+/* We're going to use these in the fr_subtype field to mark
whether to keep inserted nops. */
#define NOP_KEEP 1 /* Keep these NOPS. */
@@ -115,7 +115,7 @@ static struct vliw_insn_list *current_vliw_insn;
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
-const char line_separator_chars[] = "!";
+const char line_separator_chars[] = "!";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
@@ -477,14 +477,14 @@ md_show_usage (FILE * stream)
fprintf (stream, _(" Record the cpu type\n"));
fprintf (stream, _("-mtomcat-stats Print out stats for tomcat workarounds\n"));
fprintf (stream, _("-mtomcat-debug Debug tomcat workarounds\n"));
-}
+}
void
md_begin (void)
{
/* Initialize the `cgen' interface. */
-
+
/* Set the machine number and endian. */
gas_cgen_cpu_desc = frv_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
CGEN_CPU_OPEN_ENDIAN,
@@ -559,26 +559,26 @@ frv_insert_vliw_insn (bfd_boolean count)
}
/* Identify the following cases:
-
+
1) A VLIW insn that contains both a branch and the branch destination.
This requires the insertion of two vliw instructions before the
branch. The first consists of two nops. The second consists of
a single nop.
-
+
2) A single instruction VLIW insn which is the destination of a branch
that is in the next VLIW insn. This requires the insertion of a vliw
insn containing two nops before the branch.
-
+
3) A double instruction VLIW insn which contains the destination of a
branch that is in the next VLIW insn. This requires the insertion of
a VLIW insn containing a single nop before the branch.
-
+
4) A single instruction VLIW insn which contains branch destination (x),
followed by a single instruction VLIW insn which does not contain
the branch to (x), followed by a VLIW insn which does contain the branch
to (x). This requires the insertion of a VLIW insn containing a single
nop before the VLIW instruction containing the branch.
-
+
*/
#define FRV_IS_NOP(insn) (insn.buffer[0] == FRV_NOP_PACK || insn.buffer[0] == FRV_NOP_NOPACK)
#define FRV_NOP_PACK 0x00880000 /* ori.p gr0,0,gr0 */
@@ -611,11 +611,11 @@ enum vliw_nop_type
{
/* A Vliw insn containing a single nop insn. */
VLIW_SINGLE_NOP,
-
+
/* A Vliw insn containing two nop insns. */
VLIW_DOUBLE_NOP,
- /* Two vliw insns. The first containing two nop insns.
+ /* Two vliw insns. The first containing two nop insns.
The second contain a single nop insn. */
VLIW_DOUBLE_THEN_SINGLE_NOP
};
@@ -697,7 +697,7 @@ frv_tomcat_shuffle (enum vliw_nop_type this_nop_type,
pack_prev = TRUE;
prev_insn = curr_insn;
curr_insn = curr_insn->next;
- }
+ }
while (curr_vliw && curr_vliw != vliw_to_split)
{
@@ -736,10 +736,10 @@ frv_tomcat_shuffle (enum vliw_nop_type this_nop_type,
frv_adjust_vliw_count (second_part);
single_nop->next = second_part;
-
+
vliw_to_split->next = single_nop;
prev_insn->next = NULL;
-
+
return_me = second_part;
frv_adjust_vliw_count (vliw_to_split);
}
@@ -773,13 +773,13 @@ frv_tomcat_shuffle (enum vliw_nop_type this_nop_type,
second_part->insn_list->type = VLIW_BRANCH_HAS_NOPS;
second_part->next = vliw_to_split->next;
frv_adjust_vliw_count (second_part);
-
+
double_nop->next = second_part;
-
+
vliw_to_split->next = single_nop;
prev_insn->next = NULL;
frv_adjust_vliw_count (vliw_to_split);
-
+
return_me = second_part;
}
break;
@@ -799,7 +799,7 @@ frv_tomcat_shuffle (enum vliw_nop_type this_nop_type,
prev_vliw->next = double_nop;
else
vliw_chain_top = double_nop;
-
+
single_nop->next = vliw_to_split;
return_me = vliw_to_split;
vliw_to_split->insn_list->type = VLIW_BRANCH_HAS_NOPS;
@@ -814,7 +814,7 @@ frv_tomcat_shuffle (enum vliw_nop_type this_nop_type,
}
/* The branch is in the middle of this vliw insn. Split into first and
- second parts. Insert the nop vliws in between. */
+ second parts. Insert the nop vliws in between. */
second_part->insn_list = insert_before_insn;
second_part->insn_list->type = VLIW_BRANCH_HAS_NOPS;
second_part->next = vliw_to_split->next;
@@ -881,7 +881,7 @@ workaround_top:
tomcat_doubles++;
goto workaround_top;
}
- else if (vliw2
+ else if (vliw2
&& vliw2->insn_count == 1
&& (temp_insn = frv_find_in_vliw (VLIW_BRANCH_TYPE, vliw3, vliw1->insn_list->sym)) != NULL)
{
@@ -1000,7 +1000,7 @@ fr550_check_insn_acc_range (frv_insn *insn, int low, int hi)
case FRV_INSN_CMQMULHU:
case FRV_INSN_MMACHS:
case FRV_INSN_MMRDHS:
- case FRV_INSN_CMMACHS:
+ case FRV_INSN_CMMACHS:
case FRV_INSN_MQMACHS:
case FRV_INSN_CMQMACHS:
case FRV_INSN_MQXMACHS:
@@ -1102,13 +1102,13 @@ md_assemble (char *str)
insn.insn = frv_cgen_assemble_insn
(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, &errmsg);
-
+
if (!insn.insn)
{
as_bad ("%s", errmsg);
return;
}
-
+
/* If the cpu is tomcat, then we need to insert nops to workaround
hardware limitations. We need to keep track of each vliw unit
and examine the length of the unit and the individual insns
@@ -1118,7 +1118,7 @@ md_assemble (char *str)
{
/* If we've just finished a VLIW insn OR this is a branch,
then start up a new frag. Fill it with nops. We will get rid
- of those that are not required after we've seen all of the
+ of those that are not required after we've seen all of the
instructions but before we start resolving fixups. */
if ( !FRV_IS_NOP (insn)
&& (frv_is_branch_insn (insn.insn) || insn.fields.f_pack))
@@ -1206,14 +1206,14 @@ md_assemble (char *str)
previous_vliw_chain = current_vliw_chain;
current_vliw_chain = NULL;
current_vliw_insn = NULL;
- }
+ }
}
}
/* The syntax in the manual says constants begin with '#'.
We just ignore it. */
-void
+void
md_operand (expressionS *expressionP)
{
if (* input_line_pointer == '#')
@@ -1275,8 +1275,8 @@ md_estimate_size_before_relax (fragS *fragP, segT segment ATTRIBUTE_UNUSED)
default:
case NOP_DELETE:
return 0;
- }
-}
+ }
+}
/* *fragP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size.
@@ -1299,7 +1299,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
case NOP_KEEP:
fragP->fr_fix = fragP->fr_var;
fragP->fr_var = 0;
- return;
+ return;
}
}
@@ -1369,7 +1369,7 @@ md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
case FRV_OPERAND_U12:
return BFD_RELOC_FRV_GPRELU12;
- default:
+ default:
break;
}
return BFD_RELOC_NONE;
@@ -1593,7 +1593,7 @@ frv_pic_ptr (int nbytes)
do
{
bfd_reloc_code_real_type reloc_type = BFD_RELOC_CTOR;
-
+
if (strncasecmp (input_line_pointer, "funcdesc(", 9) == 0)
{
input_line_pointer += 9;
@@ -1808,7 +1808,7 @@ frv_frob_label (symbolS *this_label)
vliw_insn_list_entry = frv_insert_vliw_insn(DONT_COUNT);
vliw_insn_list_entry->type = VLIW_LABEL_TYPE;
- vliw_insn_list_entry->sym = this_label;
+ vliw_insn_list_entry->sym = this_label;
}
fixS *
@@ -1828,6 +1828,6 @@ frv_cgen_record_fixup_exp (fragS *frag,
&& current_vliw_insn->type == VLIW_BRANCH_TYPE
&& exp != NULL)
current_vliw_insn->sym = exp->X_add_symbol;
-
+
return fixP;
}
diff --git a/gas/config/tc-h8300.c b/gas/config/tc-h8300.c
index 9ff8138..9609f2b 100644
--- a/gas/config/tc-h8300.c
+++ b/gas/config/tc-h8300.c
@@ -251,7 +251,7 @@ md_begin (void)
prev_buffer[0] = 0;
nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode);
-
+
h8_instructions = (struct h8_instruction *)
xmalloc (nopcodes * sizeof (struct h8_instruction));
@@ -398,36 +398,36 @@ parse_reg (char *src, op_type *mode, unsigned int *reg, int direction)
*reg = 7;
return len;
}
- if (len == 3 &&
- TOLOWER (src[0]) == 'c' &&
- TOLOWER (src[1]) == 'c' &&
+ if (len == 3 &&
+ TOLOWER (src[0]) == 'c' &&
+ TOLOWER (src[1]) == 'c' &&
TOLOWER (src[2]) == 'r')
{
*mode = CCR;
*reg = 0;
return len;
}
- if (len == 3 &&
- TOLOWER (src[0]) == 'e' &&
- TOLOWER (src[1]) == 'x' &&
+ if (len == 3 &&
+ TOLOWER (src[0]) == 'e' &&
+ TOLOWER (src[1]) == 'x' &&
TOLOWER (src[2]) == 'r')
{
*mode = EXR;
*reg = 1;
return len;
}
- if (len == 3 &&
- TOLOWER (src[0]) == 'v' &&
- TOLOWER (src[1]) == 'b' &&
+ if (len == 3 &&
+ TOLOWER (src[0]) == 'v' &&
+ TOLOWER (src[1]) == 'b' &&
TOLOWER (src[2]) == 'r')
{
*mode = VBR;
*reg = 6;
return len;
}
- if (len == 3 &&
- TOLOWER (src[0]) == 's' &&
- TOLOWER (src[1]) == 'b' &&
+ if (len == 3 &&
+ TOLOWER (src[0]) == 's' &&
+ TOLOWER (src[1]) == 'b' &&
TOLOWER (src[2]) == 'r')
{
*mode = SBR;
@@ -621,7 +621,7 @@ get_operand (char **ptr, struct h8_op *op, int direction)
/* Gross. Gross. ldm and stm have a format not easily handled
by get_operand. We deal with it explicitly here. */
- if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' &&
+ if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' &&
ISDIGIT (src[2]) && src[3] == '-' &&
TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6]))
{
@@ -764,7 +764,7 @@ get_operand (char **ptr, struct h8_op *op, int direction)
}
if (mode
&& src[len + 2] == ','
- && TOLOWER (src[len + 3]) != 'p'
+ && TOLOWER (src[len + 3]) != 'p'
&& TOLOWER (src[len + 4]) != 'c'
&& src[len + 5] != ')')
{
@@ -878,9 +878,9 @@ get_operand (char **ptr, struct h8_op *op, int direction)
*ptr = parse_exp (src + 1, op);
return;
}
- else if (strncmp (src, "mach", 4) == 0 ||
+ else if (strncmp (src, "mach", 4) == 0 ||
strncmp (src, "macl", 4) == 0 ||
- strncmp (src, "MACH", 4) == 0 ||
+ strncmp (src, "MACH", 4) == 0 ||
strncmp (src, "MACL", 4) == 0)
{
op->reg = TOLOWER (src[3]) == 'l';
@@ -979,7 +979,7 @@ get_mova_operands (char *op_end, struct h8_op *operand)
}
else if ((operand[1].mode & MODE) == LOWREG)
{
- switch (operand[1].mode & SIZE)
+ switch (operand[1].mode & SIZE)
{
case L_8:
operand[0].mode = (operand[0].mode & ~MODE) | INDEXB;
@@ -1483,12 +1483,12 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
if (!Hmode && this_try->opcode->available != AV_H8)
as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"),
this_try->opcode->name);
- else if (!Smode
- && this_try->opcode->available != AV_H8
+ else if (!Smode
+ && this_try->opcode->available != AV_H8
&& this_try->opcode->available != AV_H8H)
as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"),
this_try->opcode->name);
- else if (!SXmode
+ else if (!SXmode
&& this_try->opcode->available != AV_H8
&& this_try->opcode->available != AV_H8H
&& this_try->opcode->available != AV_H8S)
@@ -1748,7 +1748,7 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
/* To be compatible with the proposed H8 ELF format, we
want the relocation's offset to point to the first byte
that will be modified, not to the start of the instruction. */
-
+
if ((operand->mode & SIZE) == L_32)
{
where = 2;
@@ -1760,8 +1760,8 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
/* This jmp may be a jump or a branch. */
- check_operand (operand + i,
- SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff,
+ check_operand (operand + i,
+ SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff,
"@");
if (operand[i].exp.X_add_number & 1)
@@ -1891,7 +1891,7 @@ fix_operand_size (struct h8_op *operand, int size)
is safe. get_specific() will relax L_24 into L_32 where
necessary. */
if (Hmode
- && !Nmode
+ && !Nmode
&& ((((addressT) operand->exp.X_add_number + 0x8000)
& 0xffffffff) > 0xffff
|| operand->exp.X_add_symbol != 0
diff --git a/gas/config/tc-i370.c b/gas/config/tc-i370.c
index f9d49ac..6993f79 100644
--- a/gas/config/tc-i370.c
+++ b/gas/config/tc-i370.c
@@ -1185,7 +1185,7 @@ i370_elf_validate_fix (fixS *fixp, segT seg)
waste space padding out to alignments. The four pointers
longlong_poolP, word_poolP, etc. point to a symbol labeling the
start of each pool part.
-
+
lit_pool_num increments from zero to infinity and uniquely id's
-- its used to generate the *_poolP symbol name. */
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 2bdb769..6c910ed 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -797,7 +797,7 @@ static const arch_entry cpu_arch[] =
{ STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
CPU_BDVER4_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
- CPU_ZNVER1_FLAGS, 0, 0 },
+ CPU_ZNVER1_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
CPU_BTVER1_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
diff --git a/gas/config/tc-i860.c b/gas/config/tc-i860.c
index e3a0bdf..919ee00 100644
--- a/gas/config/tc-i860.c
+++ b/gas/config/tc-i860.c
@@ -90,7 +90,7 @@ static void s_enddual (int);
static void s_atmp (int);
static void s_align_wrapper (int);
static int i860_get_expression (char *);
-static bfd_reloc_code_real_type obtain_reloc_for_imm16 (fixS *, long *);
+static bfd_reloc_code_real_type obtain_reloc_for_imm16 (fixS *, long *);
#ifdef DEBUG_I860
static void print_insn (struct i860_it *);
#endif
@@ -173,7 +173,7 @@ s_atmp (int ignore ATTRIBUTE_UNUSED)
}
/* Handle ".align" directive depending on syntax mode.
- AT&T/SVR4 syntax uses the standard align directive. However,
+ AT&T/SVR4 syntax uses the standard align directive. However,
the Intel syntax additionally allows keywords for the alignment
parameter: ".align type", where type is one of {.short, .long,
.quad, .single, .double} representing alignments of 2, 4,
@@ -197,7 +197,7 @@ s_align_wrapper (int arg)
strncpy (parm, " 4", 7);
else if (strncmp (parm, ".double", 7) == 0)
strncpy (parm, " 8", 7);
-
+
while (*input_line_pointer == ' ')
++input_line_pointer;
}
@@ -895,7 +895,7 @@ i860_process_insn (char *str)
the_insn.expand = insn->expand;
fc++;
-
+
continue;
}
else
@@ -1482,7 +1482,7 @@ void
i860_check_label (symbolS *labelsym)
{
/* At this point, the current line pointer is sitting on the character
- just after the first colon on the label. */
+ just after the first colon on the label. */
if (target_intel_syntax && *input_line_pointer == ':')
{
S_SET_EXTERNAL (labelsym);
diff --git a/gas/config/tc-i960.c b/gas/config/tc-i960.c
index cd140fe..6321791 100644
--- a/gas/config/tc-i960.c
+++ b/gas/config/tc-i960.c
@@ -564,7 +564,7 @@ get_cdisp (char *dispP, /* Displacement as specified in source instruction. */
int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL). */
int var_frag,/* 1 if varying length code fragment should be emitted;
0 if an address fix should be emitted. */
- int callj) /* 1 if callj relocation should be done; else 0. */
+ int callj) /* 1 if callj relocation should be done; else 0. */
{
expressionS e; /* Parsed expression. */
fixS *fixP; /* Structure describing needed address fix. */
@@ -802,7 +802,7 @@ parse_regop (struct regop *regopP, /* Where to put description of register opera
}
/* get_ispec: parse a memory operand for an index specification
-
+
Here, an "index specification" is taken to be anything surrounded
by square brackets and NOT followed by anything else.
@@ -811,7 +811,7 @@ parse_regop (struct regop *regopP, /* Where to put description of register opera
static char *
get_ispec (char *textP) /* Pointer to memory operand from source instruction, no white space. */
-
+
{
/* Points to start of index specification. */
char *start;
@@ -1258,7 +1258,7 @@ parse_ldconst (char *arg[]) /* See above. */
ldconst 64,<reg> -> shlo 8,3,<reg>
ldconst -1,<reg> -> subo 1,0,<reg>
ldconst -31,<reg> -> subo 31,0,<reg>
-
+
Anything else becomes:
lda xxx,<reg>. */
n = offs (e);
@@ -2287,7 +2287,7 @@ parse_po (int po_num) /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC.
passed fixup structure. */
int
-reloc_callj (fixS *fixP) /* Relocation that can be done at assembly time. */
+reloc_callj (fixS *fixP) /* Relocation that can be done at assembly time. */
{
/* Points to the binary for the instruction being relocated. */
char *where;
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c
index f3c4120..d11570a 100644
--- a/gas/config/tc-ia64.c
+++ b/gas/config/tc-ia64.c
@@ -829,7 +829,7 @@ ar_is_only_in_integer_unit (int reg)
return reg >= 64 && reg <= 111;
}
-/* Determine if application register REGNUM resides only in the memory
+/* Determine if application register REGNUM resides only in the memory
unit (as opposed to the integer unit). */
static int
ar_is_only_in_memory_unit (int reg)
@@ -3687,7 +3687,7 @@ generate_unwind_image (const segT text_seg)
/* Set expression which points to start of unwind descriptor area. */
unwind.info = expr_build_dot ();
-
+
frag_var (rs_machine_dependent, size, size, 0, 0,
(offsetT) (long) unwind.personality_routine,
(char *) list);
@@ -6009,10 +6009,10 @@ operand_match (const struct ia64_opcode *idesc, int res_index, expressionS *e)
if (e->X_op == O_constant)
{
/* 5-bit signed scaled by 64 */
- if ((e->X_add_number <= ( 0xf << 6 ))
+ if ((e->X_add_number <= ( 0xf << 6 ))
&& (e->X_add_number >= -( 0x10 << 6 )))
{
-
+
/* Must be a multiple of 64 */
if ((e->X_add_number & 0x3f) != 0)
as_warn (_("stride must be a multiple of 64; lower 6 bits ignored"));
@@ -6028,7 +6028,7 @@ operand_match (const struct ia64_opcode *idesc, int res_index, expressionS *e)
if (e->X_op == O_constant)
{
/* 6-bit unsigned biased by 1 -- count 0 is meaningless */
- if ((e->X_add_number <= 64)
+ if ((e->X_add_number <= 64)
&& (e->X_add_number > 0) )
{
return OPERAND_MATCH;
@@ -6143,7 +6143,7 @@ parse_operands (struct ia64_opcode *idesc)
for (; ; ++i)
{
- if (i < NELEMS (CURR_SLOT.opnd))
+ if (i < NELEMS (CURR_SLOT.opnd))
{
sep = parse_operand_maybe_eval (CURR_SLOT.opnd + i, '=',
idesc->operands[i]);
@@ -7011,7 +7011,7 @@ emit_one_bundle (void)
as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
_("Missing '}' at end of file"));
}
-
+
know (md.num_slots_in_use < NUM_SLOTS);
t0 = end_of_insn_group | (template_val << 1) | (insn[0] << 5) | (insn[1] << 46);
@@ -9653,7 +9653,7 @@ update_qp_mutex (valueT mask)
print_prmask (qp_mutexes[i].prmask);
fprintf (stderr, "\n");
}
-
+
/* Deal with the old mutex with more than 3+ PRs only if
the new mutex on the same execution path with it.
@@ -9666,7 +9666,7 @@ update_qp_mutex (valueT mask)
if (add == 0
&& (qp_mutexes[i].prmask & mask) == mask)
add = 1;
-
+
qp_mutexes[i].prmask &= ~mask;
if (qp_mutexes[i].prmask & (qp_mutexes[i].prmask - 1))
{
@@ -9676,7 +9676,7 @@ update_qp_mutex (valueT mask)
i++;
}
}
-
+
if (keep == 0)
/* Remove the mutex. */
qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
@@ -10797,7 +10797,7 @@ md_assemble (char *str)
{
enum ia64_opnd opnd1, opnd2;
int rop;
-
+
opnd1 = idesc->operands[0];
opnd2 = idesc->operands[1];
if (opnd1 == IA64_OPND_AR3)
@@ -11700,7 +11700,7 @@ ia64_handle_align (fragS *fragp)
bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
p = fragp->fr_literal + fragp->fr_fix;
- /* If no paddings are needed, we check if we need a stop bit. */
+ /* If no paddings are needed, we check if we need a stop bit. */
if (!bytes && fragp->tc_frag_data)
{
if (fragp->fr_fix < 16)
@@ -11881,7 +11881,7 @@ dot_alias (int section)
h = (struct alias *) xmalloc (sizeof (struct alias));
as_where (&h->file, &h->line);
h->name = name;
-
+
error_string = hash_jam (ahash, alias, (void *) h);
if (error_string)
{
@@ -12001,7 +12001,7 @@ ia64_vms_note (void)
bname = xstrdup (lbasename (out_file_name));
if ((p = strrchr (bname, '.')))
*p = '\0';
-
+
/* VMS note header is 24 bytes long. */
p = frag_more (8 + 8 + 8);
number_to_chars_littleendian (p + 0, 8, 8);
diff --git a/gas/config/tc-ip2k.c b/gas/config/tc-ip2k.c
index 788a863..4f4cffe 100644
--- a/gas/config/tc-ip2k.c
+++ b/gas/config/tc-ip2k.c
@@ -19,7 +19,7 @@
Boston, MA 02110-1301, USA. */
#include "as.h"
-#include "subsegs.h"
+#include "subsegs.h"
#include "symcat.h"
#include "opcodes/ip2k-desc.h"
#include "opcodes/ip2k-opc.h"
@@ -52,7 +52,7 @@ ip2k_insn;
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
-const char line_separator_chars[] = "";
+const char line_separator_chars[] = "";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
@@ -119,7 +119,7 @@ enum options
OPTION_CPU_IP2022EXT
};
-struct option md_longopts[] =
+struct option md_longopts[] =
{
{ "mip2022", no_argument, NULL, OPTION_CPU_IP2022 },
{ "mip2022ext", no_argument, NULL, OPTION_CPU_IP2022EXT },
@@ -164,7 +164,7 @@ void
md_begin (void)
{
/* Initialize the `cgen' interface. */
-
+
/* Set the machine number and endian. */
gas_cgen_cpu_desc = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_MACHS,
ip2k_mach_bitmask,
@@ -247,7 +247,7 @@ md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
{
as_fatal (_("relaxation not supported\n"));
return 1;
-}
+}
/* *fragP has been relaxed to its final size, and now needs to have
@@ -420,7 +420,7 @@ ip2k_elf_section_flags (flagword flags,
word alignment should be forced. */
if (flags & SEC_CODE)
force_code_align = 1;
-
+
return flags;
}
diff --git a/gas/config/tc-m32c.c b/gas/config/tc-m32c.c
index f7b70a4..2c8136b 100644
--- a/gas/config/tc-m32c.c
+++ b/gas/config/tc-m32c.c
@@ -20,7 +20,7 @@
Boston, MA 02111-1307, USA. */
#include "as.h"
-#include "subsegs.h"
+#include "subsegs.h"
#include "symcat.h"
#include "opcodes/m32c-desc.h"
#include "opcodes/m32c-opc.h"
@@ -141,7 +141,7 @@ void
md_show_usage (FILE * stream)
{
fprintf (stream, _(" M32C specific command line options:\n"));
-}
+}
static void
s_bss (int ignore ATTRIBUTE_UNUSED)
@@ -261,21 +261,21 @@ m32c_indirect_operand (char *str)
if (s[0] == '[' && s[1] == '[')
indirection[operand] = relative;
}
-
+
if (indirection[1] == none && indirection[2] == none)
return FALSE;
-
+
operand = 1;
ns_len = strlen (str);
new_str = (char*) xmalloc (ns_len);
ns = new_str;
ns_end = ns + ns_len;
-
+
for (s = str; *s; s++)
{
if (s[0] == ',')
operand = 2;
-
+
if (s[0] == '[' && ! brace_n[operand])
{
brace_n[operand] += 1;
@@ -283,7 +283,7 @@ m32c_indirect_operand (char *str)
if (indirection[operand] != none)
continue;
}
-
+
else if (s[0] == '[' && brace_n[operand])
{
brace_n[operand] += 1;
@@ -315,7 +315,7 @@ m32c_indirect_operand (char *str)
{
fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]);
}
-
+
if (indirection[1] != none && indirection[2] != none)
md_assemble ("src-dest-indirect");
else if (indirection[1] != none)
@@ -345,7 +345,7 @@ md_assemble (char * str)
insn.insn = m32c_cgen_assemble_insn
(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
-
+
if (!insn.insn)
{
as_bad ("%s", errmsg);
@@ -398,7 +398,7 @@ md_assemble (char * str)
/* The syntax in the manual says constants begin with '#'.
We just ignore it. */
-void
+void
md_operand (expressionS * exp)
{
/* In case of a syntax error, escape back to try next syntax combo. */
@@ -595,7 +595,7 @@ md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED)
}
return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where);
-}
+}
/* *fragP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size.
@@ -1063,9 +1063,9 @@ tc_gen_reloc (asection *sec, fixS *fx)
|| fx->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
{
arelent * reloc;
-
+
reloc = xmalloc (sizeof (* reloc));
-
+
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy);
reloc->address = fx->fx_frag->fr_address + fx->fx_where;
diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c
index b080f9e..38da4b5 100644
--- a/gas/config/tc-m32r.c
+++ b/gas/config/tc-m32r.c
@@ -2198,9 +2198,9 @@ tc_gen_reloc (asection * section, fixS * fixP)
{
arelent * reloc;
bfd_reloc_code_real_type code;
-
+
reloc = xmalloc (sizeof (* reloc));
-
+
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
@@ -2215,7 +2215,7 @@ tc_gen_reloc (asection * section, fixS * fixP)
bfd_set_error (bfd_error_bad_value);
}
}
-
+
code = fixP->fx_r_type;
if (pic_code)
{
@@ -2267,7 +2267,7 @@ printf("%s",bfd_get_reloc_code_name(code));
printf(" => %s",bfd_get_reloc_code_name(code));
#endif
}
-
+
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
#ifdef DEBUG_PIC
@@ -2281,7 +2281,7 @@ printf(" => %s\n",reloc->howto->name);
fixP->fx_r_type, bfd_get_reloc_code_name (code));
return NULL;
}
-
+
/* Use fx_offset for these cases. */
if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
@@ -2299,7 +2299,7 @@ printf(" => %s\n",reloc->howto->name);
reloc->addend = fixP->fx_offset;
else
reloc->addend = fixP->fx_addnumber;
-
+
return reloc;
}
diff --git a/gas/config/tc-m32r.h b/gas/config/tc-m32r.h
index 1114c30..6f350e1 100644
--- a/gas/config/tc-m32r.h
+++ b/gas/config/tc-m32r.h
@@ -108,7 +108,7 @@ extern void m32r_elf_section_change_hook (void);
#define md_flush_pending_output() m32r_flush_pending_output ()
extern void m32r_flush_pending_output (void);
-
+
#define elf_tc_final_processing m32r_elf_final_processing
extern void m32r_elf_final_processing (void);
diff --git a/gas/config/tc-m68hc11.c b/gas/config/tc-m68hc11.c
index a12d106..a2aa424 100644
--- a/gas/config/tc-m68hc11.c
+++ b/gas/config/tc-m68hc11.c
@@ -2141,8 +2141,8 @@ build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn)
if (!check_range (val, M6812_OP_IDX))
as_bad (_("Offset out of 16-bit range: %ld."), val);
- if (move_insn && !(val >= -16 && val <= 15)
- && ((!(mode & M6812_OP_IDX) && !(mode & M6812_OP_D_IDX_2))
+ if (move_insn && !(val >= -16 && val <= 15)
+ && ((!(mode & M6812_OP_IDX) && !(mode & M6812_OP_D_IDX_2))
|| !(current_architecture & cpu9s12x)))
{
as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
@@ -2420,7 +2420,7 @@ build_insn_xg (struct m68hc11_opcode *opcode,
f = m68hc11_new_insn (1);
number_to_chars_bigendian (f, opcode->opcode >> 8, 1); /* High byte. */
fixup8_xg (&operands[0].exp, format, M68XG_OP_REL9);
- }
+ }
else if (format & M68XG_OP_REL10)
{
f = m68hc11_new_insn (1);
@@ -2949,7 +2949,7 @@ md_assemble (char *str)
}
else
as_bad ("No opcode found\n");
-
+
return;
}
else
@@ -2973,7 +2973,7 @@ md_assemble (char *str)
{
opcode_local.opcode |= (operands[0].exp.X_add_number);
operands[0].mode = M68XG_OP_IMM3;
-
+
opcode = find (opc, operands, 1);
if (opcode)
{
@@ -3067,7 +3067,7 @@ md_assemble (char *str)
if (opc->format & (M68XG_OP_REL9 | M68XG_OP_REL10))
{
- opcode_local.format = opc->format;
+ opcode_local.format = opc->format;
input_line_pointer = skip_whites (input_line_pointer);
expression (&operands[0].exp);
if (operands[0].exp.X_op == O_illegal)
@@ -3093,12 +3093,12 @@ md_assemble (char *str)
if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r')
|| (*input_line_pointer == '\0'))
return; /* nothing left */
-
+
if (*input_line_pointer == '#')
{
as_bad ("No register specified before hash\n");
return;
- }
+ }
/* first operand is expected to be a register */
if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r'))
@@ -3165,12 +3165,12 @@ md_assemble (char *str)
if (opcode)
opcode_local.opcode = opcode->opcode
| (operands[0].reg1 << 8);
-
+
if (operands[0].exp.X_op != O_constant)
as_bad ("Only constants supported at for IMM4 mode\n");
else
{
- if (check_range
+ if (check_range
(operands[0].exp.X_add_number,M68XG_OP_R_IMM4))
opcode_local.opcode
|= (operands[0].exp.X_add_number << 4);
@@ -3226,7 +3226,7 @@ md_assemble (char *str)
com RD, RS alias for xnor RD,R0,RS
mov RD, RS alias for or RD, R0, RS
neg RD, RS alias for sub RD, R0, RS */
- opcode_local.opcode = opcode->opcode
+ opcode_local.opcode = opcode->opcode
| (operands[0].reg1 << 8) | (operands[1].reg1 << 2);
}
else if ((strncmp (opc->opcode->name, "cmp",3) == 0)
@@ -3235,7 +3235,7 @@ md_assemble (char *str)
/* special cases for:
cmp RS1, RS2 alias for sub R0, RS1, RS2
cpc RS1, RS2 alias for sbc R0, RS1, RS2 */
- opcode_local.opcode = opcode->opcode
+ opcode_local.opcode = opcode->opcode
| (operands[0].reg1 << 5) | (operands[1].reg1 << 2);
}
else
@@ -3277,7 +3277,7 @@ md_assemble (char *str)
opcode = find (opc, operands, 1);
if (opcode)
{
- opcode_local.opcode = opcode->opcode
+ opcode_local.opcode = opcode->opcode
| (operands[0].reg1 << 8) | (operands[1].reg1 << 5)
| (operands[2].reg1 << 2);
opcode_local.format = M68XG_OP_NONE;
@@ -3314,7 +3314,7 @@ md_assemble (char *str)
}
input_line_pointer = skip_whites (input_line_pointer);
-
+
if (*input_line_pointer != ',')
{
as_bad (_("Missing operand."));
@@ -3349,7 +3349,7 @@ md_assemble (char *str)
{
input_line_pointer++;
}
-
+
/* Ok so far, can only be one mode. */
opcode_local.format = M68XG_OP_R_R_OFFS5;
operands[0].mode = M68XG_OP_R_R_OFFS5;
@@ -4433,7 +4433,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
value);
if (value >= 0)
where[0] |= value;
- else
+ else
where[0] |= (0x10 | (16 + value));
break;
@@ -4445,7 +4445,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
/* sign bit already in xb postbyte */
if (value >= 0)
where[1] = value;
- else
+ else
where[1] = (256 + value);
break;
diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c
index 443bf20..acfe349 100644
--- a/gas/config/tc-m68k.c
+++ b/gas/config/tc-m68k.c
@@ -654,13 +654,13 @@ static const struct m68k_cpu m68k_cpus[] =
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
-
+
{mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
{mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
{mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
@@ -671,20 +671,20 @@ static const struct m68k_cpu m68k_cpus[] =
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
-
+
{mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
@@ -692,18 +692,18 @@ static const struct m68k_cpu m68k_cpus[] =
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
-
+
{mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
-
+
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
-
+
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
{mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
@@ -718,7 +718,7 @@ static const struct m68k_cpu m68k_cpus[] =
{mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
{mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
{mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
-
+
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
@@ -726,7 +726,7 @@ static const struct m68k_cpu m68k_cpus[] =
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
-
+
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
@@ -734,7 +734,7 @@ static const struct m68k_cpu m68k_cpus[] =
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
-
+
{fido_a, fido_ctrl, "fidoa", 0},
{fido_a, fido_ctrl, "fido", 1},
@@ -870,7 +870,7 @@ relax_typeS md_relax_table[] =
{ 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
{ 0, 0, 4, 0 },
{ 1, 1, 0, 0 },
-
+
{ 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
{ 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
{ 0, 0, 10, 0 },
@@ -1998,7 +1998,7 @@ m68k_ip (char *instring)
else
{
const enum m68k_register *rp;
-
+
for (rp = control_regs; *rp; rp++)
{
if (*rp == opP->reg)
@@ -2410,7 +2410,7 @@ m68k_ip (char *instring)
{
const struct m68k_cpu *alias;
int seen_master = 0;
-
+
if (any)
APPEND (", ");
any = 0;
@@ -2468,7 +2468,7 @@ m68k_ip (char *instring)
{
int have_disp = 0;
int use_pl = 0;
-
+
/* This switch is a doozy.
Watch the first step; its a big one! */
switch (s[0])
@@ -3128,7 +3128,7 @@ m68k_ip (char *instring)
case 'B':
tmpreg = get_num (&opP->disp, 90);
-
+
switch (s[1])
{
case 'B':
@@ -3148,15 +3148,15 @@ m68k_ip (char *instring)
case 'g': /* Conditional branch */
have_disp = HAVE_LONG_CALL (current_architecture);
goto var_branch;
-
+
case 'b': /* Unconditional branch */
have_disp = HAVE_LONG_BRANCH (current_architecture);
use_pl = LONG_BRANCH_VIA_COND (current_architecture);
goto var_branch;
-
+
case 's': /* Unconditional subroutine */
have_disp = HAVE_LONG_CALL (current_architecture);
-
+
var_branch:
if (subs (&opP->disp) /* We can't relax it. */
#ifdef OBJ_ELF
@@ -3170,7 +3170,7 @@ m68k_ip (char *instring)
as_warn (_("Can't use long branches on this architecture"));
goto long_branch;
}
-
+
/* This could either be a symbol, or an absolute
address. If it's an absolute address, turn it into
an absolute jump right here and keep it out of the
@@ -3286,7 +3286,7 @@ m68k_ip (char *instring)
case 'e': /* EMAC ACCx, reg/reg. */
install_operand (s[1], opP->reg - ACC);
break;
-
+
case 'E': /* Ignore it. */
break;
@@ -4332,7 +4332,7 @@ md_assemble (char *str)
}
if (!initialized)
m68k_init_arch ();
-
+
/* In MRI mode, the instruction and operands are separated by a
space. Anything following the operands is a comment. The label
has already been removed. */
@@ -4625,7 +4625,7 @@ md_begin (void)
slak->m_operands = ins->args;
slak->m_arch = ins->arch;
slak->m_opcode = ins->opcode;
-
+
/* In most cases we can determine the number of opcode words
by checking the second word of the mask. Unfortunately
some instructions have 2 opcode words, but no fixed bits
@@ -4641,7 +4641,7 @@ md_begin (void)
else
slak->m_codenum = 1;
slak->m_opnum = strlen (slak->m_operands) / 2;
-
+
if (i + 1 != m68k_numopcodes
&& !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
{
@@ -7336,7 +7336,7 @@ s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
ignore_rest_of_line ();
return;
}
-
+
name = input_line_pointer;
while (*input_line_pointer && !ISSPACE(*input_line_pointer))
input_line_pointer++;
@@ -7344,7 +7344,7 @@ s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
*input_line_pointer = 0;
m68k_set_cpu (name, 1, 0);
-
+
*input_line_pointer = saved_char;
demand_empty_rest_of_line ();
return;
@@ -7364,7 +7364,7 @@ s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
ignore_rest_of_line ();
return;
}
-
+
name = input_line_pointer;
while (*input_line_pointer && *input_line_pointer != ','
&& !ISSPACE (*input_line_pointer))
@@ -7389,7 +7389,7 @@ s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
}
while (m68k_set_extension (name, 1, 0));
}
-
+
*input_line_pointer = saved_char;
demand_empty_rest_of_line ();
return;
@@ -7418,7 +7418,7 @@ m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
*negated = 1;
}
}
-
+
/* Remove 'm' or 'mc' prefix from 68k variants. */
if (allow_m)
{
@@ -7658,7 +7658,7 @@ m[...]
[diff truncated at 100000 bytes]