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[binutils-gdb] Change ARM symbol name verification code so that it only triggers when the form "name = val" is used


https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ae8714c2712ef9a179cfa9158a289bd400c0ad97

commit ae8714c2712ef9a179cfa9158a289bd400c0ad97
Author: Nick Clifton <nickc@redhat.com>
Date:   Fri May 8 17:28:26 2015 +0100

    Change ARM symbol name verification code so that it only triggers when the form "name = val" is used.
    
    	PR gas/18347
    	* config/tc-arm.h (TC_EQUAL_IN_INSN): Define.
    	* config/tc-arm.c (arm_tc_equal_in_insn): New function.  Move
    	the symbol name checking code to here from...
    	(md_undefined_symbo): ... here.

Diff:
---
 gas/ChangeLog                   |  8 +++++
 gas/config/tc-arm.c             | 65 ++++++++++++++++++++---------------------
 gas/config/tc-arm.h             |  3 ++
 gas/testsuite/ChangeLog         |  7 +++++
 gas/testsuite/gas/arm/pr18347.l |  2 +-
 gas/testsuite/gas/arm/pr18347.s | 11 +++++++
 6 files changed, 61 insertions(+), 35 deletions(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9bf6931..19bdb16 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2015-05-08  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/18347
+	* config/tc-arm.h (TC_EQUAL_IN_INSN): Define.
+	* config/tc-arm.c (arm_tc_equal_in_insn): New function.  Move
+	the symbol name checking code to here from...
+	(md_undefined_symbo): ... here.
+
 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/tc-i386.c (no_shared): New.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 2f6fea6..683774f 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -21625,29 +21625,9 @@ md_pcrel_from_section (fixS * fixP, segT seg)
 
 static bfd_boolean flag_warn_syms = TRUE;
 
-/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
-   Otherwise we have no need to default values of symbols.  */
-
-symbolS *
-md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+bfd_boolean
+arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
 {
-#ifdef OBJ_ELF
-  if (name[0] == '_' && name[1] == 'G'
-      && streq (name, GLOBAL_OFFSET_TABLE_NAME))
-    {
-      if (!GOT_symbol)
-	{
-	  if (symbol_find (name))
-	    as_bad (_("GOT already in the symbol table"));
-
-	  GOT_symbol = symbol_new (name, undefined_section,
-				   (valueT) 0, & zero_address_frag);
-	}
-
-      return GOT_symbol;
-    }
-#endif
-
   /* PR 18347 - Warn if the user attempts to create a symbol with the same
      name as an ARM instruction.  Whilst strictly speaking it is allowed, it
      does mean that the resulting code might be very confusing to the reader.
@@ -21662,17 +21642,8 @@ md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
 
      Note - ARM instructions are case-insensitive but the strings in the hash
      table are all stored in lower case, so we must first ensure that name is
-     lower case too.
-
-     Some names are problematical.  Several gas tests for example use:
-
-       b:
-
-     as a label, but of course this matches the branch instruction.  For now
-     we punt and only check names longer than 1.
-
-     FIXME: Should this be made into generic code for all targets ?  */
-  if (flag_warn_syms && arm_ops_hsh && strlen (name) > 1)
+     lower case too.  */
+  if (flag_warn_syms && arm_ops_hsh)
     {
       char * nbuf = strdup (name);
       char * p;
@@ -21688,12 +21659,38 @@ md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
 	  /* Only warn about the symbol once.  To keep the code
 	     simple we let hash_insert do the lookup for us.  */
 	  if (hash_insert (already_warned, name, NULL) == NULL)
-	    as_warn (_("[-mwarn-syms]: Symbol '%s' matches an ARM instruction - is this intentional ?"), name);
+	    as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
 	}
       else
 	free (nbuf);
     }
   
+  return FALSE;
+}
+
+/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
+   Otherwise we have no need to default values of symbols.  */
+
+symbolS *
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+{
+#ifdef OBJ_ELF
+  if (name[0] == '_' && name[1] == 'G'
+      && streq (name, GLOBAL_OFFSET_TABLE_NAME))
+    {
+      if (!GOT_symbol)
+	{
+	  if (symbol_find (name))
+	    as_bad (_("GOT already in the symbol table"));
+
+	  GOT_symbol = symbol_new (name, undefined_section,
+				   (valueT) 0, & zero_address_frag);
+	}
+
+      return GOT_symbol;
+    }
+#endif
+
   return NULL;
 }
 
diff --git a/gas/config/tc-arm.h b/gas/config/tc-arm.h
index 2216267..22e9027 100644
--- a/gas/config/tc-arm.h
+++ b/gas/config/tc-arm.h
@@ -389,3 +389,6 @@ extern char arm_comment_chars[];
 
 #define tc_line_separator_chars arm_line_separator_chars
 extern char arm_line_separator_chars[];
+
+#define TC_EQUAL_IN_INSN(c, s) arm_tc_equal_in_insn ((c), (s))
+extern bfd_boolean arm_tc_equal_in_insn (int, char *);
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d63f48a..b3efb8f 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2015-05-08  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/18347
+	* gas/arm/pr18347.s: Add tests of other symbol assignments which
+	should not generate the warning.
+	* gas/arm/pr18347.l: Update expected output.
+
 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/i386.exp: Run relax-4 and x86-64-relax-3.
diff --git a/gas/testsuite/gas/arm/pr18347.l b/gas/testsuite/gas/arm/pr18347.l
index 12e223d..9ef0da8 100644
--- a/gas/testsuite/gas/arm/pr18347.l
+++ b/gas/testsuite/gas/arm/pr18347.l
@@ -1,2 +1,2 @@
 [^:]*: Assembler messages:
-[^:]*:2: Warning: \[-mwarn-syms\]: Symbol 'LDR' matches an ARM instruction - is this intentional \?
+[^:]*:2: Warning: \[-mwarn-syms\]: Assignment makes a symbol match an ARM instruction: LDR
diff --git a/gas/testsuite/gas/arm/pr18347.s b/gas/testsuite/gas/arm/pr18347.s
index ac22b45..591d69b 100644
--- a/gas/testsuite/gas/arm/pr18347.s
+++ b/gas/testsuite/gas/arm/pr18347.s
@@ -1,3 +1,14 @@
     MOV r1, r0
     LDR =garbage // no destination register
     MOV r2, r3
+
+	// The warning should only be triggered by a "foo = bar"
+	// type of expression.  Other ways of creating symbols
+	// should allow ARM instruction names.
+b:
+   nop
+
+.set   bx,  fred
+.equiv ldr, bar
+.eqv   nop, fred
+.equ   mov, foo


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