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src cpu/ChangeLog cpu/m32c.cpu opcodes/ChangeL ...
- From: dj at sourceware dot org
- To: binutils-cvs at sources dot redhat dot com
- Date: 22 Oct 2005 00:03:13 -0000
- Subject: src cpu/ChangeLog cpu/m32c.cpu opcodes/ChangeL ...
CVSROOT: /cvs/src
Module name: src
Changes by: dj@sourceware.org 2005-10-22 00:03:13
Modified files:
cpu : ChangeLog m32c.cpu
opcodes : ChangeLog m32c-asm.c m32c-desc.c m32c-desc.h
m32c-dis.c m32c-ibld.c m32c-opc.c m32c-opc.h
Log message:
[cpu]
* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
(indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
indexld, indexls): .w variants have `1' bit.
(rot32.b): QI, not SI.
(rot32.w): HI, not SI.
(xchg16): HI for .w variant.
[opcodes]
* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cpu/ChangeLog.diff?cvsroot=src&r1=1.51&r2=1.52
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cpu/m32c.cpu.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.853&r2=1.854
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32c-asm.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32c-desc.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32c-desc.h.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32c-dis.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32c-ibld.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32c-opc.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32c-opc.h.diff?cvsroot=src&r1=1.2&r2=1.3