XSTORMY16 Architecture Documentation
DISCLAIMER: This documentation is derived from the cgen cpu description
of this architecture, and does not represent official documentation
of the chip maker.
In cgen-parlance, an architecture consists of machines and models.
A `machine' is the specification of a variant of the architecture,
and a `model' is the implementation of that specification.
Typically there is a one-to-one correspondance between machine and model.
The distinction allows for separation of what application programs see
(the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code.
Chip variants that are quite dissimilar can be treated separately by the
generated code even though they're both members of the same architecture.
XSTORMY16 Architecture
This section describes various things about the cgen description of
the XSTORMY16 architecture. Familiarity with cgen cpu descriptions
is assumed.
Bit number orientation (arch.lsb0?): msb = 0
ISA description
-
xstormy16 - Xstormy16 instruction set
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:
CPU Families
-
xstormy16 - Xstormy16 CPU core
Machines:
-
xstormy16 - Xstormy16 CPU core
Models:
Machine variants
xstormy16 - Xstormy16 CPU core
-
bfd-name: xstormy16
-
isas: xstormy16
Model variants
Registers
h-Rb - Rb registers
-
machines: base
-
bitsize: 32
-
array: [8]
names:
r8 |
0 |
r9 |
1 |
r10 |
2 |
r11 |
3 |
r12 |
4 |
r13 |
5 |
r14 |
6 |
r15 |
7 |
psw |
6 |
sp |
7 |
h-Rbj - Rbj registers
-
machines: base
-
bitsize: 32
-
array: [2]
names:
r8 |
0 |
r9 |
1 |
r10 |
2 |
r11 |
3 |
r12 |
4 |
r13 |
5 |
r14 |
6 |
r15 |
7 |
psw |
6 |
sp |
7 |
h-Rpsw - Register number field of the PSW
-
machines: base
-
bitsize: 32
h-cy -
-
machines: base
-
bitsize: 32
h-gr - registers
-
machines: base
-
bitsize: 32
-
array: [16]
names:
r0 |
0 |
r1 |
1 |
r2 |
2 |
r3 |
3 |
r4 |
4 |
r5 |
5 |
r6 |
6 |
r7 |
7 |
r8 |
8 |
r9 |
9 |
r10 |
10 |
r11 |
11 |
r12 |
12 |
r13 |
13 |
r14 |
14 |
r15 |
15 |
psw |
14 |
sp |
15 |
h-hc -
-
machines: base
-
bitsize: 32
h-ov -
-
machines: base
-
bitsize: 32
h-pc - program counter
-
machines: base
-
bitsize: 32
h-pt -
-
machines: base
-
bitsize: 32
h-s -
-
machines: base
-
bitsize: 32
h-z16 -
-
machines: base
-
bitsize: 32
h-z8 -
-
machines: base
-
bitsize: 32
Assembler supplemental
This documentation was machine generated from the cgen cpu description
files for this architecture.
http://sources.redhat.com/cgen/