OPENRISC Architecture Documentation
DISCLAIMER: This documentation is derived from the cgen cpu description
of this architecture, and does not represent official documentation
of the chip maker.
In cgen-parlance, an architecture consists of machines and models.
A `machine' is the specification of a variant of the architecture,
and a `model' is the implementation of that specification.
Typically there is a one-to-one correspondance between machine and model.
The distinction allows for separation of what application programs see
(the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code.
Chip variants that are quite dissimilar can be treated separately by the
generated code even though they're both members of the same architecture.
OPENRISC Architecture
This section describes various things about the cgen description of
the OPENRISC architecture. Familiarity with cgen cpu descriptions
is assumed.
Bit number orientation (arch.lsb0?): lsb = 0
ISA description
-
or32 -
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:
- setup-semantics:
((reg h-delay-insn)
(add pc (attr (current-insn) 4)))
CPU Families
-
openriscbf - OpenRISC base family
Machines:
-
openrisc - Generic OpenRISC cpu
Models:
-
openrisc-1 - OpenRISC generic model
-
or1300 - OpenRISC 1300
Models:
-
or1320-1 - OpenRISC 1320 model
Machine variants
openrisc - Generic OpenRISC cpu
-
bfd-name: openrisc
-
isas: or32
or1300 - OpenRISC 1300
-
bfd-name: openrisc:1300
-
isas: or32
Model variants
openrisc-1 - OpenRISC generic model
or1320-1 - OpenRISC 1320 model
Registers
h-cbit - condition bit
-
machines: base
-
bitsize: 1
h-delay-insn - delay insn addr
-
machines: base
-
bitsize: 32
h-gr - general registers
-
machines: base
-
bitsize: 32
-
array: [32]
names:
r0 |
0 |
r1 |
1 |
r2 |
2 |
r3 |
3 |
r4 |
4 |
r5 |
5 |
r6 |
6 |
r7 |
7 |
r8 |
8 |
r9 |
9 |
r10 |
10 |
r11 |
11 |
r12 |
12 |
r13 |
13 |
r14 |
14 |
r15 |
15 |
r16 |
16 |
r17 |
17 |
r18 |
18 |
r19 |
19 |
r20 |
20 |
r21 |
21 |
r22 |
22 |
r23 |
23 |
r24 |
24 |
r25 |
25 |
r26 |
26 |
r27 |
27 |
r28 |
28 |
r29 |
29 |
r30 |
30 |
r31 |
31 |
lr |
11 |
sp |
1 |
fp |
2 |
h-pc - program counter
-
machines: base
-
bitsize: 32
h-sr - special registers
-
machines: base
-
bitsize: 32
-
array: [131072]
Assembler supplemental
This documentation was machine generated from the cgen cpu description
files for this architecture.
http://sources.redhat.com/cgen/